CN113687550A - Array substrate, preparation method thereof and electronic paper display device - Google Patents
Array substrate, preparation method thereof and electronic paper display device Download PDFInfo
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
- G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/1675—Constructional details
- G02F1/1676—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
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- G02F1/16766—Electrodes for active matrices
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
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Abstract
The embodiment of the invention discloses an array substrate, a preparation method thereof and an electronic paper display device. In a specific embodiment, an array substrate for an electronic paper display device includes a gate line and a data line on a substrate, the gate line and the data line intersect to define a plurality of pixel regions, at least a portion of the pixel regions include a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode, and a second pixel electrode on the substrate, a first electrode of the first thin film transistor and a second electrode of the second thin film transistor are respectively connected to the first pixel electrode, a second electrode of the first thin film transistor is connected to the data line, a first electrode of the second thin film transistor is connected to the second pixel electrode, and a gate of the first thin film transistor and a gate of the second thin film transistor are respectively connected to the gate line. The embodiment can reduce the leakage speed of the storage capacitor, thereby increasing the capability of keeping the voltage of the pixel electrode stable.
Description
Technical Field
The invention relates to the technical field of display. And more particularly, to an array substrate, a method for manufacturing the same, and an electronic paper display device.
Background
Electronic paper display screens have been rapidly developed due to their low power consumption, foldable bending, fine and smooth picture display, wide viewing angle, and the like. The electronic paper display screen achieves a visual effect by reflecting ambient light.
In an array substrate of an electronic paper display screen in the prior art, each pixel structure comprises a data line, a gate line and a pixel electrode, a thin film transistor is formed at the intersection part of the data line and the gate line, the gate of the thin film transistor is connected with the gate line, the source of the thin film transistor is connected with the data line, and the drain of the thin film transistor is connected with the pixel electrode.
The pixel structure and the common electrode in the prior art form a structure that: the pixel electrode comprises a grid line and a data line, a storage capacitor is formed between the pixel electrode and the common electrode which are connected with the thin film transistor, when the grid voltage is normally opened, the thin film transistor is opened by the high level of the grid, and the current flows to the thin film transistor and the pixel electrode through the data line; when the grid voltage is closed, the source electrode of the thin film transistor has no voltage, the drain electrode voltage is kept, a large voltage difference exists between the source electrode and the drain electrode of the thin film transistor at the moment, the leakage current of the thin film transistor is large, the residual direct current component is increased when the pixel discharges, the charge loss of the storage capacitor is caused, and the voltage of the pixel electrode is attenuated.
Disclosure of Invention
The invention aims to provide an array substrate, a preparation method thereof and an electronic paper display device, so as to solve at least one of the problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides in a first aspect an array substrate for an electronic paper display device, the array substrate comprising gate lines and data lines on a substrate, the gate lines and the data lines crossing to define a plurality of pixel regions,
at least part of the pixel region comprises a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode which are positioned on the substrate, wherein a first pole of the first thin film transistor and a second pole of the second thin film transistor are respectively connected with the first pixel electrode, a second pole of the first thin film transistor is connected with the data line, a first pole of the second thin film transistor is connected with the second pixel electrode, and a grid electrode of the first thin film transistor and a grid electrode of the second thin film transistor are respectively connected with the grid line;
the first pixel electrode, the common electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between an orthographic projection of the second pixel electrode on the substrate and an orthographic projection of the common electrode on the substrate and an orthographic projection of the first pixel electrode on the substrate, the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor.
According to the array substrate provided by the first aspect of the invention, the first pixel electrode, the common electrode and the second pixel electrode are formed, so that even if the second pixel electrode and the common electrode form a storage capacitor, the common electrode and the first pixel electrode form a compensation capacitor, the electric leakage speed of the storage capacitor can be reduced, and the capacity of keeping the voltage of the pixel electrode stable is increased; meanwhile, the orthographic projection of the second pixel electrode on the substrate respectively has an overlapping region with the orthographic projection of the common electrode on the substrate and the orthographic projection of the first pixel electrode on the substrate, so that the storage capacitor and the compensation capacitor can be designed in a laminated mode, the extra plane space is not occupied, and the pixel array substrate is suitable for high PPI products.
Optionally, an orthographic projection of the second pixel electrode on the substrate covers an orthographic projection of the common electrode on the substrate, and an orthographic projection of the second pixel electrode on the substrate covers an orthographic projection of the first pixel electrode on the substrate.
This optional mode can make storage capacitor and compensating capacitor realize the full overlapping stack design, and storage capacitor and compensating capacitor's area is great, and the bigger compensating capacitor area is better to the inhibitory effect of leakage current to make pixel electrode voltage keep stable ability better.
Optionally, the first pixel electrode, the first pole of the first thin film transistor, the second pole of the second thin film transistor, and the data line are disposed in the same layer, wherein the first pixel electrode includes an electrode plate forming portion and an extension portion, the extension portion extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor.
According to the optional mode, the first pixel electrode and the data line, the source electrode and the drain electrode of the first thin film transistor and the source electrode and the drain electrode of the second thin film transistor are located on the same layer, the space of the layer can be fully utilized, extra plane space is not occupied, and the pixel structure is suitable for high PPI products.
Optionally, the array substrate further includes: and a first insulating layer disposed over the first pixel electrode, wherein the common electrode, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate line are disposed over the first insulating layer at the same layer.
In this alternative, it is possible to realize that the layer on which the first pixel electrode is provided and the layer on which the common electrode is provided are separated by the first insulating layer.
Optionally, the gate of the first thin film transistor and the gate of the second thin film transistor are the same gate metal, wherein an orthographic projection of the gate metal on the substrate covers an orthographic projection of the channel region of the first thin film transistor and an orthographic projection of the channel region of the second thin film transistor on the substrate.
In the optional mode, the grid electrode of the first thin film transistor and the grid electrode of the second thin film transistor can be arranged in the same region, and the grid electrode of the first thin film transistor and the grid electrode of the second thin film transistor are controlled to be turned on or turned off simultaneously by the grid line, so that the control mode is easy to realize.
Optionally, the array substrate further includes: a second insulating layer disposed over the layer on which the common electrode is disposed, wherein the second pixel electrode is disposed over the second insulating layer.
In this alternative, it is possible to separate the layer on which the second pixel electrode is located and the layer on which the common electrode is located by the second insulating layer.
Optionally, the array substrate further includes: a via hole formed in the second insulating layer, wherein the second pixel electrode is connected to the first pole of the second thin film transistor through the via hole.
In this alternative way, the second pixel electrode can be connected to the source electrode of the second thin film transistor through the via hole in the second insulating layer and then through the first insulating layer.
A second aspect of the present invention provides an electronic paper display device, including the array substrate according to the first aspect of the present invention.
The third aspect of the present invention provides a method for manufacturing an array substrate for an electronic paper display device, including:
forming a gate line and a data line crossing to define a plurality of pixel regions, and a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode in at least a part of the pixel regions on a substrate; wherein,
the at least partial pixel region is formed to include a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode on the substrate, a first pole of the first thin film transistor and a second pole of the second thin film transistor are respectively connected with the first pixel electrode, a second pole of the first thin film transistor is connected with the data line, a first pole of the second thin film transistor is connected with the second pixel electrode, and a gate of the first thin film transistor and a gate of the second thin film transistor are respectively connected with the gate line;
the first pixel electrode, the common electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between an orthographic projection of the second pixel electrode on the substrate and an orthographic projection of the common electrode on the substrate and an orthographic projection of the first pixel electrode on the substrate, the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor.
Optionally, the forming of the intersections on the substrate to define a plurality of pixel region gate lines and data lines, and the first thin film transistor, the second thin film transistor, the first pixel electrode, the common electrode, and the second pixel electrode in at least a part of the pixel region includes:
forming a first pixel electrode, a first pole and a second pole of a first thin film transistor, a first pole and a second pole of a second thin film transistor and a data line on a substrate by using a one-time composition process, wherein the first pixel electrode comprises an electrode plate forming part and an extension part, the extension part extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor;
forming a first insulating layer covering the first pixel electrode, the first and second poles of the first thin film transistor, the first and second poles of the second thin film transistor, and the data line;
forming a common electrode, a grid electrode of the first thin film transistor, a grid electrode of the second thin film transistor and a grid line on the first insulating layer by using a one-time composition process;
forming a second insulating layer covering the common electrode, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate line;
forming via holes in the second insulating layer and the first insulating layer;
and forming a second pixel electrode connected with the first pole of the second thin film transistor through the through hole on the second insulating layer.
The invention has the following beneficial effects:
aiming at the technical problems in the prior art, the invention provides an array substrate, a preparation method thereof and an electronic paper display device, wherein the array substrate forms a first pixel electrode, a common electrode and a second pixel electrode, so that the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor, thereby reducing the electric leakage speed of the storage capacitor and increasing the capability of keeping the voltage of the pixel electrode stable; meanwhile, the orthographic projection of the second pixel electrode on the substrate respectively has an overlapping region with the orthographic projection of the common electrode on the substrate and the orthographic projection of the first pixel electrode on the substrate, so that the storage capacitor and the compensation capacitor can be designed in a laminated mode, the extra plane space is not occupied, and the pixel array substrate is suitable for high PPI products.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 shows a flowchart of a method for manufacturing an array substrate for an electronic paper display device according to an embodiment of the present invention.
Fig. 2-4 are schematic diagrams respectively illustrating main steps of a part of a manufacturing flow according to an embodiment of the present invention.
Fig. 5 shows a schematic diagram of a pixel of an embodiment of the invention.
FIG. 6 shows a schematic cross-sectional view of one embodiment of the present invention along line A-A' of FIG. 5.
Fig. 7 illustrates an equivalent circuit diagram of an array substrate for an electronic paper display device according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to the following examples and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
The terms "on … …", "formed on … …" and "disposed on … …" as used herein may mean that one layer is formed or disposed directly on another layer or that one layer is formed or disposed indirectly on another layer, i.e., there is another layer between the two layers.
It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present invention.
In the present invention, unless otherwise specified, the term "disposed on the same layer" is used to mean that two layers, components, members, elements or portions may be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements or portions are generally formed of the same material. For example, two or more functional layers are arranged in the same layer, which means that the functional layers arranged in the same layer can be formed by using the same material layer and using the same manufacturing process, so that the manufacturing process of the display substrate can be simplified.
In the present invention, unless otherwise specified, the expression "patterning process" generally includes steps of coating of a photoresist, exposure, development, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.
Electronic paper display screens have been rapidly developed due to their low power consumption, foldable bending, fine and smooth picture display, wide viewing angle, and the like. The electronic paper display screen achieves a visual effect by reflecting ambient light.
In an array substrate of an electronic paper display screen in the prior art, each pixel structure comprises a data line, a gate line and a pixel electrode, a thin film transistor is formed at the intersection part of the data line and the gate line, the gate of the thin film transistor is connected with the gate line, the source of the thin film transistor is connected with the data line, and the drain of the thin film transistor is connected with the pixel electrode.
The pixel structure and the common electrode in the prior art form a structure that: the pixel electrode comprises a grid line and a data line, a storage capacitor is formed between the pixel electrode and the common electrode which are connected with the thin film transistor, when the grid voltage is normally opened, the thin film transistor is opened by the high level of the grid, and the current flows to the thin film transistor and the pixel electrode through the data line; when the grid voltage is turned off, the source electrode of the thin film transistor has no voltage, the drain electrode voltage is maintained, a large voltage difference exists between the source electrode and the drain electrode of the thin film transistor at the moment, the leakage current of the thin film transistor is large, the residual direct current component is increased when the pixel discharges, so that the charge loss of the storage capacitor is caused, the voltage of the pixel electrode is attenuated, and the phenomena of flicker, image retention and the like are caused when the electronic paper display screen displays.
In order to solve the technical problems in the prior art, a method for manufacturing an array substrate for an electronic paper display device and a structure thereof according to an embodiment of the present invention are described with reference to a method flowchart shown in fig. 1 and schematic structural diagrams shown in fig. 2 to 5.
In a specific example as shown in fig. 1, the preparation method includes:
s101, forming a first pixel electrode 5, a source 81 and a drain 82 of the first thin film transistor TFT1, a drain 91 and a source 92 of the second thin film transistor TFT2, and a data line 2 on the substrate by using a one-step patterning process, wherein the first pixel electrode 5 includes an electrode plate forming portion 51 and an extension portion 52, the extension portion 52 extends between the drain 82 of the first thin film transistor and the drain 91 of the second thin film transistor, and is multiplexed into the source 81 of the first thin film transistor and the source 92 of the second thin film transistor, as shown in fig. 2 and 6.
S102, forming a first insulating layer 41 covering the first pixel electrode 5, the source and drain electrodes 81 and 82 of the first thin film transistor TFT1, the drain and source electrodes 91 and 92 of the second thin film transistor TFT2, and the data line 2, as shown in fig. 6.
The first insulating layer 41 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
S103, forming a common electrode 6, a gate electrode 83 of the first thin film transistor TFT1, a gate electrode 93 of the second thin film transistor TFT2, and a gate line 1 on the first insulating layer 41 by using a one-step patterning process, wherein the gate electrode 83 and the gate electrode 93 are made of the same metal, as shown in fig. 3. Wherein an orthographic projection of the gate metal on the substrate covers an orthographic projection of the channel region of the first thin film transistor TFT1 and the channel region of the second thin film transistor TFT2 on the substrate.
The gate material may include a metal material such as aluminum, titanium, and cobalt.
In this implementation manner, the gate 83 of the first thin film transistor TFT1 and the gate 93 of the second thin film transistor TFT2 may be disposed in the same region, and the gate line 1 simultaneously controls the gate 8 of the first thin film transistor TFT1 and the gate 93 of the second thin film transistor TFT2 to be turned on or off, which is easy to implement and saves the process.
However, it can be understood by those skilled in the art that the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor may be separately formed, and both are electrically connected to the same connecting gate line, and the gate line simultaneously controls the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor to be turned on or off.
S104, forming a second insulating layer 42 covering the common electrode 6, the gate electrode 83 of the first thin film transistor TFT1, the gate electrode 93 of the second thin film transistor TFT2, and the gate line 1, as shown in fig. 6.
The second insulating layer 42 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
S105, forming a via hole 3 in the second insulating layer 42 and the first insulating layer 41, as shown in fig. 5 and 6.
S106, forming a second pixel electrode 7 on the second insulating layer 42, connected to the source electrode 92 of the second thin film transistor TFT2 through the via hole 3, as shown in fig. 4 and 6.
Fig. 5 is a top view of the array substrate obtained by the above exemplary method, and fig. 6 is a cross-sectional view taken along line AA' in fig. 5.
The array substrate obtained by the above exemplary method includes a gate line 1 and a data line 2 on a substrate (not shown in the figure), and the gate line 1 and the data line 2 cross to define a plurality of pixel regions.
Wherein each pixel region illustratively comprises a first thin film transistor TFT1, a second thin film transistor TFT2, a first pixel electrode 5, a common electrode 6, and a second pixel electrode 7 on the substrate.
The first pixel electrode 5, the common electrode 6 and the second pixel electrode 7 are sequentially stacked on the substrate, that is, the layer where the first pixel electrode 5 is located at the bottom layer, the layer where the common electrode 6 is located at the middle layer, and the layer where the second pixel electrode 7 is located at the surface layer. A first insulating layer 41 is provided over the bottom layer, separating the bottom layer from the middle layer by the first insulating layer, and a second insulating layer 42 is provided over the middle layer, separating the middle layer from the top layer by the second insulating layer. The first insulating layer and the second insulating layer may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
In a specific example, the first pixel electrode 5 and the common electrode 6 are made of metal electrode materials to realize a one-time composition process with the source electrode 81 and the drain electrode 82 of the first thin film transistor TFT1, the drain electrode 91 and the source electrode 92 of the second thin film transistor TFT2, the data line 2, and the gate electrode 83 of the first thin film transistor TFT1, the gate electrode 93 of the second thin film transistor TFT2, and the gate line 1, respectively. The second pixel electrode 7 may be made of a metal electrode material, or may be made of a transparent ITO (indium tin oxide) electrode material.
An overlapping region exists between the orthographic projection of the second pixel electrode 7 on the substrate and the orthographic projection of the common electrode 6 on the substrate and the orthographic projection of the first pixel electrode 5 on the substrate respectively, the second pixel electrode 7 and the common electrode 6 form a storage capacitor C2, and the common electrode 6 and the first pixel electrode 5 form a compensation capacitor C1. The storage capacitor C2 is used to hold the voltage of the pixel electrode of the electronic paper display device, so as to ensure that the electronic paper display device can maintain the display image for a long time.
In a specific example, as shown in fig. 5 and 6, there are overlapping portions between the orthographic projection of the second pixel electrode 7 on the substrate and the orthographic projection of the common electrode 6 on the substrate and the orthographic projection of the first pixel electrode 5 on the substrate, respectively, and there are overlapping portions between the orthographic projection of the first pixel electrode 5 on the substrate and the orthographic projection of the common electrode 6 on the substrate, that is, there are overlapping portions between the orthographic projections of the three electrodes of the second pixel electrode 7, the common electrode 6 and the first pixel electrode 5 on the substrate in this embodiment.
In the embodiment, by forming the first pixel electrode, the common electrode and the second pixel electrode, even if the second pixel electrode and the common electrode form a storage capacitor, the common electrode and the first pixel electrode form a compensation capacitor, the leakage speed of the storage capacitor can be reduced, and the capability of keeping the voltage of the pixel electrode stable is increased; meanwhile, the orthographic projection of the second pixel electrode on the substrate respectively has an overlapping area with the orthographic projection of the common electrode on the substrate and the orthographic projection of the first pixel electrode on the substrate, so that the storage capacitor and the compensation capacitor are partially overlapped, and a larger additional plane space is not occupied.
In a more preferred implementation, the orthographic projection of the second pixel electrode 7 on the substrate covers the orthographic projection of the common electrode 6 on the substrate, and the orthographic projection of the second pixel electrode 7 on the substrate covers the orthographic projection of the first pixel electrode 5 (including 51 and 52) on the substrate. In a specific example, as shown in fig. 6, the area of the second pixel electrode 7 is slightly larger than the area of the first pixel electrode 5, and the area of the second pixel electrode 7 is slightly larger than the area of the common electrode 6, and the areas of the first pixel electrode 5 and the common electrode 6 are close to the area of the second pixel electrode 7.
According to the implementation mode, the stacking design of the storage capacitor and the compensation capacitor can be realized, the formed areas of the storage capacitor and the compensation capacitor are large, the larger the area of the compensation capacitor is, the better the suppression effect on the leakage current is, and therefore the capability of keeping the voltage of the pixel electrode stable is better.
In this embodiment, the first thin film transistor TFT1, the first pixel electrode 5, and the second thin film transistor TFT2 are connected in series between the data line 2 and the second pixel electrode 7, and the common electrode 6 is disposed between the first pixel electrode 5 and the second pixel electrode 7. A compensation capacitor C1 is formed between the first pixel electrode 5 and the common electrode 6, and a storage capacitor C2 is formed between the second pixel electrode 7 and the common electrode 6.
The specific connection mode can be explained by reference to the following descriptions: the source 81 of the first TFT1 is electrically connected to the data line 2, the drain 82 of the first TFT1 and the drain 91 of the second TFT2 are electrically connected to the first pixel electrode 5, the source 92 of the second TFT2 is electrically connected to the second pixel electrode 7, and the gate 83 of the first TFT1 and the gate 93 of the second TFT2 are electrically connected to the gate line 1.
In one possible implementation, as shown in fig. 2, 5 and 6, the first pixel electrode 5, the source electrode 81 and the drain electrode 82 of the first thin film transistor TFT1, the drain electrode 91 and the source electrode 92 of the second thin film transistor TFT2, and the data line 2 are disposed in the same layer, wherein the first pixel electrode 5 includes an electrode plate forming part 51 and an extension part 52, and the extension part 52 extends between the drain electrode 82 of the first thin film transistor TFT1 and the drain electrode 91 of the second thin film transistor TFT2 and is multiplexed into the source electrode 81 of the first thin film transistor TFT1 and the drain electrode 91 of the second thin film transistor TFT 2.
The implementation mode can realize that the first pixel electrode is positioned on the same layer as the data line, the source electrode and the drain electrode of the first thin film transistor and the source electrode and the drain electrode of the second thin film transistor, fully utilizes the space of the layer, does not occupy extra plane space, and is suitable for high PPI products.
In one specific example, the common electrode 6, the gate electrode of the first thin film transistor TFT1, the gate electrode of the second thin film transistor TFT2, and the gate line 1 are disposed on the same layer over the first insulating layer.
In a specific example, the second pixel electrode 7 is provided over a second insulating layer, a via hole is opened in the second insulating layer and the first insulating layer, and the second pixel electrode 7 is connected to the source electrode of the second thin film transistor TFT2 provided on the same layer as the first pixel electrode 5 through the via hole.
An equivalent circuit of an array substrate according to an embodiment of the invention is shown in fig. 7. When the pixel works, the high level of the grid electrode turns on the first thin film transistor TFT1 and the second thin film transistor TFT2, the compensation capacitor C1 and the storage capacitor C2 are charged at the same time, the voltages of the first thin film transistor TFT1 and the second thin film transistor TFT2 are the same in the full-charging state, and the voltage difference between the source electrode and the drain electrode of the second thin film transistor TFT2 is zero at the moment; when the gate voltage is turned off, under the condition that a large voltage difference exists between the source and the drain of the first thin film transistor TFT1, the leakage current of the compensation capacitor C1 through the first thin film transistor TFT1 runs off, and the voltage difference between the source and the drain of the second thin film transistor TFT2 becomes a voltage difference larger than zero from zero, but because of the effect of the compensation capacitor C1, the voltage difference between the source and the drain of the second thin film transistor TFT2 is far smaller than the voltage difference between the source and the drain of the first thin film transistor TFT1, and the voltage difference between the second pixel electrode 7 and the drain of the second thin film transistor TFT2 is small, so that the leakage current of the second thin film transistor TFT2 can be effectively reduced, the voltage of the second pixel electrode 7 can be maintained on the basis of reducing the leakage current, and the phenomena of flickering, image sticking and the like of the electronic paper display screen during displaying can be reduced.
In this embodiment, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be both N-type thin film transistors or both P-type thin film transistors, or one of them is an N-type thin film transistor and the other is a P-type thin film transistor. From the viewpoint of simplifying the manufacturing process, it is preferable that the first thin film transistor TFT1 and the second thin film transistor TFT2 be both N-type thin film transistors or both P-type thin film transistors.
Another embodiment of the present invention provides an electronic paper display device including the array substrate provided in the above embodiments. Among them, the electronic paper display device mainly uses various reflective display technologies with bistable characteristics, and common types include electrophoretic display, rolling ball display, bistable liquid crystal, electrowetting display, and fast response electronic powder fluid display.
The electronic paper mainly comprises a surface layer, a bottom layer and a middle layer, wherein tens of thousands of tiny ink particles are arranged in the middle layer, the ink particles are distributed in a transparent base liquid to form a suspension system, the diameter of each ink particle is about 100 mu m, the surface of each ink particle is easy to absorb charges, and the particles capable of inducing the charges can move under the action of an external electric field.
The electronic paper display device may be any product or component with a display function, such as a Kindle electronic book and an ink screen electronic book, which is not limited in this embodiment.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
It is further noted that, in the description of the present invention, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations and modifications can be made on the basis of the above description, and all embodiments cannot be exhaustive, and all obvious variations and modifications belonging to the technical scheme of the present invention are within the protection scope of the present invention.
Claims (10)
1. An array substrate for an electronic paper display device, the array substrate comprising gate lines and data lines on a substrate, the gate lines and the data lines crossing to define a plurality of pixel regions,
at least part of the pixel region comprises a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode which are positioned on the substrate, wherein a first pole of the first thin film transistor and a second pole of the second thin film transistor are respectively connected with the first pixel electrode, a second pole of the first thin film transistor is connected with the data line, a first pole of the second thin film transistor is connected with the second pixel electrode, and a grid electrode of the first thin film transistor and a grid electrode of the second thin film transistor are respectively connected with the grid line;
the first pixel electrode, the common electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between an orthographic projection of the second pixel electrode on the substrate and an orthographic projection of the common electrode on the substrate and an orthographic projection of the first pixel electrode on the substrate, the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor.
2. The array substrate of claim 1, wherein an orthographic projection of the second pixel electrode on the substrate covers an orthographic projection of the common electrode on the substrate, and an orthographic projection of the second pixel electrode on the substrate covers an orthographic projection of the first pixel electrode on the substrate.
3. The array substrate of claim 1 or 2, wherein the first pixel electrode, the first pole of the first thin film transistor, the second pole of the second thin film transistor, and the data line are disposed in the same layer, wherein the first pixel electrode comprises an electrode plate forming part and an extension part, the extension part extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor.
4. The array substrate of claim 3, further comprising: and a first insulating layer disposed over the first pixel electrode, wherein the common electrode, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate line are disposed over the first insulating layer at the same layer.
5. The array substrate of claim 4, wherein the gate of the first thin film transistor and the gate of the second thin film transistor are the same gate metal, and wherein an orthographic projection of the gate metal on the substrate covers an orthographic projection of the channel region of the first thin film transistor and the orthographic projection of the channel region of the second thin film transistor on the substrate.
6. The array substrate of claim 4 or 5, further comprising: a second insulating layer disposed over the layer on which the common electrode is disposed, wherein the second pixel electrode is disposed over the second insulating layer.
7. The array substrate of claim 6, further comprising: a via hole formed in the second insulating layer, wherein the second pixel electrode is connected to the first pole of the second thin film transistor through the via hole.
8. An electronic paper display device comprising the array substrate according to any one of claims 1 to 7.
9. A preparation method of an array substrate for an electronic paper display device is characterized by comprising the following steps:
forming a gate line and a data line crossing to define a plurality of pixel regions, and a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode in at least a part of the pixel regions on a substrate; wherein,
the at least partial pixel region is formed to include a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode on the substrate, a first pole of the first thin film transistor and a second pole of the second thin film transistor are respectively connected with the first pixel electrode, a second pole of the first thin film transistor is connected with the data line, a first pole of the second thin film transistor is connected with the second pixel electrode, and a gate of the first thin film transistor and a gate of the second thin film transistor are respectively connected with the gate line;
the first pixel electrode, the common electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between an orthographic projection of the second pixel electrode on the substrate and an orthographic projection of the common electrode on the substrate and an orthographic projection of the first pixel electrode on the substrate, the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor.
10. The method of claim 9, wherein the forming of the intersections on the substrate to define a plurality of pixel region gate lines and data lines, and wherein the first thin film transistors, the second thin film transistors, the first pixel electrodes, the common electrodes, and the second pixel electrodes in at least a portion of the pixel regions comprises:
forming a first pixel electrode, a first pole and a second pole of a first thin film transistor, a first pole and a second pole of a second thin film transistor and a data line on a substrate by using a one-time composition process, wherein the first pixel electrode comprises an electrode plate forming part and an extension part, the extension part extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor;
forming a first insulating layer covering the first pixel electrode, the first and second poles of the first thin film transistor, the first and second poles of the second thin film transistor, and the data line;
forming a common electrode, a grid electrode of the first thin film transistor, a grid electrode of the second thin film transistor and a grid line on the first insulating layer by using a one-time composition process;
forming a second insulating layer covering the common electrode, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate line;
forming via holes in the second insulating layer and the first insulating layer;
and forming a second pixel electrode connected with the first pole of the second thin film transistor through the through hole on the second insulating layer.
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