CN113687550B - Array substrate and preparation method thereof, and electronic paper display device - Google Patents
Array substrate and preparation method thereof, and electronic paper display device Download PDFInfo
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
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Abstract
本发明实施例公开一种阵列基板及其制备方法、电子纸显示装置。在一具体实施方式中，用于电子纸显示装置的阵列基板包括位于衬底上的栅线和数据线，所述栅线和所述数据线交叉限定出多个像素区域，至少部分所述像素区域包括位于所述衬底上的第一薄膜晶体管、第二薄膜晶体管、第一像素电极、公共电极和第二像素电极，所述第一薄膜晶体管的第一极和所述第二薄膜晶体管的第二极分别连接所述第一像素电极，所述第一薄膜晶体管的第二极连接所述数据线，所述第二薄膜晶体管的第一极连接所述第二像素电极，所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的栅极分别连接栅线。该实施方式可降低存储电容的漏电速度，从而增加像素电极电压保持稳定的能力。
The embodiment of the present invention discloses an array substrate and a method for preparing the same, and an electronic paper display device. In a specific embodiment, the array substrate for the electronic paper display device includes a gate line and a data line located on a substrate, the gate line and the data line intersect to define a plurality of pixel areas, at least part of the pixel areas include a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode, and a second pixel electrode located on the substrate, the first electrode of the first thin film transistor and the second electrode of the second thin film transistor are respectively connected to the first pixel electrode, the second electrode of the first thin film transistor is connected to the data line, the first electrode of the second thin film transistor is connected to the second pixel electrode, and the gate of the first thin film transistor and the gate of the second thin film transistor are respectively connected to the gate line. This embodiment can reduce the leakage rate of the storage capacitor, thereby increasing the ability of the pixel electrode voltage to remain stable.
Description
Technical Field
The invention relates to the technical field of display. More particularly, the invention relates to an array substrate, a preparation method thereof and an electronic paper display device.
Background
The electronic paper display screen has the characteristics of low power consumption, folding and bending, fine and smooth picture display, wide visual angle and the like, so that the electronic paper display screen is rapidly developed. The electronic paper display screen achieves a visual effect by reflecting ambient light.
In an array substrate of an electronic paper display screen in the prior art, each pixel structure comprises a data line, a grid line and a pixel electrode, a thin film transistor is formed at the intersection part of the data line and the grid line, the grid line is connected with the grid line, the source electrode of the thin film transistor is connected with the data line, and the drain electrode of the thin film transistor is connected with the pixel electrode.
The structure formed by the pixel structure and the common electrode in the prior art is as follows: the pixel electrode comprises a grid line and a data line, a storage capacitor is formed between the pixel electrode connected with the thin film transistor and the common electrode, when the grid voltage is normally opened, the thin film transistor is opened by the high level of the grid, and current flows to the thin film transistor and the pixel electrode through the data line; when the grid voltage is closed, the source electrode of the thin film transistor has no voltage, the drain electrode voltage is kept, at the moment, a larger voltage difference exists between the source electrode and the drain electrode of the thin film transistor, the leakage current of the thin film transistor is larger, the residual direct current component is increased when the pixel discharges, the charge loss of the storage capacitor is caused, and the voltage of the pixel electrode is attenuated.
Disclosure of Invention
The invention aims to provide an array substrate, a preparation method thereof and an electronic paper display device, so as to solve at least one of the problems in the prior art.
In order to achieve the above purpose, the invention adopts the following technical scheme:
The first aspect of the present invention provides an array substrate for an electronic paper display device, the array substrate including gate lines and data lines on a substrate, the gate lines and the data lines intersecting to define a plurality of pixel regions,
At least part of the pixel region comprises a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode which are positioned on the substrate, wherein a first electrode of the first thin film transistor and a second electrode of the second thin film transistor are respectively connected with the first pixel electrode, a second electrode of the first thin film transistor is connected with the data line, a first electrode of the second thin film transistor is connected with the second pixel electrode, and a grid electrode of the first thin film transistor and a grid electrode of the second thin film transistor are respectively connected with the grid line;
The first pixel electrode, the public electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between orthographic projection of the second pixel electrode on the substrate and orthographic projection of the public electrode on the substrate and orthographic projection of the first pixel electrode on the substrate respectively, the second pixel electrode and the public electrode form a storage capacitor, and the public electrode and the first pixel electrode form a compensation capacitor.
According to the array substrate provided by the first aspect of the invention, the first pixel electrode, the common electrode and the second pixel electrode are formed, so that the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor, so that the leakage speed of the storage capacitor can be reduced, and the capacity of keeping the voltage of the pixel electrode stable is improved; meanwhile, the front projection of the second pixel electrode on the substrate has an overlapping area with the front projection of the common electrode on the substrate and the front projection of the first pixel electrode on the substrate respectively, so that the storage capacitor and the compensation capacitor are designed in a stacked manner, no extra plane space is occupied, and the method is suitable for high PPI products.
Optionally, the orthographic projection of the second pixel electrode on the substrate covers the orthographic projection of the common electrode on the substrate, and the orthographic projection of the second pixel electrode on the substrate covers the orthographic projection of the first pixel electrode on the substrate.
In the alternative mode, the storage capacitor and the compensation capacitor can be designed in a full-overlapping mode, the areas of the storage capacitor and the compensation capacitor are larger, the larger the area of the compensation capacitor is, the better the suppression effect on leakage current is, and therefore the capability of keeping the voltage of the pixel electrode stable is better.
Optionally, the first pixel electrode, the first pole of the first thin film transistor, the second pole of the second thin film transistor, and the data line are arranged in the same layer, wherein the first pixel electrode includes an electrode plate forming portion and an extension portion, and the extension portion extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor, and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor.
In this alternative manner, the first pixel electrode, the source electrode and the drain electrode of the first thin film transistor and the source electrode and the drain electrode of the second thin film transistor are located on the same layer, so that the space of the layer can be fully utilized, no extra planar space is occupied, and the pixel electrode is suitable for high PPI products.
Optionally, the array substrate further includes: and the first insulating layer is arranged above the layer where the first pixel electrode is arranged, wherein the common electrode, the grid electrode of the first thin film transistor, the grid electrode of the second thin film transistor and the grid line are arranged above the first insulating layer in the same layer.
Alternatively, a layer where the first pixel electrode is located and a layer where the common electrode is located may be separated by a first insulating layer.
Optionally, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are the same gate metal, wherein the orthographic projection of the gate metal on the substrate covers the orthographic projections of the channel region of the first thin film transistor and the channel region of the second thin film transistor on the substrate.
In this alternative manner, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor may be disposed in the same region, and the gate line may simultaneously control the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor to be turned on or off, so that the control manner is easy to implement.
Optionally, the array substrate further includes: and a second insulating layer disposed over the common electrode layer, wherein the second pixel electrode is disposed over the second insulating layer.
Alternatively, a layer where the second pixel electrode is located and a layer where the common electrode is located may be separated by a second insulating layer.
Optionally, the array substrate further includes: and a via hole formed in the second insulating layer, wherein the second pixel electrode is connected to the first electrode of the second thin film transistor through the via hole.
Alternatively, the second pixel electrode may be connected to the source electrode of the second thin film transistor through the via hole in the second insulating layer and then through the first insulating layer.
A second aspect of the present invention provides an electronic paper display device, including an array substrate according to the first aspect of the present invention.
A third aspect of the present invention provides a method for manufacturing an array substrate for an electronic paper display device, including:
Forming gate lines and data lines intersecting to define a plurality of pixel regions on a substrate, and a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode, and a second pixel electrode in at least a portion of the pixel regions; wherein,
The at least partial pixel region is formed to include a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode, and a second pixel electrode on the substrate, a first electrode of the first thin film transistor and a second electrode of the second thin film transistor are respectively connected to the first pixel electrode, a second electrode of the first thin film transistor is connected to the data line, a first electrode of the second thin film transistor is connected to the second pixel electrode, and a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are respectively connected to the gate line;
The first pixel electrode, the public electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between orthographic projection of the second pixel electrode on the substrate and orthographic projection of the public electrode on the substrate and orthographic projection of the first pixel electrode on the substrate respectively, the second pixel electrode and the public electrode form a storage capacitor, and the public electrode and the first pixel electrode form a compensation capacitor.
Optionally, forming the gate lines and the data lines on the substrate to cross and define a plurality of pixel regions, and the first thin film transistor, the second thin film transistor, the first pixel electrode, the common electrode, and the second pixel electrode in at least a portion of the pixel regions includes:
forming a first pixel electrode, a first pole and a second pole of a first thin film transistor, and a first pole and a second pole of a second thin film transistor, and a data line on a substrate by a one-time patterning process, wherein the first pixel electrode comprises an electrode plate forming part and an extending part, and the extending part extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor;
Forming a first insulating layer covering the first pixel electrode, the first and second poles of the first thin film transistor, the first and second poles of the second thin film transistor, and the data line;
Forming a common electrode, a grid electrode of a first thin film transistor, a grid electrode of a second thin film transistor and a grid line on the first insulating layer by utilizing a one-time composition process;
Forming a second insulating layer covering the common electrode, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate line;
Forming a via hole in the second insulating layer and the first insulating layer;
And forming a second pixel electrode connected to the first electrode of the second thin film transistor through the via hole on the second insulating layer.
The beneficial effects of the invention are as follows:
Aiming at the technical problems existing in the prior art, the invention provides an array substrate, a preparation method thereof and an electronic paper display device, wherein the array substrate forms a storage capacitor with a common electrode by forming a first pixel electrode, the common electrode and a second pixel electrode, and the common electrode forms a compensation capacitor with the first pixel electrode, so that the leakage speed of the storage capacitor can be reduced, and the voltage maintaining capacity of the pixel electrode is improved; meanwhile, the front projection of the second pixel electrode on the substrate has an overlapping area with the front projection of the common electrode on the substrate and the front projection of the first pixel electrode on the substrate respectively, so that the storage capacitor and the compensation capacitor are designed in a stacked manner, no extra plane space is occupied, and the method is suitable for high PPI products.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Fig. 1 is a flowchart illustrating a method for manufacturing an array substrate for an electronic paper display device according to an embodiment of the present invention.
Fig. 2-4 respectively show schematic diagrams corresponding to main steps of a partial manufacturing process according to an embodiment of the invention.
Fig. 5 shows a schematic diagram of a pixel of an embodiment of the invention.
FIG. 6 shows a schematic cross-sectional view along line A-A' of FIG. 5 of one embodiment of the invention.
Fig. 7 illustrates an equivalent circuit diagram of an array substrate for an electronic paper display device according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to examples and drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
The terms "on … …", "formed on … …" and "disposed on … …" as used herein may mean that one layer is formed directly on or disposed on another layer, or that one layer is formed indirectly on or disposed on another layer, i.e., that other layers are present between the two layers.
It should be noted that although the terms "first," "second," etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer and/or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present invention.
In the present invention, unless otherwise indicated, the term "co-layer arrangement" is used to mean that two layers, components, members, elements or portions may be formed by the same manufacturing process (e.g., patterning process, etc.), and that the two layers, components, members, elements or portions are generally formed of the same material. For example, the two or more functional layers are arranged in the same layer, meaning that the functional layers arranged in the same layer may be formed using the same material layer and the same manufacturing process, so that the manufacturing process of the display substrate may be simplified.
In the present invention, the expression "patterning process" generally includes the steps of coating of photoresist, exposure, development, etching, stripping of photoresist, and the like, unless otherwise specified. The expression "one patterning process" means a process of forming a patterned layer, feature, component, etc. using a single mask.
The electronic paper display screen has the characteristics of low power consumption, folding and bending, fine and smooth picture display, wide visual angle and the like, so that the electronic paper display screen is rapidly developed. The electronic paper display screen achieves a visual effect by reflecting ambient light.
In an array substrate of an electronic paper display screen in the prior art, each pixel structure comprises a data line, a grid line and a pixel electrode, a thin film transistor is formed at the intersection part of the data line and the grid line, the grid line is connected with the grid line, the source electrode of the thin film transistor is connected with the data line, and the drain electrode of the thin film transistor is connected with the pixel electrode.
The structure formed by the pixel structure and the common electrode in the prior art is as follows: the pixel electrode comprises a grid line and a data line, a storage capacitor is formed between the pixel electrode connected with the thin film transistor and the common electrode, when the grid voltage is normally opened, the thin film transistor is opened by the high level of the grid, and current flows to the thin film transistor and the pixel electrode through the data line; when the grid voltage is closed, the source electrode of the thin film transistor has no voltage, the drain electrode voltage is kept, at the moment, a larger voltage difference exists between the source electrode and the drain electrode of the thin film transistor, the leakage current of the thin film transistor is larger, the residual direct current component is increased when the pixel discharges to cause the charge loss of the storage capacitor, the voltage of the pixel electrode is attenuated, and the phenomena of flickering, afterimage and the like occur when the electronic paper display screen displays.
In order to solve the technical problems in the prior art, the method and structure for manufacturing an array substrate for an electronic paper display device according to the embodiments of the present invention are described with reference to a flowchart of a method shown in fig. 1 and schematic structural diagrams shown in fig. 2 to 5.
In the specific example shown in fig. 1, the preparation method includes:
S101, forming a first pixel electrode 5, a source 81 and a drain 82 of a first thin film transistor TFT1, a drain 91 and a source 92 of a second thin film transistor TFT2, and a data line 2 on a substrate by a one-time patterning process, wherein the first pixel electrode 5 includes an electrode plate forming portion 51 and an extension portion 52, and the extension portion 52 extends between the drain 82 of the first thin film transistor and the drain 91 of the second thin film transistor, and is multiplexed into the source 81 of the first thin film transistor and the source 92 of the second thin film transistor, as shown in fig. 2 and 6.
S102, a first insulating layer 41 is formed to cover the first pixel electrode 5, the source 81 and drain 82 of the first thin film transistor TFT1, the drain 91 and source 92 of the second thin film transistor TFT2, and the data line 2, as shown in fig. 6.
The first insulating layer 41 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
S103, forming a common electrode 6, a gate electrode 83 of the first TFT1, a gate electrode 93 of the second TFT2, and a gate line 1 on the first insulating layer 41 by using a single patterning process, wherein the gate electrode 83 and the gate electrode 93 are made of the same metal, as shown in fig. 3. Wherein the orthographic projection of the gate metal on the substrate covers the orthographic projection of the channel region of the first thin film transistor TFT1 and the channel region of the second thin film transistor TFT2 on the substrate.
The gate material may include a metal material such as aluminum, titanium, cobalt, and the like.
In this implementation manner, the gate electrode 83 of the first thin film transistor TFT1 and the gate electrode 93 of the second thin film transistor TFT2 may be disposed in the same region, and the gate line 1 may simultaneously control the gate electrode 8 of the first thin film transistor TFT1 and the gate electrode 93 of the second thin film transistor TFT2 to be turned on or off, so that the control manner is easy to implement, and the process is saved.
However, as will be appreciated by those skilled in the art, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor may be formed separately, both of which are electrically connected to the same connecting gate line, and the gate lines simultaneously control the gate electrodes of the first thin film transistor and the second thin film transistor to be turned on or off.
S104, a second insulating layer 42 is formed to cover the common electrode 6, the gate electrode 83 of the first thin film transistor TFT1, the gate electrode 93 of the second thin film transistor TFT2, and the gate line 1, as shown in fig. 6.
The second insulating layer 42 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
S105, opening a via hole 3 in the second insulating layer 42 and the first insulating layer 41, as shown in fig. 5 and 6.
S106, a second pixel electrode 7 connected to the source 92 of the second thin film transistor TFT2 through the via hole 3 is formed on the second insulating layer 42, as shown in fig. 4 and 6.
In which fig. 5 shows a structural plan view of the array substrate obtained by the above-described exemplary method, and fig. 6 is a sectional view taken along line AA' in fig. 5.
The array substrate obtained by the above-described exemplary method includes the gate line 1 and the data line 2 on the substrate (not shown in the drawing), and the gate line 1 and the data line 2 cross to define a plurality of pixel regions.
In which, by way of example, each pixel region includes a first thin film transistor TFT1, a second thin film transistor TFT2, a first pixel electrode 5, a common electrode 6, and a second pixel electrode 7 on the substrate.
The first pixel electrode 5, the common electrode 6 and the second pixel electrode 7 are sequentially stacked on the substrate, that is, the first pixel electrode 5 is located at the bottom layer, the common electrode 6 is located at the middle layer, and the second pixel electrode 7 is located at the surface layer. A first insulating layer 41 is provided over the base layer, separating the base layer from the intermediate layer by the first insulating layer, and a second insulating layer 42 is provided over the intermediate layer, separating the intermediate layer from the face layer by the second insulating layer. Wherein, the first insulating layer and the second insulating layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
In a specific example, the first pixel electrode 5 and the common electrode 6 are made of metal electrode materials to realize preparation with the source 81 and the drain 82 of the first thin film transistor TFT1, the drain 91 and the source 92 of the second thin film transistor TFT2, the data line 2 by one patterning process and preparation with the gate 83 of the first thin film transistor TFT1, the gate 93 of the second thin film transistor TFT2, and the gate line 1 by one patterning process, respectively. The second pixel electrode 7 may be made of a metal electrode material or a transparent ITO (indium tin oxide) electrode material.
The orthographic projection of the second pixel electrode 7 on the substrate has overlapping areas with the orthographic projection of the common electrode 6 on the substrate and the orthographic projection of the first pixel electrode 5 on the substrate respectively, the second pixel electrode 7 and the common electrode 6 form a storage capacitor C2, and the common electrode 6 and the first pixel electrode 5 form a compensation capacitor C1. The storage capacitor C2 is used to maintain the voltage of the pixel electrode of the electronic paper display device, so as to ensure that the electronic paper display device can maintain the display screen for a long time.
In a specific example, as shown in fig. 5 and 6, the front projection of the second pixel electrode 7 on the substrate has an overlapping portion with the front projection of the common electrode 6 on the substrate and the front projection of the first pixel electrode 5 on the substrate, respectively, and the front projection of the first pixel electrode 5 on the substrate also has an overlapping portion with the front projection of the common electrode 6 on the substrate, that is, the front projections of the three electrodes of the second pixel electrode 7, the common electrode 6 and the first pixel electrode 5 overlap with each other in this embodiment.
According to the embodiment, the first pixel electrode, the common electrode and the second pixel electrode are formed, so that the second pixel electrode and the common electrode form a storage capacitor, and the common electrode and the first pixel electrode form a compensation capacitor, so that the leakage speed of the storage capacitor can be reduced, and the capacity of keeping the voltage of the pixel electrode stable is improved; meanwhile, the front projection of the second pixel electrode on the substrate has an overlapping area with the front projection of the common electrode on the substrate and the front projection of the first pixel electrode on the substrate respectively, so that the storage capacitor and the compensation capacitor are partially overlapped, and the larger additional plane space is not occupied.
In a more preferred implementation, the front projection of the second pixel electrode 7 on the substrate covers the front projection of the common electrode 6 on the substrate, and the front projection of the second pixel electrode 7 on the substrate covers the front projection of the first pixel electrode 5 (including 51 and 52) on the substrate. In a specific example, as shown in fig. 6, the area of the second pixel electrode 7 is slightly larger than the area of the first pixel electrode 5, and the area of the second pixel electrode 7 is slightly larger than the area of the common electrode 6, and the areas of the first pixel electrode 5 and the common electrode 6 are close to the area of the second pixel electrode 7.
According to the implementation mode, the stacked design of the storage capacitor and the compensation capacitor can be realized, the formed storage capacitor and compensation capacitor are larger in area, and the larger the area of the compensation capacitor is, the better the suppression effect on leakage current is, so that the capacity of keeping the voltage of the pixel electrode stable is better.
In this embodiment, the first thin film transistor TFT1, the first pixel electrode 5 and the second thin film transistor TFT2 are connected in series between the data line 2 and the second pixel electrode 7, and the common electrode 6 is disposed between the first pixel electrode 5 and the second pixel electrode 7. A compensation capacitor C1 is formed between the first pixel electrode 5 and the common electrode 6, and a storage capacitor C2 is formed between the second pixel electrode 7 and the common electrode 6.
The specific connection mode can be described as follows: the source 81 of the first thin film transistor TFT1 is electrically connected to the data line 2, the drain 82 of the first thin film transistor TFT1 and the drain 91 of the second thin film transistor TFT2 are electrically connected to the first pixel electrode 5, the source 92 of the second thin film transistor TFT2 is electrically connected to the second pixel electrode 7, and the gate 83 of the first thin film transistor TFT1 and the gate 93 of the second thin film transistor TFT2 are electrically connected to the gate line 1.
In one possible implementation, as shown in fig. 2, 5 and 6, the first pixel electrode 5, the source 81 and the drain 82 of the first thin film transistor TFT1, the drain 91 and the source 92 of the second thin film transistor TFT2, and the data line 2 are arranged in the same layer, wherein the first pixel electrode 5 includes an electrode plate forming portion 51 and an extension portion 52, and the extension portion 52 extends between the drain 82 of the first thin film transistor TFT1 and the drain 91 of the second thin film transistor TFT2, and is multiplexed into the source 81 of the first thin film transistor TFT1 and the drain 91 of the second thin film transistor TFT 2.
The implementation mode can realize that the first pixel electrode is positioned on the same layer as the data line, the source electrode and the drain electrode of the first thin film transistor and the source electrode and the drain electrode of the second thin film transistor, fully utilizes the space of the layer, does not occupy extra plane space, and is suitable for high PPI products.
In a specific example, the common electrode 6, the gate electrode of the first thin film transistor TFT1, the gate electrode of the second thin film transistor TFT2, and the gate line 1 are disposed above the first insulating layer in the same layer.
In a specific example, the second pixel electrode 7 is disposed above the second insulating layer, and the second insulating layer and the first insulating layer are provided with vias, and the second pixel electrode 7 is connected to the source of the second thin film transistor TFT2 disposed on the same layer as the first pixel electrode 5 through the vias.
An array substrate equivalent circuit according to an embodiment of the present invention is shown in fig. 7. When the pixel works, the first thin film transistor TFT1 and the second thin film transistor TFT2 are turned on by the high level of the grid electrode, meanwhile, the compensation capacitor C1 and the storage capacitor C2 are charged, the voltages of the first thin film transistor TFT1 and the second thin film transistor TFT2 are the same in a full state, and at the moment, the voltage difference between the source electrode and the drain electrode of the second thin film transistor TFT2 is zero; when the gate voltage is turned off, under the condition that a larger voltage difference exists between the source electrode and the drain electrode of the first thin film transistor TFT1, the compensation capacitor C1 runs off through the leakage current of the first thin film transistor TFT1, the voltage difference between the source electrode and the drain electrode of the second thin film transistor TFT2 is changed from zero to a voltage difference larger than zero, but because of the effect of the compensation capacitor C1, the voltage difference between the source electrode and the drain electrode of the second thin film transistor TFT2 is far smaller than the voltage difference between the source electrode and the drain electrode of the first thin film transistor TFT1, the voltage difference between the second pixel electrode 7 and the drain electrode of the second thin film transistor TFT2 is small, the leakage current of the second thin film transistor TFT2 can be effectively reduced, and the voltage of the second pixel electrode 7 can be kept on the basis of reducing the leakage current, so that phenomena such as flickering and afterimage and the like of an electronic paper display screen can be reduced during display.
It should be noted that, in this embodiment, the first TFT1 and the second TFT2 may be N-type TFTs, P-type TFTs, or one of the N-type TFTs and the other P-type TFT. From the viewpoint of simplifying the manufacturing process, it is preferable that the first thin film transistor TFT1 and the second thin film transistor TFT2 are both N-type thin film transistors or both P-type thin film transistors.
Another embodiment of the present invention provides an electronic paper display device including the array substrate provided in the above embodiment. Among them, electronic paper display devices are mainly based on various reflective display technologies with bistable characteristics, and common types include electrophoretic display, spin ball display, bistable liquid crystal, electrowetting display, and fast response electronic powder fluid display.
The electronic paper mainly comprises a surface layer, a bottom layer and a middle layer, wherein tens of thousands of tiny ink particles are distributed in a transparent base solution to form a suspension system, the diameter of each ink particle is about 100 mu m, the surface of each ink particle is easy to absorb charges, and the particles capable of inducing charges can move under the action of an external electric field.
The electronic paper display device may be any product or component with a display function, such as a Kindle electronic book, an ink screen electronic book, and the embodiment is not limited thereto.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
It is further noted that in the description of the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (9)
1. An array substrate for an electronic paper display device, the array substrate comprising a gate line and a data line on a substrate, the gate line and the data line crossing to define a plurality of pixel regions, characterized in that,
At least part of the pixel region comprises a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode and a second pixel electrode which are positioned on the substrate, wherein a first electrode of the first thin film transistor and a second electrode of the second thin film transistor are respectively connected with the first pixel electrode, a second electrode of the first thin film transistor is connected with the data line, a first electrode of the second thin film transistor is connected with the second pixel electrode, and a grid electrode of the first thin film transistor and a grid electrode of the second thin film transistor are respectively connected with the grid line;
The first pixel electrode, the public electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between orthographic projection of the second pixel electrode on the substrate and orthographic projection of the public electrode on the substrate and orthographic projection of the first pixel electrode on the substrate respectively, the second pixel electrode and the public electrode form a storage capacitor, and the public electrode and the first pixel electrode form a compensation capacitor;
The first pixel electrode, the first pole of the first thin film transistor, the second pole of the second thin film transistor and the data line are arranged in the same layer, wherein the first pixel electrode comprises an electrode plate forming part and an extending part, and the extending part extends to a position between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor.
2. The array substrate of claim 1, wherein the orthographic projection of the second pixel electrode on the substrate covers the orthographic projection of the common electrode on the substrate, and the orthographic projection of the second pixel electrode on the substrate covers the orthographic projection of the first pixel electrode on the substrate.
3. The array substrate of claim 2, further comprising: and the first insulating layer is arranged above the layer where the first pixel electrode is arranged, wherein the common electrode, the grid electrode of the first thin film transistor, the grid electrode of the second thin film transistor and the grid line are arranged above the first insulating layer in the same layer.
4. The array substrate of claim 3, wherein the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are the same gate metal, wherein an orthographic projection of the gate metal on the substrate covers an orthographic projection of the channel region of the first thin film transistor and the channel region of the second thin film transistor on the substrate.
5. The array substrate of claim 3 or 4, further comprising: and a second insulating layer disposed over the common electrode layer, wherein the second pixel electrode is disposed over the second insulating layer.
6. The array substrate of claim 5, further comprising: and a via hole formed in the second insulating layer, wherein the second pixel electrode is connected to the first electrode of the second thin film transistor through the via hole.
7. An electronic paper display device comprising the array substrate according to any one of claims 1 to 6.
8. A method for manufacturing an array substrate for an electronic paper display device, comprising:
Forming gate lines and data lines intersecting to define a plurality of pixel regions on a substrate, and a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode, and a second pixel electrode in at least a portion of the pixel regions; wherein,
The at least partial pixel region is formed to include a first thin film transistor, a second thin film transistor, a first pixel electrode, a common electrode, and a second pixel electrode on the substrate, a first electrode of the first thin film transistor and a second electrode of the second thin film transistor are respectively connected to the first pixel electrode, a second electrode of the first thin film transistor is connected to the data line, a first electrode of the second thin film transistor is connected to the second pixel electrode, and a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are respectively connected to the gate line;
The first pixel electrode, the public electrode and the second pixel electrode are sequentially stacked on the substrate, an overlapping area exists between orthographic projection of the second pixel electrode on the substrate and orthographic projection of the public electrode on the substrate and orthographic projection of the first pixel electrode on the substrate respectively, the second pixel electrode and the public electrode form a storage capacitor, and the public electrode and the first pixel electrode form a compensation capacitor;
The forming the gate lines and the data lines on the substrate to cross and define a plurality of pixel regions, and the first thin film transistor, the second thin film transistor, the first pixel electrode, the common electrode, and the second pixel electrode in at least a portion of the pixel regions includes:
And forming a first pixel electrode, a first pole and a second pole of a first thin film transistor, and a first pole and a second pole of a second thin film transistor, and a data line on a substrate by using a one-time patterning process, wherein the first pixel electrode comprises an electrode plate forming part and an extending part, and the extending part extends between the first pole of the first thin film transistor and the second pole of the second thin film transistor and is multiplexed into the second pole of the first thin film transistor and the first pole of the second thin film transistor.
9. The method of manufacturing according to claim 8, further comprising:
Forming a first insulating layer covering the first pixel electrode, the first and second poles of the first thin film transistor, the first and second poles of the second thin film transistor, and the data line;
Forming a common electrode, a grid electrode of a first thin film transistor, a grid electrode of a second thin film transistor and a grid line on the first insulating layer by utilizing a one-time composition process;
Forming a second insulating layer covering the common electrode, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate line;
Forming a via hole in the second insulating layer and the first insulating layer;
And forming a second pixel electrode connected to the first electrode of the second thin film transistor through the via hole on the second insulating layer.
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| WO2025020075A1 (en) * | 2023-07-25 | 2025-01-30 | 京东方科技集团股份有限公司 | Electronic paper, display apparatus, and display control method |
| CN117059042B (en) * | 2023-08-24 | 2026-03-20 | 昆山国显光电有限公司 | Electronic paper driving circuit, fabrication method and electronic paper display panel |
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