CN110515252A - Electronic Paper pixel unit and Electronic Paper pixel unit preparation method - Google Patents
Electronic Paper pixel unit and Electronic Paper pixel unit preparation method Download PDFInfo
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- CN110515252A CN110515252A CN201910818751.7A CN201910818751A CN110515252A CN 110515252 A CN110515252 A CN 110515252A CN 201910818751 A CN201910818751 A CN 201910818751A CN 110515252 A CN110515252 A CN 110515252A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 370
- 239000002184 metal Substances 0.000 claims abstract description 127
- 229910052751 metal Inorganic materials 0.000 claims abstract description 127
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 13
- 230000008878 coupling Effects 0.000 claims description 11
- 238000010168 coupling process Methods 0.000 claims description 11
- 238000005859 coupling reaction Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 1
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- 239000003989 dielectric material Substances 0.000 abstract description 15
- 230000006835 compression Effects 0.000 abstract description 7
- 238000007906 compression Methods 0.000 abstract description 7
- 238000007639 printing Methods 0.000 abstract description 7
- 239000010408 film Substances 0.000 description 27
- 239000003990 capacitor Substances 0.000 description 12
- 238000003860 storage Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 101150037603 cst-1 gene Proteins 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
- G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/1675—Constructional details
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/1675—Constructional details
- G02F1/1676—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field
- G02F1/1675—Constructional details
- G02F1/1676—Electrodes
- G02F1/16766—Electrodes for active matrices
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- Optics & Photonics (AREA)
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Abstract
The embodiment of the invention discloses a kind of Electronic Paper pixel unit and Electronic Paper pixel unit and preparation method; the Electronic Paper pixel unit includes the tft layer to be formed on substrate; the protective layer being covered on the tft layer, and it is formed in the pixel electrode layer that the protective layer deviates from the tft layer side；The pixel electrode layer is coupled by the Source and drain metal level of the first via hole and the tft layer through the protective layer；Wherein, the protective layer includes the insulating layer and flatness layer being stacked.The embodiment of the present invention increases the flatness layer being stacked with insulating layer in Electronic Paper pixel unit, the setting of the flatness layer increases the dielectric material thickness between tft layer and pixel electrode layer, Array film layer is weighed wounded so as to avoid in blue film wire printed network version printing process foreign matter, ability is hurt in the resistance to compression for improving the Electronic Paper, and then improves the yield of product.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of Electronic Paper pixel unit and Electronic Paper pixel unit
Preparation method.
Background technique
Electronic Paper has the characteristics that frivolous, flexible and energy saving, is applied to portable product and Dynamically Announce and requires lower production
In product, it is concentrated mainly on billboard, billboard, label, wrist-watch, mobile phone, electronic paper reader, Flexible Displays etc..
Currently, the structure of Electronic Paper pixel unit is referring to Fig.1, including being stacked TFT layer (film crystal on substrate
Tube layer) 101, insulating layer 102 and pixel electrode layer 103；Due to the characteristic of current Electronic Paper cellular construction, in the blue film of Electronic Paper
It attaches in journey made of paper, is easy to produce the case where foreign matter weighs Array film layer wounded, so as to cause GDS phenomenon.
Summary of the invention
The present invention provides Electronic Paper pixel unit and Electronic Paper pixel unit preparation method, existing in electronics to solve
The blue film of paper attaches during paper is made, and is easy to produce the case where foreign matter weighs Array film layer wounded, the problem of so as to cause GDS phenomenon.
To solve the above-mentioned problems, the invention discloses a kind of Electronic Paper pixel units, which is characterized in that the Electronic Paper
Pixel unit includes the tft layer to be formed on substrate, the protective layer being covered on the tft layer, and
It is formed in the pixel electrode layer that the protective layer deviates from the tft layer side；
The source and drain gold that the pixel electrode layer passes through the first via hole and the tft layer through the protective layer
Belong to layer coupling；Wherein, the protective layer includes the insulating layer and flatness layer being stacked.
Optionally, the tft layer includes the gate metal layer being stacked, gate insulating layer, active layer and institute
State Source and drain metal level, wherein the gate metal layer setting is over the substrate；
The first metal layer is additionally provided on the substrate, the first metal layer and the gate metal layer same layer are arranged；
The Electronic Paper pixel unit further includes the second metal layer with Source and drain metal level same layer setting；
The pixel electrode layer is coupled by the second via hole and the first metal layer, and second via hole runs through the guarantor
Sheath, and part is through the gate insulating layer between the Source and drain metal level and the second metal layer.
Optionally, first via hole is connected with second via hole.
Optionally, the pixel electrode layer and the first metal layer and pixel electrode signal wire couple, the second metal layer
It is coupled with common electrode signal line.
Optionally, the insulating layer is covered on the tft layer, and the flatness layer is located at insulating layer back
Side from the tft layer.
Optionally, the flatness layer is covered on the tft layer, and the insulating layer is located at flatness layer back
Side from the tft layer.
The invention also discloses a kind of Electronic Paper dot structures, the Electronic Paper pixel unit including array arrangement.
The invention also discloses a kind of Electronic Papers, including Electronic Paper dot structure.
The invention also discloses a kind of Electronic Paper pixel unit preparation methods, comprising:
Substrate is provided；
Tft layer is prepared over the substrate；
Form protective layer on the tft layer, the protective layer includes the insulating layer being stacked and flat
Layer；
Form the first via hole for running through the protective layer；
Pixel electrode layer is formed on the protective layer, the pixel electrode layer passes through first via hole and the film
The Source and drain metal level of transistor layer couples.
It is optionally, described to prepare tft layer over the substrate, comprising:
Gate metal layer and the first metal layer are formed over the substrate；
Form the gate insulating layer for covering the gate metal layer and the first metal layer；
Active layer is formed on the gate insulating layer；
Metal layer is covered on the active layer；
Patterned process is carried out to the metal layer, forms Source and drain metal level and second metal layer；
The method also includes:
It is formed and runs through the protective layer, and part is through the grid between the Source and drain metal level and the second metal layer
The second via hole of insulating layer；
Wherein, the pixel electrode layer is coupled by second via hole and the first metal layer.
Compared with prior art, the present invention includes the following advantages:
The embodiment of the invention discloses a kind of Electronic Paper pixel units, including forming tft layer on substrate,
The protective layer being covered on the tft layer, and the protective layer is formed in away from the tft layer side
Pixel electrode layer；The source that the pixel electrode layer passes through the first via hole and the tft layer through the protective layer
Leak metal layer coupling；Wherein, the protective layer includes the insulating layer and flatness layer being stacked.The embodiment of the present invention is in Electronic Paper
Increase the flatness layer being stacked with insulating layer in pixel unit, the setting of the flatness layer increase tft layer with
Dielectric material thickness between pixel electrode layer weighs Array film wounded so as to avoid in blue film wire printed network version printing process foreign matter
Layer, ability is hurt in the resistance to compression for improving the Electronic Paper, and then improves the yield of product.
Detailed description of the invention
Fig. 1 is the Electronic Paper pixel unit film layer structure schematic diagram in background of invention；
Fig. 2 is one of embodiment of the present invention one Electronic Paper pixel unit film layer structure schematic diagram；
Fig. 3 is another Electronic Paper pixel unit film layer structure schematic diagram in the embodiment of the present invention one；
Fig. 4 is another Electronic Paper pixel unit schematic diagram in the embodiment of the present invention one；
Fig. 5 is the structural schematic diagram of storage capacitance in one of embodiment of the present invention one Electronic Paper pixel cell structure；
Fig. 6 is a kind of step flow chart of pixel unit preparation method of the embodiment of the present invention four；
Fig. 7 is a kind of sub-step flow chart of pixel unit preparation method of the embodiment of the present invention four.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Embodiment one
Referring to Fig. 2, a kind of Electronic Paper pixel cell structure schematic diagram of the embodiment of the present invention one, the Electronic Paper are shown
Pixel unit includes the tft layer 201 to be formed on substrate, the protective layer being covered on the tft layer
202, and it is formed in the pixel electrode layer 203 that the protective layer deviates from the tft layer side；
The pixel electrode layer 203 passes through through the first via hole 204 of the protective layer and the tft layer 201
Source and drain metal level coupling；Wherein, the protective layer 202 includes the insulating layer and flatness layer being stacked.
In the embodiment of the present invention, the protective layer 202 includes the insulating layer and flatness layer being stacked, and compares existing skill
Art, the embodiment of the present invention are additionally arranged flatness layer, the setting of the flatness layer increase tft layer and pixel electrode layer it
Between dielectric material thickness, weigh Array film layer wounded so as to avoid in blue film wire printed network version printing process foreign matter, improve described
Ability is hurt in the resistance to compression of Electronic Paper, and then improves the yield of product.
As a kind of specific example, the material that the flatness layer is made includes resin material or other high molecular materials.
Optionally, a kind of Electronic Paper pixel unit film layer structure schematic diagram is shown with reference to Fig. 3 and Fig. 4, Fig. 3, Fig. 4 is shown
A kind of Electronic Paper pixel unit schematic diagram.The tft layer includes the gate metal layer 2011 being stacked, grid
Insulating layer 2012, active layer 2013 and the Source and drain metal level 2014, wherein the gate metal layer 2021 is arranged in the lining
On bottom；The first metal layer 2015, the first metal layer 2015 and the gate metal layer 2011 are additionally provided on the substrate
Same layer setting；The Electronic Paper pixel unit further includes the second metal layer with 2014 same layer of Source and drain metal level setting
2016；The pixel electrode layer 203 is coupled by the second via hole 2017 with the first metal layer 2015, second via hole
2017 run through the protective layer 202, and part is through between the Source and drain metal level 2014 and the first metal layer 2015
Gate insulating layer 2012.
In the embodiment of the present invention, adding flatness layer will increase dielectric material between tft layer and pixel electrode layer
Thickness weighs Array film layer wounded so as to avoid in blue film wire printed network version printing process foreign matter, but the increase of flatness layer will lead to
The reduction of capacitor between the tft layer and pixel electrode layer of pixel unit, since the maximum advantage of Electronic Paper is low function
Consumption, natural light is utilized in Electronic Paper, is not necessarily to backlight, while it is with low frequency and bistable characteristic, in the case where same picture
Not power consumption, ability only transformation display content when power consumption, and it is to realize that lower pixel electrode signal for a long time and public electrode are believed
The stabilization of number voltage between lines, need to make storage capacitance more big as far as possible in the case where guaranteeing that tft layer can be fully charged more
It is good.Therefore, most important to stablizing for display to the design of storage capacitance in Electronic Paper design.In the prior art, referring to Fig.1,
The source signal of tft layer 101 is connect by 102 via hole of insulating layer with pixel electrode layer 103, and connects pixel jointly
Electrode signal, the public electrode letter of the metal layer connection IC input in 102 underlying film transistor layer of pixel region insulating layer
Number, i.e., there was only insulating dielectric layer material, storage capacitance between common electrode signal and pixel electrode signal are as follows:
Cst=Ci (pvx) * A (Pixel area SD_ITO)
Wherein Ci (pvx) is the capacitor of insulating dielectric layer material unit area, and A (area Pixel SD_ITO is overlapping) is pixel
Area's metal layer and pixel electrode layer overlapping area.
Further, the pixel electrode layer 203 and the first metal layer 2015 and pixel electrode signal wire couple, and described the
Two metal layers 2016 are coupled with common electrode signal line.
In order to guarantee that stablizing for pixel voltage exports, embodiment adds common electrode signals in second metal layer 2016
Setting, pixel electrode signal deposited in the present embodiment in the setting of pixel electrode layer 203 and the first metal layer 2015 referring to Fig. 5
Storage is held are as follows:
Cst=Cst1+Cst2=Ci (pvx_Resin) * A (Pixel area SD_ITO)+Ci (GI) * A (area Pixel SD_
Gate)
Wherein, capacitor of the Cst1 between pixel electrode layer and second metal layer, Cst2 are the first metal layer and grid gold
Belong to the capacitor between layer, Ci (pvx_Resin) is the capacitor of insulating layer and flatness layer parallel unit area, the A (area Pixel SD_
It ITO is) pixel region second metal layer and pixel electrode layer overlapping area, Ci (GI) is gate insulating layer dielectric material unit area
Capacitor, A (Pixel area SD_Gate) is pixel region the first metal layer and gate metal layer overlapping area.
The present embodiment is increased between tft layer and pixel electrode layer by adding flatness layer to increase setting
Dielectric material thickness, the blue film solved in Electronic Paper attach in journey made of paper, are easy to produce the feelings that foreign matter weighs Array film layer wounded
Condition, the phenomenon that leading to GDS.And pixel electrode layer 203 and the first metal layer 2015 are coupled by adding the second through-hole,
And the pixel electrode layer 203 and the first metal layer 2015 and the coupling of pixel electrode signal wire, the second metal layer are set
2016 couple with common electrode signal line, due to increasing pixel electrode signal in the first metal layer, to make total storage electricity
Hold Cst and becomes capacitor Cst1 and second metal layer between second metal layer common electrode signal and gate metal layer picture element signal
Common electrode signal and pixel electrode layer picture element signal between the sum of capacitor Cst2, compensate for due to dielectric material flatness layer
Increase caused by storage capacitance reduction, thus ensure that pixel voltage stablize output.
Optionally, first via hole and the second via hole are connected.
In the embodiment of the present invention, being connected by setting first through hole and the second through-hole can guarantee the first metal layer and pixel
Electrode layer coupling, while Source and drain metal level and pixel electrode layer couple, moreover it is possible to guarantee Source and drain metal level and second metal layer it
Between coupling.Based on this, first through hole is set and is connected with the second through-hole the increasing that can also be compensated due to dielectric material flatness layer
The reduction of storage capacitance caused by adding, to ensure that stablizing for pixel voltage exports.
Optionally, the insulating layer is covered on the tft layer, and the flatness layer is located at insulating layer back
Side from the tft layer.
Or the flatness layer is covered on the tft layer, the insulating layer is located at the flatness layer away from described
The side of tft layer.
The embodiment of the present invention be in order to explain stepped construction between insulating layer and flatness layer, due to add flatness layer be in order to
Dielectric material thickness between tft layer and pixel electrode layer, so to the layered relationship between flatness layer and insulating layer
The present invention is with no restrictions.
The embodiment of the invention discloses a kind of Electronic Paper pixel units, including forming tft layer on substrate,
The protective layer being covered on the tft layer, and the protective layer is formed in away from the tft layer side
Pixel electrode layer；The source that the pixel electrode layer passes through the first via hole and the tft layer through the protective layer
Leak metal layer coupling；Wherein, the protective layer includes the insulating layer and flatness layer being stacked.The embodiment of the present invention is in pixel list
The flatness layer being stacked with insulating layer is increased in member, the setting of the flatness layer increases tft layer and pixel electricity
Dielectric material thickness between the layer of pole, weighs Array film layer wounded so as to avoid in blue film wire printed network version printing process foreign matter, improves
Ability is hurt in the resistance to compression of the Electronic Paper, and then improves the yield of product.The embodiment of the present invention is by adding the second through-hole again
Pixel electrode layer and second metal layer and the first metal layer are coupled, and the pixel electrode layer and the first metal layer are set
It is coupled with pixel electrode signal wire, the second metal layer and common electrode signal line couple, due to increasing in the first metal layer
Pixel electrode signal, so that total storage capacitance Cst be made to become second metal layer common electrode signal and gate metal layer picture
Capacitor between capacitor Cst1 between plain signal and the common electrode signal and pixel electrode layer picture element signal of second metal layer
The sum of Cst2 compensates for the reduction of storage capacitance caused by the increase due to dielectric material flatness layer, to ensure that pixel
Voltage stablizes output.
Embodiment two
The embodiment of the invention discloses a kind of Electronic Paper dot structures, the Electronic Paper pixel unit including array arrangement.Institute
Stating Electronic Paper pixel unit includes the tft layer to be formed on substrate, the protection being covered on the tft layer
Layer, and it is formed in the pixel electrode layer that the protective layer deviates from the tft layer side；The pixel electrode layer is logical
It crosses and is coupled through the first via hole of the protective layer and the Source and drain metal level of the tft layer；Wherein, the protective layer
Including the insulating layer and flatness layer being stacked.
The embodiment of the present invention increases the flatness layer being stacked with insulating layer in pixel unit, and the flatness layer is set
The dielectric material thickness increased between tft layer and pixel electrode layer is set, is printed so as to avoid in blue film wire printed network version
Swiped through journey foreign matter weighs Array film layer wounded, and ability is hurt in the resistance to compression for improving the Electronic Paper, and then improves the yield of product.
Embodiment three
The embodiment of the invention discloses a kind of Electronic Papers, including Electronic Paper dot structure.
In the embodiment of the present invention, since the Electronic Paper dot structure includes Electronic Paper pixel unit above-mentioned, and institute
Stating Electronic Paper pixel unit includes the tft layer to be formed on substrate, the protection being covered on the tft layer
Layer, and it is formed in the pixel electrode layer that the protective layer deviates from the tft layer side；The pixel electrode layer is logical
It crosses and is coupled through the first via hole of the protective layer and the Source and drain metal level of the tft layer；Wherein, the protective layer
Including the insulating layer and flatness layer being stacked.The embodiment of the present invention increases in pixel unit to be stacked with insulating layer
The setting of flatness layer, the flatness layer increases the dielectric material thickness between tft layer and pixel electrode layer, thus
It avoiding and weighs Array film layer wounded in blue film wire printed network version printing process foreign matter, ability is hurt in the resistance to compression for improving the Electronic Paper, into
And improve the yield of product.
Example IV
The embodiment of the invention discloses a kind of Electronic Paper pixel unit preparation methods, referring to Fig. 6, which comprises
Step 401, substrate is provided.
In the embodiment of the present invention, the substrate can be glass substrate.
Step 402, tft layer is prepared over the substrate.
In the embodiment of the present invention, referring to Fig. 7, prepares the thin film transistor (TFT) and include the following steps: step 4021, described
Gate metal layer and the first metal layer are formed on substrate；Step 4022, it is formed and covers the gate metal layer and first gold medal
Belong to the gate insulating layer of layer；Step 4023, active layer is formed on the gate insulating layer；Step 4024, in the active layer
Upper covering metal layer；Step 4025, patterned process is carried out to the metal layer, forms Source and drain metal level and second metal layer.
Step 403, protective layer is formed on the tft layer, the protective layer includes the insulating layer being stacked
And flatness layer.
The embodiment of the present invention in pixel unit by increasing the flatness layer being stacked with insulating layer, the flatness layer
Setting increase the dielectric material thickness between tft layer and pixel electrode layer, so as to avoid in blue film wire printed network
Version printing process foreign matter weighs Array film layer wounded, and ability is hurt in the resistance to compression for improving the Electronic Paper, and then improves the good of product
Rate.
Step 404, the first via hole for running through the protective layer is formed.
Step 405, form pixel electrode layer on the protective layer, the pixel electrode layer by first via hole with
The Source and drain metal level of the tft layer couples.
In the embodiment of the present invention, first via hole is used for the Source and drain metal level of pixel electrode layer and tft layer
Coupling, the Source and drain metal level and second metal layer same layer are arranged, and the second metal layer and common electrode signal line couple, institute
Pixel electrode layer and common pixels electrode signal is stated to couple, thus first via hole make pixel electrode layer and Source and drain metal level it
Between can carry out transmitting between common electrode signal or pixel electrode signal.
Optionally, the method also includes:
It is formed and runs through the protective layer, and part is through the grid between the Source and drain metal level and the second metal layer
The second via hole of insulating layer；
Wherein, the pixel electrode layer is coupled by second via hole and the first metal layer.
In the embodiment of the present invention, second via hole is used to couple the pixel electrode layer and the first metal layer,
According to aforementioned it is found that first via hole is connected with second via hole, so the Source and drain metal level passes through described first
Via hole and second via hole and the first metal layer couple, therefore can between the Source and drain metal level and the first metal layer
To carry out the transmitting between common electrode signal or pixel electrode signal.The embodiment of the present invention makes picture by adding the second through-hole again
Plain electrode layer and second metal layer and the first metal layer couple, and the pixel electrode layer and the first metal layer and picture is arranged
Plain electrode signal line coupling, the second metal layer and common electrode signal line couple, due to increasing picture in the first metal layer
Plain electrode signal, so that total storage capacitance Cst be made to become second metal layer common electrode signal and gate metal layer pixel letter
Capacitor Cst2 between capacitor Cst1 between number and the common electrode signal and pixel electrode layer picture element signal of second metal layer
The sum of, the reduction of storage capacitance caused by the increase due to dielectric material flatness layer is compensated for, to ensure that pixel voltage
Stablize output.
For the various method embodiments described above, for simple description, therefore, it is stated as a series of action combinations, but
Be those skilled in the art should understand that, the present invention is not limited by the sequence of acts described because according to the present invention, certain
A little steps can be performed in other orders or simultaneously.Secondly, those skilled in the art should also know that, it is retouched in specification
The embodiment stated belongs to preferred embodiment, and related actions and modules are not necessarily necessary for the present invention.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, commodity or the equipment that include a series of elements not only include that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, commodity or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in process, method, commodity or the equipment for including the element.
Above to a kind of static release circuit provided by the present invention, display panel, display device and Electro-static Driven Comb side
Method is described in detail, and used herein a specific example illustrates the principle and implementation of the invention, above
The explanation of embodiment is merely used to help understand method and its core concept of the invention；Meanwhile for the general skill of this field
Art personnel, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, in conclusion this
Description should not be construed as limiting the invention.
Claims (10)
1. a kind of Electronic Paper pixel unit, which is characterized in that the Electronic Paper pixel unit includes the film to be formed on substrate
Transistor layer, the protective layer being covered on the tft layer, and the protective layer is formed in away from the film crystalline substance
The pixel electrode layer of body tube layer side；
The Source and drain metal level that the pixel electrode layer passes through the first via hole and the tft layer through the protective layer
Coupling；Wherein, the protective layer includes the insulating layer and flatness layer being stacked.
2. pixel unit according to claim 1, which is characterized in that the tft layer includes the grid being stacked
Pole metal layer, gate insulating layer, active layer and the Source and drain metal level, wherein the gate metal layer is arranged in the substrate
On；
The first metal layer is additionally provided on the substrate, the first metal layer and the gate metal layer same layer are arranged；
The Electronic Paper pixel unit further includes the second metal layer with Source and drain metal level same layer setting；
The pixel electrode layer is coupled by the second via hole and the first metal layer, and second via hole runs through the protection
Layer, and part is through the gate insulating layer between the Source and drain metal level and the first metal layer.
3. pixel unit according to claim 2, which is characterized in that first via hole is connected with second via hole
It is logical.
4. pixel unit according to claim 2, which is characterized in that the pixel electrode layer and the first metal layer and pixel
The coupling of electrode signal line, the second metal layer and common electrode signal line couple.
5. according to the described in any item pixel units of claim 4, which is characterized in that it is brilliant that the insulating layer is covered on the film
In body tube layer, the flatness layer is located at the side that the insulating layer deviates from the tft layer.
6. according to any pixel unit of claim 4, which is characterized in that the flatness layer is covered on the film crystal
In tube layer, the insulating layer is located at the side that the flatness layer deviates from the tft layer.
7. a kind of Electronic Paper dot structure, which is characterized in that the electronics as described in claim 1-6 is any including array arrangement
Paper pixel unit.
8. a kind of Electronic Paper, which is characterized in that including Electronic Paper dot structure as claimed in claim 7.
9. a kind of Electronic Paper pixel unit preparation method characterized by comprising
Substrate is provided；
Tft layer is prepared over the substrate；
Protective layer is formed on the tft layer, the protective layer includes the insulating layer and flatness layer being stacked；
Form the first via hole for running through the protective layer；
Pixel electrode layer is formed on the protective layer, the pixel electrode layer passes through first via hole and the film crystal
The Source and drain metal level of tube layer couples.
10. according to the method described in claim 9, it is characterized in that, described prepare tft layer, packet over the substrate
It includes:
Gate metal layer and the first metal layer are formed over the substrate；
Form the gate insulating layer for covering the gate metal layer and the first metal layer；
Active layer is formed on the gate insulating layer；
Metal layer is covered on the active layer；
Patterned process is carried out to the metal layer, forms Source and drain metal level and second metal layer；
The method also includes:
It is formed and runs through the protective layer, and part is through the gate insulator between the Source and drain metal level and the second metal layer
The second via hole of layer；
Wherein, the pixel electrode layer is coupled by second via hole and the first metal layer.
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| CN201910818751.7A CN110515252B (en) | 2019-08-30 | 2019-08-30 | Electronic paper pixel unit and preparation method thereof |
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| CN201910818751.7A CN110515252B (en) | 2019-08-30 | 2019-08-30 | Electronic paper pixel unit and preparation method thereof |
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| CN110515252B CN110515252B (en) | 2024-02-20 |
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| CN113013052A (en) * | 2019-12-19 | 2021-06-22 | 京东方科技集团股份有限公司 | Screen printing plate, protective film printing method and protective film |
| CN113687550A (en) * | 2021-08-25 | 2021-11-23 | 福州京东方光电科技有限公司 | Array substrate, preparation method thereof and electronic paper display device |
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| CN110515252B (en) | 2024-02-20 |
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