CN115202126A

CN115202126A - Array substrate and electronic paper display device

Info

Publication number: CN115202126A
Application number: CN202210882032.3A
Authority: CN
Inventors: 席文星; 邹振游; 王为旺; 余雪; 王洋; 林滨; 李增荣; 谢鑫
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2022-07-26
Filing date: 2022-07-26
Publication date: 2022-10-18

Abstract

The embodiment of the invention discloses an array substrate and an electronic paper display device. In a specific embodiment, the array substrate includes a gate line and a data line on a substrate, the gate line and the data line intersect to define a plurality of pixel regions, the plurality of pixel regions form a display region, the pixel region includes a dual-gate thin film transistor and a pixel electrode on the substrate, the dual-gate thin film transistor includes a first gate, a second gate, a first electrode, a bridging electrode and a second electrode, a first active region is arranged between the first gate and the first electrode, the bridging electrode, and a second active region is arranged between the second gate and the bridging electrode, and the second electrode; the film layer of the first active region facing the substrate is formed with a first slope and/or the film layer of the second active region facing the substrate is formed with a second slope, at least part of the first active region being formed on the first slope and/or at least part of the second active region being formed on the second slope. This embodiment can improve the pixel aperture ratio.

Description

Array substrate and electronic paper display device

Technical Field

The invention relates to the technical field of display. And more particularly, to an array substrate and an electronic paper display device.

Background

An electronic paper Display device based on an Electrophoretic Display (EPD) technology is a Display product which realizes Display by utilizing natural environment light reflection without the support of a backlight source. Because of the advantages of low power consumption, high visual angle, high portability, strong flexibility, small limitation of substrate materials and the like, the Electronic Shelf Label is widely applied to scenes such as home, transportation, business, education, entertainment and the like, for example, an Electronic Shelf Label (ESL) commonly seen in supermarkets. At present, the existing electronic paper display device has the problems of low pixel aperture ratio and the like due to the performance requirements of the array substrate such as storage capacitance, leakage current and the like.

Disclosure of Invention

The present invention is directed to an array substrate and an electronic paper display device to solve at least one of the problems of the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides an array substrate for an electronic paper display device, which comprises a grid line and a data line which are positioned on a substrate, wherein the grid line and the data line are crossed to define a plurality of pixel regions, the pixel regions form a display region, the pixel regions comprise a double-grid thin film transistor and a pixel electrode which are positioned on the substrate, the double-grid thin film transistor comprises a first grid electrode, a second grid electrode, a first electrode, a bridging electrode and a second electrode, a first active region is arranged between the first grid electrode and the first electrode as well as between the first grid electrode and the bridging electrode, and a second active region is arranged between the second grid electrode and the bridging electrode as well as between the second grid electrode and the bridging electrode; the film layer of the first active region facing the substrate is provided with a first inclined surface and/or the film layer of the second active region facing the substrate is provided with a second inclined surface, and at least part of the first active region is formed on the first inclined surface and/or at least part of the second active region is formed on the second inclined surface.

Optionally, the pixel electrode comprises a metal electrode.

Optionally, the first gate, the second gate and the pixel electrode are disposed in the same layer.

Optionally, the array substrate further includes a switching area located at the periphery of the display area, and the switching hole of the switching area is electrically connected to the peripheral circuit by using a metal layer disposed on the same layer as the metal electrode.

Optionally, the array substrate further includes a common electrode and an insulating layer, the first electrode and the common electrode are disposed on the substrate in the same layer, the insulating layer covers the first electrode and the common electrode, the first active region and the second active region are disposed on the insulating layer in the same layer, and the insulating layer is provided with a first opening exposing the first electrode so that the first electrode is electrically connected to the first active region.

Optionally, the insulating layer has a protrusion to form the first slope and the second slope.

Optionally, the first active region and the second active region are in communication, the bridging electrode is disposed at the position of the communication, and the second electrode is disposed on the exposed insulating layer and is electrically connected to the second active region.

Optionally, the array substrate further includes a passivation layer covering the exposed first active region, the exposed second active region, the bridge electrode, the second electrode, and the exposed insulating layer, the pixel electrode is disposed on the passivation layer, and the passivation layer is provided with a second opening exposing the second electrode so that the second electrode is electrically connected to the pixel electrode.

Optionally, the first gate, the second gate and the pixel electrode are disposed on the passivation layer at the same layer.

Optionally, the pixel electrode comprises a metal electrode and a first metal oxide film disposed on the metal electrode; the first grid electrode, the second grid electrode and the metal electrode are arranged on the passivation layer at the same layer, the first grid electrode comprises a first metal grid electrode and a second metal oxide film arranged on the first metal grid electrode, and the second grid electrode comprises a second metal grid electrode and a third metal oxide film arranged on the second metal grid electrode.

Optionally, the array substrate further includes a switching area located at the periphery of the display area, the switching hole of the switching area is electrically connected to the peripheral circuit by using a metal layer disposed on the same layer as the metal electrode, and the array substrate further includes a fourth metal oxide film disposed on the metal layer.

Optionally, the first active region and the second active region are formed in an active layer, and an orthographic projection of the active layer on the substrate covers an orthographic projection of the pixel electrode on the substrate.

The second aspect of the invention provides an electronic paper display device, which comprises the array substrate provided by the first aspect of the invention.

The invention has the following beneficial effects:

according to the technical scheme, the double-gate thin film transistor is designed into a three-dimensional device, the size of the double-gate thin film transistor is reduced, specifically, the area of the double-gate thin film transistor in a plane parallel to a substrate is reduced, and further, the area proportion of the double-gate thin film transistor in a pixel area is reduced under the condition that the channel width-length ratio of the double-gate thin film transistor is ensured, so that the area proportion of a pixel electrode in the pixel area can be improved, the pixel aperture ratio is improved, and the defects of residual images (Ghosting) and the like are improved.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating the positions of dual gate thin film transistors in a pixel region of an array substrate in a conventional electronic paper display device.

Fig. 2 is a schematic diagram illustrating the positions of dual-gate tfts in a pixel region of an array substrate of an electronic paper display device according to an embodiment of the present invention.

Fig. 3 illustrates a top perspective view of a pixel region of the array substrate shown in fig. 2.

Fig. 4-7 are schematic diagrams illustrating stages in a method for manufacturing the array substrate in the electronic paper display device shown in fig. 2 according to an embodiment of the present invention.

Fig. 8 is another schematic diagram illustrating a location of a dual-gate thin film transistor in a pixel region of an array substrate in an electronic paper display device according to an embodiment of the present invention.

Fig. 9 and 10 are schematic diagrams illustrating stages corresponding to a method for manufacturing an array substrate in the electronic paper display device shown in fig. 8 according to an embodiment of the present invention.

Fig. 11 is a schematic diagram illustrating a transfer area of an array substrate in an electronic paper display device according to an embodiment of the present invention.

Detailed Description

The terms "on … …", "on … …" and "on … …" as used herein may mean that one layer is formed or provided directly on another layer, or that one layer is formed or provided indirectly on another layer, i.e., there is another layer between the two layers.

It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present invention.

In the present invention, unless otherwise specified, the term "disposed on the same layer" is used to mean that two layers, components, members, elements or portions may be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements or portions are generally formed of the same material. For example, two or more functional layers are arranged in the same layer, which means that the functional layers arranged in the same layer can be formed by using the same material layer and using the same manufacturing process, so that the manufacturing process of the display substrate can be simplified.

In the present invention, unless otherwise specified, the expression "patterning process" generally includes steps of coating of a photoresist, exposure, development, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.

At present, the existing electronic paper display device has the problems of low pixel aperture ratio and the like due to the performance requirements of the array substrate such as storage capacitance, leakage current and the like. Specifically, the existing electronic paper display device is a reflective bistable display device using ambient light without a backlight. In the design of the array substrate thereof, on one hand, it is required that the pixel has a storage capacitance (Cst) as large as possible in order to maintain a voltage between the pixel electrode and the common electrode (Vcom) for a long time, and therefore, the size of the Thin Film Transistor (TFT) device in the array substrate of the electronic paper display device is generally designed to be larger than that of the thin film transistor device in the array substrate of the display device such as a Liquid Crystal Display (LCD), and on the other hand, in order to reduce a leakage current (Ioff) as small as possible, the thin film transistor device in the array substrate of the electronic paper display device employs a double gate structure, that is, the thin film transistor device employs a double gate thin film transistor, and thus, the size of the thin film transistor device in the array substrate of the electronic paper display device is further increased, and the area thereof in a plane parallel to the substrate is large.

The existing electronic paper display device comprises an array substrate and an electronic ink layer, wherein the electronic ink layer comprises at least two dyeing particles with different electric properties. Fig. 1 shows a dual gate thin film transistor location of a pixel region of an array substrate in a conventional electronic paper display device, and the location has a structure including: a substrate 100, a first Gate electrode (Gate) 101, a second Gate electrode 102, and a common electrode (Vcom) 103 formed on the substrate 100, an insulating layer (Insulator) 104 (the insulating layer 104 may be referred to as a Gate insulating layer) covering the first Gate electrode 101, the second Gate electrode 102, and the common electrode 103, an Active layer formed on the insulating layer 104, a first Active region (Active) 1051 and a second Active region 1052 formed in the Active layer, a Source electrode (Source) 106, a bridge electrode 107, and a Drain electrode (Drain) 108 formed on the Active layer 105, a passivation layer (PVX) 109 covering the Source electrode 106, the bridge electrode 107, and the Drain electrode 108, the passivation layer 109 forming an opening to expose the Drain electrode 108, a pixel electrode 110 formed on the passivation layer 109, the pixel electrode 110 being electrically connected to the Drain electrode through the opening, the pixel electrode 110 being a metal oxide thin film, such as an Indium Tin Oxide (ITO) thin film. The first gate 101 and the second gate 102 are disposed in the same layer and are electrically connected to the gate line, respectively, the source 106, the bridge electrode 107, and the drain 108 are disposed in the same layer, the source 106 is electrically connected to the data line, the bridge electrode 107 can be divided into a first bridge electrode region on the left side and a second bridge electrode region on the right side, the first active layer region 1051 forms a first channel between the source 106 and the first bridge electrode region, the second active layer region 1052 forms a second channel between the second bridge electrode region and the drain 108, one thin film transistor structure of the dual-gate thin film transistor is formed by the first gate 101, the source 106, the bridge electrode 107 (specifically, the first bridge electrode region on the left side of the bridge electrode 107), and the first active layer region 1051, the other thin film transistor structure of the dual-gate thin film transistor is formed by the second gate 102, the bridge electrode 107 (specifically, the second bridge electrode region on the right side of the bridge electrode 107), the drain 108, and the second active layer region 1052, and the two thin film transistor structures are matched to realize the structure and function of the dual-gate thin film transistor. In addition, since the electronic paper display device is a reflective display device, the existing electronic paper display device also generally provides a reflective metal layer for reflecting ambient light on the substrate 100.

As shown in fig. 1, it can be seen that the pixel electrode 110 in the array substrate of the electronic paper display device is designed not to cover the thin film transistor device because, if the orthographic projection of the pixel electrode 110 on the substrate 100 covers the orthographic projection of the thin film transistor device on the substrate 100, the pixel electrode, the passivation layer 109 and the Active area (Active) covering the thin film transistor device would form an MIS structure (a structure composed of metal (M) -insulator (I) -semiconductor (S)), thereby causing an increase in the leakage current of the thin film transistor device, and therefore, the pixel electrode 110 would avoid covering the thin film transistor device, so that, in the case of a large thin film transistor device size (a large area in a plane parallel to the substrate), there would be a large pixel electrode Gap (Gap) above the thin film transistor device, which affects the pixel aperture ratio and the screen fineness is low. When the electronic paper display device displays, the pixel electrode is in a vertical electric field, so that the corresponding dyed particles can be normally driven, the gap of the pixel electrode only acts on a weak non-vertical edge electric field, the corresponding dyed particles cannot be effectively driven, and a residual image (ghost) defect is generated, for example, in a black background, red bright spots regularly distributed exist in the area.

In view of the above, an embodiment of the present invention provides an electronic paper display device, which includes an array substrate and an electronic ink layer, wherein the electronic ink layer includes at least two different types of dyed particles. As shown in fig. 2 and 3, the array substrate includes a gate line and a data line on a substrate 200, the gate line and the data line intersect to define a plurality of pixel regions, the plurality of pixel regions form a display region, the pixel region includes a dual-gate thin film transistor and a pixel electrode 210 on the substrate 200, the dual-gate thin film transistor includes a first gate 201, a second gate 202, a first electrode 203 such as a source, a bridge electrode 204, and a second electrode 205 such as a drain, a first active region 2061 is disposed between the first gate 201 and the first electrode 203, between the first gate 202 and the bridge electrode 204, and between the second gate 202 and the bridge electrode 204, between the second gate 205, a second active region 2062 is disposed; the film layer of the side of the first active region 2061 facing the substrate 200 is formed with a first slope and/or the film layer of the side of the second active region 2062 facing the substrate 200 is formed with a second slope, at least part of the first active region 2061 being formed on the first slope and/or at least part of the second active region 2062 being formed on the second slope. For example, as shown in fig. 2, in the present embodiment, a film layer of the first active region 2061 facing the substrate 200 is formed with a first inclined surface and a film layer of the second active region 2062 facing the substrate 200 is formed with a second inclined surface.

It can be understood that, in the array substrate provided in this embodiment, the first gate 201 and the second gate 202 are respectively electrically connected to the gate line, the first electrode 203 is electrically connected to the data line, the bridging electrode 204 can be divided into a first bridging electrode region on the left side and a second bridging electrode region on the right side in fig. 2, the first active layer region 2061 forms a first channel between the first electrode 203 and the first bridging electrode region, the second active layer region 2 forms a second channel between the second bridging electrode region and the second electrode 205, one thin film transistor structure of the double-gate thin film transistor is formed by the first gate 201, the first electrode 203, the bridging electrode 204 (specifically, the first bridging electrode region on the left side of the bridging electrode 204) and the first active layer region 2061, and the other thin film transistor structure of the double-gate thin film transistor is formed by the second gate 202, the bridging electrode 204 (specifically, the second bridging electrode region on the right side of the bridging electrode 204), the second electrode 205 and the second double-gate thin film transistor structure 2062, and the function of the double-gate thin film transistor are realized by the cooperation of the two thin film transistor structures. As shown in fig. 2, the orthographic projection of the first gate 201 on the substrate 200 covers the orthographic projection of the first active layer region 2061 on the substrate 200, and the orthographic projection of the first gate 202 on the substrate 200 covers the orthographic projection of the second active layer region 2062 on the substrate 200. Taking the first gate 201 as an example, the orthographic projection of the first gate 201 on the substrate 200 covers the orthographic projection of the first active layer region 2061 on the substrate 200 because to form a MISFET device, the conduction principle of the first active layer region 2061 is that it is necessary to forward bias through the first gate 201 to form carrier accumulation in the front channel, and when the field reaches a certain value, the first channel can conduct to change from a semiconductor to a conductor by adding the pressure difference between vsds. In one specific example, the first active layer region 2061 and the second active layer region 2062 can be formed using a material such as polysilicon and a metal oxide (e.g., IGZO).

In the electronic paper display device provided in this embodiment, at least a portion of the first active region 2061 is formed on the first inclined surface and/or at least a portion of the second active region 2062 is formed on the second inclined surface, so that the dual-gate thin film transistor of the array substrate is designed as a three-dimensional device, the size of the dual-gate thin film transistor is reduced, specifically, the area of the dual-gate thin film transistor in a plane parallel to the substrate 200 is reduced, and further, under the condition that the width-to-length ratio of the channel (the first active region 2061 forms the first channel and the second active region 2062 forms the second channel) of the dual-gate thin film transistor is ensured, the area ratio of the dual-gate thin film transistor in the pixel region is reduced, so that the area ratio of the pixel electrode in the pixel region can be increased, the pixel aperture ratio is increased, the screen fineness is increased, and defects such as afterimage (Ghosting) are improved.

It should be noted that the first inclined surface formed by the film layer of the first active region 2061 facing the substrate 200 and the second inclined surface formed by the film layer of the second active region 2062 facing the substrate 200 may be implemented by designing the thickness of the film layers, designing the overlap with other film layers, and the like. In addition, as shown in fig. 2, the first gate 201 and the second gate 202 are also at least partially formed on the inclined surface, and since the first gate 201 and the second gate 202 are orthographically corresponding to the first active region 2061 and the second active region 2062, respectively, the dual-gate thin film transistor can be downsized as long as at least a portion of the first active region 2061 and/or the second active region 2062 is formed on the inclined surface, regardless of whether the first gate 201 and the second gate 202 are formed on the inclined surface. According to the structure shown in fig. 2, since the first active region 2061 and the second active region 2062 are formed at least partially on the inclined surfaces, respectively, the first gate 201 and the second gate 202 are naturally formed at least partially on the inclined surfaces, respectively, on the basis of the subsequent process.

In one possible implementation manner, as shown in fig. 2, the array substrate further includes a common electrode 207 and an insulating layer 208, the first electrode 203 and the common electrode 207 are disposed on the substrate 200 in the same layer, the insulating layer 208 covers the first electrode 203 and the common electrode 207 (for example, the first electrode 203 is a source electrode, and the insulating layer 208 may be referred to as a source insulating layer), the first active region 2061 and the second active region 2062 are disposed on the insulating layer 208 in the same layer, and the insulating layer 208 is provided with a first opening that exposes the first electrode 203 so that the first electrode is electrically connected to the first active region 2061.

In one possible implementation, as shown in fig. 2, the insulating layer 208 has a raised portion to form a first slope and a second slope, and further, at least a portion of the first active layer region 2061 is formed on the first slope formed by the raised portion of the insulating layer 208 and at least a portion of the second active layer region 2062 is formed on the second slope formed by the raised portion of the insulating layer 208. As shown in fig. 2, the protruding portion of the insulating layer 208 is realized by the thickness design and the overlapping design of the first electrode 203 and the insulating layer 208.

In one possible implementation, as shown in fig. 2, the first active region 2061 and the second active region 2062 are in communication, the bridging electrode 204 is disposed at a communication location, as shown in fig. 2, that is, on top of the raised portion of the insulating layer 208, and the second electrode 205 is electrically connected to the second active region 2062.

In one possible implementation manner, as shown in fig. 2, the array substrate further includes a passivation layer 209 covering the exposed first active region 2061, the exposed second active region 2062, the bridging electrode 204, the second electrode 205 and the exposed insulating layer 208, the pixel electrode 210 is disposed on the passivation layer 209, and the passivation layer 209 is provided with a second opening exposing the second electrode 205 so as to electrically connect the second electrode 205 with the pixel electrode 210.

In one possible implementation, as shown in fig. 2, the pixel electrode 210 includes a metal electrode 2101.

From this, the metal electrode 2101 of accessible high reflectivity forms the reflection to ambient light, need not singly establish the reflection metal layer again on substrate 200, combines metal electrode 2101 at the surface rete of array substrate, compares in the non-surface rete of the reflection metal layer setting at array substrate of current structure, and the reflection stratum is closer to the user, and the reflection effect is better, and visual readability under weak ambient light will show more excellently, and the display effect is outstanding, friendly.

In a specific example, the metal electrode 2101 may employ a metal such as copper (Cu), silver (Ag), aluminum (Al), molybdenum (Mo), or an alloy thereof.

In one possible implementation manner, as shown in fig. 2, the first gate 201 and the second gate 202 are disposed at the same layer as the pixel electrode 210, that is, the first gate 201 includes a first metal gate 2011 disposed at the same layer as the metal electrode 2101, and the second gate 202 includes a second metal gate 2021 disposed at the same layer as the metal electrode 2101. As shown in fig. 2, the first gate 201, the second gate 202 and the pixel electrode 210 are disposed on the passivation layer 209 at the same layer in combination with the pixel electrode 210 disposed on the passivation layer 209.

In one possible implementation, as shown in fig. 2, the pixel electrode 210 includes a metal electrode 2101 and a first metal oxide thin film 2102 disposed on the metal electrode 2101; the first gate 201, the second gate 202 and the pixel electrode 210 are disposed on the passivation layer 209 at the same layer, the first gate 201 includes a first metal gate 2011 and a second metal oxide film 2012 disposed on the first metal gate 2011, and the second gate 202 includes a second metal gate 2021 and a third metal oxide film 2022 disposed on the second metal gate 2021.

In a specific example, the first metal oxide film 2102, the second metal oxide film 2012, and the third metal oxide film 2022 are disposed in the same layer, and for example, metal oxides such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and the like may be used.

In one specific example, the thicknesses of the metal electrode 2101, the first metal gate 2011, and the second metal gate 2021 are set as desired, for example, as set as

For example specifically are

The thicknesses of the first metal oxide film 2102, the second metal oxide film 2012, and the third metal oxide film 2022 are set to, for example, the same

The first metal oxide film 2102, the second metal oxide film 2012 and the third metal oxide film 2022 are respectively used as a portion of the pixel electrode 210, the first gate 201 and the second gate 202, and mainly aim to encapsulate and protect the metal electrode 2101, the first metal gate 2011 and the second metal gate 2021 which are made of copper (Cu), so as to prevent the metal electrode 2101, the first metal gate 2011 and the second metal gate 2021 from being corroded due to oxidation or moisture in a subsequent electronic paper bonding process. Note that the first metal oxide film, the second metal oxide film, and the third metal oxide film may be omitted from the metal electrode 2101, the first metal gate 2011, and the second metal gate 2021 made of aluminum (Al), molybdenum (Mo), or the like.

In one possible implementation, as shown in fig. 2, the first active region 2061 and the second active region 2062 are formed in the active layer 206, and an orthogonal projection of the active layer 206 on the substrate 200 covers an orthogonal projection of the pixel electrode 210 on the substrate 200. As shown in fig. 2, the second electrode 205 is disposed on the active layer 206. Therefore, when the active layer 206 is formed, the active layer 206 of the pixel electrode 210 corresponding to the orthographic projection is not patterned, and a mask etching process can be saved.

The following briefly describes the method for manufacturing the array substrate shown in fig. 2, for example, the manufacturing process includes:

first, a substrate 200 is provided, for example, when the electronic paper display device is a flexible display device, the substrate 200 may be provided of Polyimide (PI), polyethylene naphthalate (PEN), thermoplastic Polyester (PET), or the like; when the electronic paper display device is a rigid display device, the substrate 200 may be a rigid material such as glass, quartz, or the like.

Then, the first electrode 203 such as a source electrode and the common electrode 207 are prepared by, for example: a metal material layer is deposited, then the metal material layer is masked, then the metal material layer is etched, and finally the metal material layer is stripped, so that the patterned first electrode 203 and the patterned common electrode 207 are formed, and the structure shown in fig. 4 is obtained.

Then, the insulating layer 208 is prepared, and the specific processes include: the insulating material is deposited first, and then masking, etching and stripping are performed in sequence to obtain the structure shown in fig. 5. It is to be understood that, in the case where the insulating layer 208 is an organic insulating layer, a buffer layer should be formed on the substrate 200 to block water vapor and impurity particles in the substrate, and the buffer layer may be made of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride.

Then, an active layer 206, a bridge electrode 204, and a second electrode 205 such as a drain electrode are prepared by, for example: the active layer is formed first, then the metal material layer is deposited, then the active layer and the metal material layer are masked at the same time, then drain etching, active layer etching, bridge electrode etching, ASi and N + etching of the reserved active region position are sequentially performed, and finally peeling is performed to form the active layer 206 including the first active region 2061 and the second active region 2062, the bridge electrode 204, and the second electrode 205, so that the structure shown in fig. 6 is obtained. It should be noted that, in order to reduce the product development and production cost, as shown in fig. 6, the active layer region of the pixel electrode 210 corresponding to the orthographic projection may not be patterned, so that the active layer and the metal material layer are prepared by using one mask, thereby reducing the product development and production cost.

Then, a passivation layer 209 is prepared, and the specific processes include: a passivation layer material is deposited first, and then masking, dry etching and stripping are sequentially performed to form a passivation layer 209, resulting in the structure shown in fig. 7. The passivation layer may be made of inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride

Finally, the first gate 201, the second gate 202 and the pixel electrode 210 are prepared, and the specific processes include: depositing a metal material layer, then depositing an Indium Tin Oxide (ITO) material, then performing simultaneous masking of the metal and the ITO, then performing ITO etching and metal etching in sequence, and finally performing lift-off to form a first gate 201, a second gate 202, and a pixel electrode 210, thereby obtaining the structure shown in fig. 2.

Alternatively, an encapsulation layer may be formed after the structure shown in fig. 2 is obtained. For example, the encapsulation layers are a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. For example, the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed by deposition or the like. The organic packaging layer is formed by adopting an ink-jet printing mode. For example, the first inorganic encapsulation layer and the second inorganic encapsulation layer may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride, and the organic encapsulation layer may be formed using an organic material such as Polyimide (PI) or epoxy resin. Therefore, the first inorganic packaging layer, the organic packaging layer and the second inorganic packaging layer form a composite packaging layer, the composite packaging layer can form multiple protection on the functional structure of the display area, and the packaging effect is better.

It should be noted that, in addition to the "orthographic projection of the active layer 206 on the substrate 200 covers the orthographic projection of the pixel electrode 210 on the substrate 200" shown in fig. 2, the array substrate may also adopt a structure as shown in fig. 8, that is, the active layer 206' only exists at the position of the dual-gate thin film transistor, and does not extend to the orthographic projection coverage of the pixel electrode 210. As shown in fig. 8, the second electrode 205 is provided on the insulating layer 208.

For the array substrate structure shown in fig. 8, the preparation process includes, for example:

first, a substrate 200 is provided.

Then, the first electrode 203 such as a source electrode and the common electrode 207 are prepared to obtain a structure as shown in fig. 4.

Then, an insulating layer 208 is prepared, resulting in the structure shown in fig. 5.

Then, the active layer 206 ', the bridging electrode 204 and the second electrode 205, such as the drain electrode, are prepared, and the specific process includes patterning the active layer region of the pixel electrode 210 corresponding to the orthographic projection, so as to form the active layer 206', the bridging electrode 204 and the second electrode 205, which include the first active region 2061 and the second active region 2062, and obtain the structure shown in fig. 9.

Then, a passivation layer 209 is prepared, resulting in the structure shown in fig. 10.

Finally, the first gate 201, the second gate 202 and the pixel electrode 210 are prepared, resulting in the structure shown in fig. 8.

In a possible implementation manner, the array substrate further includes a switching area located at the periphery of the display area, as shown in fig. 11, a switching hole of the switching area is electrically connected to a peripheral circuit by using a metal layer 2101' disposed on the same layer as the metal electrode 2101, so as to implement signal switching. In fig. 11, 203' is a data line extending to the display area. Further, as shown in fig. 11, the array substrate further includes a fourth metal oxide film 2102 'disposed on the metal layer 2101'.

In one specific example, the fourth metal oxide film 2102' is disposed in the same layer as the first metal oxide film 2102, the second metal oxide film 2012, and the third metal oxide film 2022.

In one specific example, the thickness of the metal layer 2101' in the via region of the via region is set as desired, the same as the thickness of the metal electrode 2101, and set as

For example specifically are

In the conventional electronic paper display device, the switching hole of the switching area at the periphery of the display area is electrically connected with a peripheral circuit by using, for example, ITO, which is disposed on the same layer as the pixel electrode 110 of the metal oxide film, so as to implement signal switching. Since it is necessary to ensure that the electronic paper display device has a high reflectivity to ensure visibility of ambient natural light, the ITO is not designed to be thick enough in this structural design, for example

) Therefore, the resistance of the via hole of the switching hole in the switching area is large, which can cause the insufficient current resistance of the via hole, so that the design of the switching hole for signal switching by adopting ITO is very easy to causeThe ITO via holes have a large resistance, which causes the via holes to burn, and further causes the batch H-Line defects (bright Line and dark Line) of the products. The pixel electrode 210 of the embodiment adopts the metal electrode 2101, and further, the problem of via hole burnout in the switching area can be effectively solved by adopting a structural design mode that the switching hole in the switching area is electrically connected with the peripheral circuit through the metal layer 2101' with smaller resistivity and thicker film thickness, which is arranged on the same layer as the metal electrode 2101, and the switching hole in the switching area is burnt out due to larger via hole resistance in the existing structure, so that the major defect of the product batch H-Line caused by the burning out of the switching hole in the switching area can be effectively solved.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations and modifications can be made on the basis of the above description, and all embodiments cannot be exhaustive, and all obvious variations and modifications belonging to the technical scheme of the present invention are within the protection scope of the present invention.

Claims

1. An array substrate is used for an electronic paper display device and comprises a grid line and a data line which are positioned on a substrate, wherein the grid line and the data line are crossed to define a plurality of pixel regions, and the pixel regions form a display region; the film layer of the first active region facing the substrate is provided with a first inclined surface and/or the film layer of the second active region facing the substrate is provided with a second inclined surface, and at least part of the first active region is formed on the first inclined surface and/or at least part of the second active region is formed on the second inclined surface.

2. The array substrate of claim 1, wherein the pixel electrode comprises a metal electrode.

3. The array substrate of claim 1 or 2, wherein the first gate, the second gate and the pixel electrode are disposed on the same layer.

4. The array substrate of claim 2, further comprising a transfer area located at the periphery of the display area, wherein the transfer hole of the transfer area is electrically connected to a peripheral circuit by a metal layer disposed on the same layer as the metal electrode.

5. The array substrate of claim 1, further comprising a common electrode and an insulating layer, wherein the first electrode and the common electrode are disposed on the substrate in the same layer, the insulating layer covers the first electrode and the common electrode, the first active region and the second active region are disposed on the insulating layer in the same layer, and the insulating layer is provided with a first opening exposing the first electrode such that the first electrode is electrically connected to the first active region.

6. The array substrate of claim 5, wherein the insulating layer has a protrusion to form the first and second slopes.

7. The array substrate of claim 6, wherein the first active region and the second active region are in communication, the bridge electrode is disposed at the communication position, and the second electrode is disposed on the exposed insulating layer and electrically connected to the second active region.

8. The array substrate of claim 7, further comprising a passivation layer covering the exposed first active region, the exposed second active region, the bridge electrode, the second electrode, and the exposed insulating layer, wherein the pixel electrode is disposed on the passivation layer, and wherein the passivation layer is provided with a second opening exposing the second electrode such that the second electrode is electrically connected to the pixel electrode.

9. The array substrate of claim 8, wherein the first gate electrode, the second gate electrode and the pixel electrode are disposed on the passivation layer at the same layer.

10. The array substrate of claim 8 or 9, wherein the pixel electrode comprises a metal electrode and a first metal oxide film disposed on the metal electrode; the first grid electrode, the second grid electrode and the metal electrode are arranged on the passivation layer at the same layer, the first grid electrode comprises a first metal grid electrode and a second metal oxide film arranged on the first metal grid electrode, and the second grid electrode comprises a second metal grid electrode and a third metal oxide film arranged on the second metal grid electrode.

11. The array substrate of claim 8, further comprising a via area located at the periphery of the display area, wherein the via hole of the via area is electrically connected to the peripheral circuit by a metal layer disposed on the same layer as the metal electrode, and the array substrate further comprises a fourth metal oxide film disposed on the metal layer.

12. The array substrate of claim 1, wherein the first active region and the second active region are formed in an active layer, and an orthographic projection of the active layer on the substrate covers an orthographic projection of the pixel electrode on the substrate.

13. An electronic paper display device comprising the array substrate according to any one of claims 1 to 12.