CN113675077A - Method for manufacturing semiconductor device - Google Patents
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- CN113675077A CN113675077A CN202110939157.0A CN202110939157A CN113675077A CN 113675077 A CN113675077 A CN 113675077A CN 202110939157 A CN202110939157 A CN 202110939157A CN 113675077 A CN113675077 A CN 113675077A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 230000004888 barrier function Effects 0.000 claims abstract description 136
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000000126 substance Substances 0.000 claims abstract description 58
- 238000000227 grinding Methods 0.000 claims abstract description 51
- 238000007517 polishing process Methods 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims description 39
- 238000005498 polishing Methods 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 25
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 239000010408 film Substances 0.000 description 152
- 239000002184 metal Substances 0.000 description 16
- 239000011810 insulating material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a first graph area and a second graph area, a film layer structure covers the substrate, a recess is formed in the film layer structure on the second graph area, and the depth of the recess exceeds a preset specification; forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film layer structure outside the recess; and grinding the film layer structure outside the recess and the barrier layer on the surface of the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the film layer structure is greater than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification. The invention can improve the smoothness of the surfaces of the patterns with different densities after the chemical mechanical polishing process, thereby improving the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a method for manufacturing a semiconductor device.
Background
In the chip manufacturing process, the device structures in each region on the substrate have different pattern densities and can be divided into a pattern dense region and a pattern sparse region. After the thin film is deposited on the patterns with different densities, a large height difference is formed on the surface of the thin film, even after the Chemical Mechanical Polishing (CMP) process is performed, the thicknesses of the thin film on the patterns with different densities are still different, the flatness of the surface of a device is poor, and the quality of a chip is reduced. The following two examples are specifically described below:
referring to fig. 1a to fig. 1c, taking manufacturing a floating gate as an example, the substrate 111 includes a pattern-dense region a111 and a pattern-sparse region a112, shallow trench isolation structures 114 densely arranged are formed on the pattern-dense region a111, and shallow trench isolation structures 114 sparsely arranged are formed on the pattern-sparse region a 112; as shown in fig. 1a, after depositing a floating gate material layer 113 covering shallow trench isolation structures 114 on an oxide layer 112 on the top surface of a substrate 111, a first recess 115 is formed in the floating gate material layer 113 between two adjacent shallow trench isolation structures 114 of a pattern sparse region a112, and the depth of the first recess 115 is far beyond the specification; as shown in fig. 1b, the floating gate material layer 113 above the bottom surface of the first recess 115 is removed by photolithography and etching processes, so that the top surfaces of the floating gate material layer 113 on the pattern-dense region a111 and the pattern-sparse region a112 are flush; as shown in fig. 1c, the floating gate material layer 113 is continuously polished by a chemical mechanical polishing process, in order to completely polish and remove the floating gate material layer 113 on the top surface of the shallow trench isolation structure 114, a part of the thickness of the shallow trench isolation structure 114 is polished and removed, and since the polishing rate of the silicon oxide of the shallow trench isolation structure 114 is slower than that of the polysilicon of the floating gate material layer 113, a second recess 116 with a depth exceeding the specification is formed in the floating gate material layer 113 on the pattern sparse region a 112. Therefore, in the example shown in fig. 1a to 1c, the chemical mechanical polishing process is used to form the recess with the depth exceeding the specification, which affects the flatness of the whole device surface; in addition, in order to reduce the load during the chemical mechanical polishing process, a photolithography and etching process is added, which results in increased cost.
Referring to fig. 2a to 2c, the substrate 121 includes a pattern dense region a121 and a pattern sparse region a122, the substrate 121 is covered with a first insulating layer 122, an MIM capacitor is formed on the first insulating layer 122 on the top surface of the pattern dense region a121, and the MIM capacitor includes a lower metal layer 1231, a second insulating layer 1232, and an upper metal layer 1233 from bottom to top; as shown in fig. 2b, a third insulating layer 124 covering the MIM capacitor is formed on the first insulating layer 122, so that a first recess 1241 having a depth far beyond specification is formed in the third insulating layer 124 on the pattern thinning-out region a122 due to the MIM capacitor; as shown in fig. 2c, the third insulating layer 124 is polished by a chemical mechanical polishing process, because the third insulating layer 124 on the pattern-dense region a121 is significantly higher than the third insulating layer 124 on the pattern-sparse region a122, the polishing load is large, and when the third insulating layer 124 at the first recess 1241 is polished to the required thickness h1, the third insulating layer 124 on the pattern-dense region a121 still does not reach the required thickness h1, and a second recess 1242 with a depth exceeding the specification is still formed in the third insulating layer 124 on the pattern-sparse region a122, which affects the flatness of the entire device surface.
Therefore, how to improve the flatness of the surface of the pattern with different densities after the chemical mechanical polishing process is a problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can improve the flatness of the surface of a pattern with different densities after a chemical mechanical polishing process so as to improve the performance of the semiconductor device.
To achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first graph area and a second graph area, a film layer structure covers the substrate, a recess is formed in the film layer structure on the second graph area, and the depth of the recess exceeds a preset specification;
forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film layer structure outside the recess; and the number of the first and second groups,
and grinding the film layer structure outside the recess and the barrier layer on the surface of the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the film layer structure is greater than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
Optionally, the step of forming the barrier layer to cover the recess comprises:
forming a barrier layer covering the film layer structure on the first pattern area and the second pattern area;
and grinding by adopting a chemical mechanical grinding process to remove the barrier layer on the film structure outside the recess, and reserving the barrier layer on the film structure at the recess.
Optionally, device structures are formed in the film layer structures on the first pattern area and the second pattern area, and the arrangement density of the device structures on the first pattern area is greater than that of the device structures on the second pattern area; the recess is located between two adjacent device structures on the second pattern region, and the bottom wall of the recess is higher than the top surface of the device structure.
Optionally, the device structure comprises a shallow trench isolation structure extending from the film layer structure into the substrate; the film structure comprises a grid material layer for manufacturing a floating grid or a control grid.
Optionally, after forming the barrier layer to cover the recess and before polishing the film layer structure outside the recess and the barrier layer on the surface of the recess by using a chemical mechanical polishing process, the method for manufacturing a semiconductor device further includes:
and etching to remove the film layer structure with partial thickness except the recess, wherein the top surface of the film layer structure except the recess after etching is not lower than the top surface of the barrier layer on the bottom wall of the recess.
Optionally, the step of polishing the film structure outside the recess and the barrier layer on the surface of the recess by using a chemical mechanical polishing process includes:
removing the barrier layer on the surface of the recess and the film layer structure which is higher than the top surface of the device structure and has at least partial thickness except the recess by adopting a chemical mechanical polishing process in a polishing way, so that the top surface of the film layer structure except the recess after polishing is lower than the top surface of the film layer structure at the recess;
and grinding the depression and the film layer structure which is higher than the top surface of the device structure and part of the thickness of the device structure outside the depression by adopting a chemical mechanical grinding process, wherein the grinding speed of the device structure is lower than that of the film layer structure, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
Optionally, a device structure is formed in the film layer structure on the first pattern region; or device structures are formed in the film layer structures on the first graphic area and the second graphic area, and the height of the device structure on the first graphic area is higher than that of the device structure on the second graphic area; the bottom wall of the recess is higher than the top surface of the device structure.
Optionally, the device structure comprises a MIM capacitor or a gate structure, and the film structure comprises an insulating dielectric layer.
Optionally, after forming the barrier layer to cover the film layer structures on the first pattern region and the second pattern region and before removing the barrier layer on the film layer structure outside the recess by using a chemical mechanical polishing process, the method for manufacturing a semiconductor device further includes:
forming a sacrificial layer covering the barrier layer on the first pattern area and the second pattern area, wherein the top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure at the recess;
and grinding the sacrificial layer by adopting a chemical mechanical grinding process until the barrier layer on the film layer structure outside the recess is exposed, wherein the top surface of the exposed barrier layer on the film layer structure outside the recess is flush with the top surface of the residual sacrificial layer on the film layer structure at the recess.
Optionally, the step of removing the barrier layer on the film structure outside the recess by using a chemical mechanical polishing process includes:
and grinding and removing the barrier layer on the film structure outside the recess and the residual sacrificial layer on the film structure at the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the sacrificial layer is greater than that of the barrier layer.
Optionally, the predetermined specification is 100 angstroms.
Compared with the prior art, the manufacturing method of the semiconductor device has the advantages that for the substrate comprising the first pattern area and the second pattern area, and a recess with a depth exceeding a preset specification is formed in the film layer structure on the second pattern area, covering the recess by forming a barrier layer having a top surface lower than a top surface of the film layer structure outside the recess, and adopting a chemical mechanical polishing process to polish the film layer structure outside the recess and the barrier layer on the surface of the recess, and the grinding rate of the film layer structure is greater than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification, the smoothness of the graph surfaces with different densities after a chemical mechanical grinding process is improved, and the performance of a semiconductor device is further improved.
Drawings
FIGS. 1a to 1c are schematic views illustrating a device manufactured by a chemical mechanical polishing process;
FIGS. 2 a-2 c are schematic views of another device fabricated by a chemical mechanical polishing process;
fig. 3 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 4a to 4g are device diagrams of a first embodiment in the method of manufacturing the semiconductor device shown in FIG. 3;
fig. 5a to 5e are device diagrams of a second embodiment in the method of manufacturing the semiconductor device shown in fig. 3.
Wherein the reference numerals of figures 1a to 5e are as follows:
111-a substrate; 112-an oxide layer; 113-a layer of floating gate material; 114-shallow trench isolation structures; 115-a first recess; 116-a second recess; 121-a substrate; 122 — a first insulating layer; 1231 — lower metal layer; 1232 — a second insulating layer; 1233 — upper metal layer; 124-third insulating layer; 1241-first recess; 1242-second recess; 21-a substrate; 211-a gate dielectric layer; 22-a layer of gate material; 221-recess; 23-shallow trench isolation structures; 24-a barrier layer; 31-a substrate; 32-a first insulating dielectric layer; 321-a metal interconnect structure; 331-lower metal layer; 332 — a first layer of insulating material; 333-upper metal layer; 334-a second layer of insulating material; 34-a second insulating dielectric layer; 341-concave; 35-a barrier layer; 36-sacrificial layer.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
step S1, providing a substrate, including a first pattern area and a second pattern area, wherein the substrate is covered with a film layer structure, and a recess is formed in the film layer structure on the second pattern area, and the depth of the recess exceeds a preset specification;
step S2, forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film layer structure outside the recess;
step S3, polishing the film structure outside the recess and the barrier layer on the surface of the recess by a chemical mechanical polishing process, wherein the polishing rate of the film structure is greater than the polishing rate of the barrier layer, so that the height difference between the surfaces of the film structure on the first pattern area and the second pattern area after polishing is within a preset specification.
The method for manufacturing the semiconductor device according to the present embodiment will be described in more detail with reference to fig. 4a to 4g and fig. 5a to 5e, and fig. 4a to 4g and fig. 5a to 5e are schematic longitudinal cross-sectional views of the semiconductor device.
According to step S1, a substrate is provided, which includes a first pattern area and a second pattern area, the substrate is covered with a film structure, and a recess is formed in the film structure on the second pattern area, and the depth of the recess exceeds a predetermined specification. The preset specification can be defined according to the type, performance requirement and the like of the manufactured semiconductor device, and the preset specification refers to the depth requirement acceptable in the manufacturing process of the semiconductor device. The predetermined specification may be 100 angstroms.
In an embodiment of the present invention, device structures are formed in the film layer structures on the substrates of the first pattern area and the second pattern area, and an arrangement density of the device structures on the substrate of the first pattern area is greater than an arrangement density of the device structures on the substrate of the second pattern area, that is, a distance between two adjacent device structures on the substrate of the first pattern area is smaller than a distance between two adjacent device structures on the substrate of the second pattern area.
When the film layer structure is deposited on the substrate, the arrangement density of the device structures on the substrate in the first pattern area is greater than that of the device structures on the substrate in the second pattern area, so that a space between two adjacent device structures on the substrate in the first pattern area is filled up and a recess cannot be generated, a recess is formed in the film layer structure between two adjacent device structures on the substrate in the second pattern area, and the bottom wall of the recess is higher than the top surface of the device structure. The smaller the arrangement density of the device structures on the substrate in the second pattern region (i.e. the larger the distance between two adjacent device structures), the larger the depth of the recess.
Referring to fig. 4a, the substrate 21 includes a first pattern region a21 and a second pattern region a22, the device structure is a shallow trench isolation structure 23, the film structure is a gate material layer 22 for manufacturing a floating gate or a control gate, the gate material layer 22 covers the shallow trench isolation structure 23, a gate dielectric layer 211 is further formed between the gate material layer 22 and the substrate 21, the shallow trench isolation structures 23 extend from the gate material layer 22 through the gate dielectric layer 211 into the substrate 21, the arrangement density of the shallow trench isolation structures 23 on the first pattern area a21 is greater than the arrangement density of the shallow trench isolation structures 23 on the second pattern area a22, so that a recess 221 is formed in the gate material layer 22 between two adjacent shallow trench isolation structures 23 on the second pattern region a22, and a bottom wall of the recess 221 is higher than a top surface of the shallow trench isolation structure 23. The depth of the recess 221 exceeds a predetermined specification, so that the height difference between the surfaces of the gate material layers 22 on the substrate 21 in the first pattern area a21 and the second pattern area a22 exceeds the predetermined specification, resulting in a decrease in the surface flatness of the device. The depth of the recess 221 is, for example, 600 to 800 angstroms.
Or, in another embodiment of the present invention, a device structure is formed in the film layer structure on the substrate in the first pattern region, a device structure is not formed in the film layer structure on the substrate in the second pattern region, and a recess with a depth exceeding a preset specification is formed in the film layer structure in the second pattern region due to the height of the device structure; or device structures are formed in the film layer structures on the substrate of the first pattern area and the second pattern area, the height of the device structure on the substrate of the first pattern area is obviously higher than that of the device structure on the substrate of the second pattern area, and the difference between the heights of the device structure and the device structure enables a recess with the depth exceeding the preset specification to be formed in the film layer structure on the second pattern area. And the bottom wall of the recess is higher than the top surface of the device structure. After depositing and covering the film layer structure on the substrate until the film layer structure on the substrate of the second pattern area reaches the height required by the device, if only the device structure is formed in the film layer structure on the substrate of the first pattern area, the higher the device structure in the film layer structure on the substrate of the first pattern area is, the greater the depth of the recess in the film layer structure on the substrate of the second pattern area is; if device structures are formed in the film layer structures on the substrate of the first pattern area and the second pattern area, the larger the height difference between the device structure on the substrate of the first pattern area and the device structure on the substrate of the second pattern area is, the larger the depth of the recess in the film layer structure on the substrate of the second pattern area is.
The device structure can be an MIM capacitor or a grid structure, and the film layer structure can be an insulating dielectric layer.
Taking a film layer structure on the substrate in the first pattern region as an example, a device structure is formed in the film layer structure on the substrate in the second pattern region, and the device structure is an MIM capacitor, referring to fig. 5a, the substrate 31 includes a first pattern region a31 and a second pattern region a32, the substrate 31 is sequentially covered with a first insulating dielectric layer 32 and a second insulating dielectric layer 34, the first insulating dielectric layer 32 of the first pattern region a31 is formed with an MIM capacitor, the first insulating dielectric layer 32 of the second pattern region a32 is not formed with an MIM capacitor, and the second insulating dielectric layer 34 buries the MIM capacitor; after depositing a second insulating dielectric layer 34 over the first insulating dielectric layer 32, if the height h2 of the second insulating dielectric layer 34 on the second pattern area a32 reaches the device requirement, the top surface of the second insulating dielectric layer 34 on the first pattern area a31 is higher than the top surface of the second insulating dielectric layer 34 on the second pattern area a32 in the first pattern area a31 due to the presence of the MIM capacitor, that is, a recess 341 is formed in the second insulating dielectric layer 34 on the second pattern area a32, and the bottom wall of the recess 341 is higher than the top surface of the MIM capacitor. The depth of the recess 341 exceeds a predetermined specification, so that the height difference between the surfaces of the second insulating medium layer 34 on the substrate 31 in the first pattern area a31 and the second pattern area a32 exceeds the predetermined specification, resulting in a decrease in the surface flatness of the device.
The MIM capacitor includes a lower metal layer 331, a first insulating material layer 332, and an upper metal layer 333 from bottom to top, a metal interconnect structure 321 is formed in the first insulating dielectric layer 32, and the lower metal layer 331 is electrically connected to the metal interconnect structure 321. The area of the lower metal layer 331 in the MIM capacitor may be larger than the areas of the first insulating material layer 332 and the upper metal layer 333, a second insulating material layer 334 may be covered on the top surface of the lower metal layer 331 not covered by the first insulating material layer 332, the side surfaces of the first insulating material layer 332, and the side surfaces and the top surface of the upper metal layer 333, and the second insulating dielectric layer 34 buries the second insulating material layer 334.
Or, in other embodiments of the present invention, device structures are formed in the film layer structures on the substrates of the first pattern area and the second pattern area, an arrangement density of the device structures on the substrate of the first pattern area is greater than an arrangement density of the device structures on the substrate of the second pattern area, and a height of the device structures on the substrate of the first pattern area is greater than that of the device structures on the substrate of the second pattern area, so that a recess formed in the film layer structure on the substrate of the second pattern area further exceeds a preset specification.
It should be noted that the device structure and the film layer structure are not limited to the types of the above embodiments, and the device structure and the film layer structure may be selected as appropriate according to the type of the semiconductor device to be manufactured.
A barrier layer is formed overlying the recess, the barrier layer having a top surface lower than a top surface of the film layer structure outside the recess, as per step S2. The bottom surface of the barrier layer is higher than the top surface of the device structure, that is, the top surface of the film layer structure on the substrate of the first pattern area and the second pattern area is higher than the top surface of the device structure.
The step of forming the barrier layer to cover the recess comprises: firstly, forming a barrier layer to cover the film layer structures on the substrate of the first graph area and the second graph area, wherein the top surface of the barrier layer on the film layer structure outside the recess is higher than that of the barrier layer on the film layer structure at the recess; and then, removing the barrier layer on the film structure except the recess by adopting a chemical mechanical polishing process, and reserving the barrier layer on the film structure at the recess. Wherein the top surface of the barrier layer on the bottom wall of the recess is lower than the top surface of the film layer structure outside the recess, and the top surface of the barrier layer on the sidewall of the recess may be flush with or slightly lower than the top surface of the film layer structure outside the recess.
In an embodiment of the present invention, if the arrangement density of the device structures on the substrate in the first pattern region is greater than the arrangement density of the device structures on the substrate in the second pattern region, and the recess is formed in the film layer structure between two adjacent device structures on the substrate in the second pattern region, the area occupied by the recess is small, so that when the chemical mechanical polishing process is used to polish and remove the barrier layer on the film layer structure outside the recess, the barrier layer on the film layer structure in the recess is not polished, and the barrier layer on the film layer structure in the recess can be retained.
Referring to fig. 4 b-4 c, the step of forming the barrier layer 24 to cover the recess includes: first, as shown in fig. 4b, a barrier layer 24 is formed to cover the gate material layer 22 on the first pattern region a21 and the second pattern region a22, wherein the barrier layer 24 also covers the recess 221; then, as shown in fig. 4c, a chemical mechanical polishing process is used to polish and remove the barrier layer 24 on the gate material layer 22 outside the recess 221, and the barrier layer 24 on the gate material layer 22 at the recess 221 is remained. During the polishing process, the barrier layer 24 on the top of the sidewall of the recess 221 is also polished and removed, so that the top surface of the barrier layer 24 on the sidewall of the recess 221 may be flush with the top surface of the gate material layer 22 outside the recess 221 or slightly lower than the top surface of the gate material layer 22 outside the recess 221.
In another embodiment of the present invention, if only a device structure is formed in the film layer structure on the substrate in the first pattern region, or the height of the device structure on the substrate in the first pattern region is higher than the height of the device structure on the substrate in the second pattern region, after forming the barrier layer to cover the film layer structures on the substrates in the first pattern region and the second pattern region and before removing the barrier layer on the film layer structure outside the recess by using a chemical mechanical polishing process, the method for manufacturing a semiconductor device further includes: forming a sacrificial layer covering the barrier layer on the first pattern area and the second pattern area, wherein the top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure at the recess due to the existence of the recess; and grinding the sacrificial layer by adopting a chemical mechanical grinding process until the barrier layer on the film layer structure outside the recess is exposed, wherein the top surface of the exposed barrier layer on the film layer structure outside the recess is flush with the top surface of the residual sacrificial layer on the film layer structure at the recess. The top surface of the sacrificial layer on the film structure outside the recess is higher than the top surface of the sacrificial layer on the film structure at the recess, so that during grinding, the grinding rate of the sacrificial layer on the film structure outside the recess is higher than that of the sacrificial layer on the film structure at the recess, and further, when the sacrificial layer ground on the film structure outside the recess is completely removed, the sacrificial layer with partial thickness still remains on the film structure at the recess.
And the step of removing the barrier layer on the film layer structure except the recess by adopting a chemical mechanical polishing process comprises the following steps: and grinding and removing the barrier layer on the film layer structure outside the recess and the residual sacrificial layer on the film layer structure at the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the sacrificial layer is greater than that of the barrier layer, so that the barrier layer on the film layer structure outside the recess is ground and removed to expose the film layer structure, and meanwhile, the residual sacrificial layer on the film layer structure at the recess is ground and removed to expose the barrier layer. In this embodiment, since the area occupied by the device structure on the substrate in the first pattern region is small, and the recess is formed due to the height of the device structure on the substrate in the first pattern region or the height difference between the device structures on the substrates in the first pattern region and the second pattern region, so that the recess is at least located in the entire film structure on the second pattern region, and the area occupied by the recess is large, if a sacrificial layer is not formed on the film structure in the recess, when the chemical mechanical polishing process is used to polish and remove the barrier layer on the film structure other than the recess, the barrier layer on the film structure in the recess is also in contact with the polishing pad and is polished and removed; therefore, when the barrier layer on the film layer structure outside the recess is removed by grinding, the residual sacrificial layer is covered on the film layer structure at the recess, so that the barrier layer on the film layer structure at the recess can be protected from being removed by grinding. Referring to fig. 5b to 5d, the step of forming the barrier layer to cover the recess includes: firstly, as shown in fig. 5b, forming a barrier layer 35 to cover the second insulating dielectric layer 34 on the first pattern area a31 and the second pattern area a32, wherein the barrier layer 35 also covers the recess 341, and the top surface of the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341 is higher than the top surface of the barrier layer 35 on the second insulating dielectric layer 34 at the recess 341; then, as shown in fig. 5b, forming a sacrificial layer 36 overlying the barrier layer 35 on the first pattern region a31 and the second pattern region a32, wherein the top surface of the sacrificial layer 36 on the second insulating dielectric layer 34 outside the recess 341 is higher than the top surface of the sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341; then, as shown in fig. 5c, the sacrificial layer 36 is polished by a chemical mechanical polishing process until the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341 is exposed, and the top surface of the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341 exposed is flush with the top surface of the remaining sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341; next, as shown in fig. 5d, a chemical mechanical polishing process is used to polish and remove the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341 until the lower second insulating dielectric layer 34 is exposed, and simultaneously polish and remove the remaining sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341 until the lower barrier layer 35 is exposed, where the remaining sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341 can protect the lower barrier layer 35 from being polished and removed. Since the thickness of the sacrificial layer 36 remaining on the second insulating medium layer 34 at the recess 341 is greater than the thickness of the barrier layer 35 on the second insulating medium layer 34 outside the recess 341, the polishing rate for the sacrificial layer 36 is greater than that for the barrier layer 35.
According to step S3, a chemical mechanical polishing process is used to polish the film structure outside the recess and the barrier layer on the surface of the recess, and the polishing rate of the film structure is greater than the polishing rate of the barrier layer, so that the height difference between the surfaces of the film structure on the first pattern area and the second pattern area after polishing is within a predetermined specification. Then, the height difference of the surface of the film layer structure on the first pattern area and the second pattern area after grinding is 0; or, after grinding, the film layer structure on the first pattern area and/or the second pattern area may form a recess, and the depth of the recess is within a preset specification.
In an embodiment of the present invention, if the arrangement density of the device structures on the first pattern region is greater than the arrangement density of the device structures on the second pattern region, the method for manufacturing a semiconductor device further includes, after forming the barrier layer to cover the recess and before polishing the film structure outside the recess and the barrier layer on the surface of the recess by using a chemical mechanical polishing process: etching to remove the film structure with partial thickness outside the recess, wherein the top surface of the film structure outside the recess after etching is not lower than the top surface of the barrier layer on the bottom wall of the recess; and after etching, the barrier layer on the side wall of the recess can be reserved. The etching selection ratio of the film layer structure to the barrier layer is high, so that the barrier layer on the film layer structure at the concave position can be used as a hard mask, and when the film layer structure outside the concave position is etched, the barrier layer on the film layer structure at the concave position is hardly etched, and the film layer structure at the concave position is prevented from being etched; and, the photoetching process is not required to be executed before the etching, so that the photomask is saved.
Before the subsequent chemical mechanical polishing process is adopted for polishing, the etching process is firstly adopted to remove the film structure with the partial thickness except the recess so as to reduce the height difference between the top surface of the film structure except the recess and the top surface of the barrier layer on the film structure at the recess, so that the load when the chemical mechanical polishing process is subsequently carried out can be reduced. Referring to fig. 4d, the gate material layer 22 is etched to remove a portion of the thickness outside the recess 221, and the top surface of the gate material layer 22 outside the recess 221 after etching is higher than the top surface of the barrier layer 24 on the bottom wall of the recess 221; the etch selectivity of the gate material layer 22 to the barrier layer 24 is so high that the barrier layer 24 on the inner surface of the recess 221 is hardly etched when the gate material layer 22 is etched.
And the step of polishing the film structure outside the recess and the barrier layer on the surface of the recess by using a chemical mechanical polishing process comprises: removing the barrier layer on the surface of the recess and the film layer structure which is higher than the top surface of the device structure and has at least partial thickness except the recess by adopting a chemical mechanical polishing process in a polishing way, so that the top surface of the film layer structure except the recess after polishing is lower than the top surface of the film layer structure at the recess; and adopting a chemical mechanical polishing process to polish the depression and the film layer structure which is higher than the top surface of the device structure and partial thickness of the device structure except the depression, wherein the polishing rate of the device structure is less than that of the film layer structure. When the device structure with partial thickness is ground and removed in order to completely remove the film layer structure on the top surface of the device structure, although the grinding rate of the device structure is lower than that of the film layer structure, after the barrier layer on the surface of the recess is removed, the top surface of the film layer structure at the recess is obviously higher than the top surface of the film layer structure outside the recess, so that when the device structure is ground and removed with partial thickness, the part of the film layer structure at the recess, which is higher than the top surface of the film layer structure, is just ground, and the height difference of the film layer structure surfaces on the first pattern area and the second pattern area after grinding is within the preset specification.
Referring to fig. 4e to 4g, the step of polishing the film structure outside the recess 221 and the barrier layer 24 on the surface of the recess 221 by using a chemical mechanical polishing process includes: firstly, as shown in fig. 4e, a chemical mechanical polishing process is used to polish the barrier layer 24 on the surface of the recess 221 and the gate material layer 22 outside the recess 221 and above the top surface of the shallow trench isolation structure 23, and since the polishing rate of the barrier layer 24 is lower than that of the gate material layer 22, when the barrier layer 24 is polished to remove a portion of the thickness, the top surface of the gate material layer 22 is lower than that of the barrier layer 24; as shown in fig. 4f, when the polishing is continued until the barrier layer 24 is completely removed, the height of the gate material layer 22 higher than the top surface of the shallow trench isolation structure 23 outside the recess 221 is further lower than the height of the gate material layer 22 higher than the top surface of the shallow trench isolation structure 23 at the recess 221; then, as shown in fig. 4g, a chemical mechanical polishing process is used to polish the gate material layer 22 and a portion of the thickness of the shallow trench isolation structure 23 outside the recess 221 and at the recess 221, which is higher than the top surface of the shallow trench isolation structure 23, and the polishing rate for the shallow trench isolation structure 23 is lower than that for the gate material layer 22, so that the height difference between the surfaces of the gate material layer 22 in the first pattern area a21 and the second pattern area a22 after polishing is within a predetermined specification.
In the embodiment shown in fig. 4a to 4g, the material of the gate material layer 22 is, for example, polysilicon, the material of the barrier layer 24 is, for example, at least one of silicon oxide, silicon nitride and silicon oxynitride, and the material of the shallow trench isolation structure 23 is, for example, at least one of silicon oxide, silicon nitride and silicon oxynitride.
In another embodiment of the present invention, if only the device structure is formed in the film layer structure on the substrate in the first pattern region, or the height of the device structure on the substrate of the first pattern area is higher than that of the device structure on the substrate of the second pattern area, in this step, the exposed film structure outside the recess and the exposed barrier layer at the recess are polished by a chemical mechanical polishing process, since the top surface of the film structure exposed in the region outside the recess is higher than the top surface of the barrier layer exposed in the recess, and the polishing rate of the film layer structure is greater than that of the barrier layer, so that the barrier layer at the concave part is removed at the same time as the raised part of the film layer structure outside the concave part is just removed, and further enabling the height difference of the surfaces of the film layer structures on the first graph area and the second graph area after grinding to be within a preset specification.
Referring to fig. 5e, the second insulating dielectric layer 34 exposed in the region outside the recess 341 and the barrier layer 35 exposed in the recess 341 are polished by a chemical mechanical polishing process, so that the height h2 required by the device can be achieved for both the second insulating dielectric layer 34 in the region outside the recess 341 and the second insulating dielectric layer 34 in the recess 341 after polishing, and further, the height difference between the surfaces of the second insulating dielectric layers 34 in the first pattern region a31 and the second pattern region a32 is within a preset specification.
In the embodiments shown in fig. 5a to 5e, the second insulating dielectric layer 34 is made of, for example, silicon oxide, the barrier layer 35 is made of, for example, at least one of silicon nitride, silicon carbide, and nitrogen-doped silicon carbide, and the sacrificial layer 36 is made of, for example, silicon oxide or polysilicon.
In summary, for a substrate including a first pattern area and a second pattern area, a recess with a depth exceeding a preset specification is formed in a film layer structure on the second pattern area, the recess is covered by forming a barrier layer, the top surface of the barrier layer is lower than the top surface of the film layer structure outside the recess, and a chemical mechanical polishing process is used to polish the film layer structure outside the recess and the barrier layer on the surface of the recess, and the polishing rate of the film layer structure is higher than that of the barrier layer, so that the height difference between the surfaces of the film layer structures on the first pattern area and the second pattern area after polishing is within the preset specification, the flatness of different density pattern surfaces after the chemical mechanical polishing process is improved, and the performance of a semiconductor device is further improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first graph area and a second graph area, a film layer structure covers the substrate, a recess is formed in the film layer structure on the second graph area, and the depth of the recess exceeds a preset specification;
forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film layer structure outside the recess; and the number of the first and second groups,
and grinding the film layer structure outside the recess and the barrier layer on the surface of the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the film layer structure is greater than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the barrier layer so as to cover the recess includes:
forming a barrier layer covering the film layer structure on the first pattern area and the second pattern area;
and grinding by adopting a chemical mechanical grinding process to remove the barrier layer on the film structure outside the recess, and reserving the barrier layer on the film structure at the recess.
3. The method for manufacturing a semiconductor device according to claim 1, wherein device structures are formed in the film layer structures on the first pattern region and the second pattern region, and wherein a density of arrangement of the device structures on the first pattern region is greater than a density of arrangement of the device structures on the second pattern region; the recess is located between two adjacent device structures on the second pattern region, and the bottom wall of the recess is higher than the top surface of the device structure.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the device structure comprises a shallow trench isolation structure extending from the film layer structure into the substrate; the film structure comprises a grid material layer for manufacturing a floating grid or a control grid.
5. The method for manufacturing a semiconductor device according to claim 3, wherein after forming the barrier layer to cover the recess and before polishing the barrier layer on the surface of the recess and the film layer structure outside the recess by a chemical mechanical polishing process, the method for manufacturing a semiconductor device further comprises:
and etching to remove the film layer structure with partial thickness except the recess, wherein the top surface of the film layer structure except the recess after etching is not lower than the top surface of the barrier layer on the bottom wall of the recess.
6. The method for manufacturing a semiconductor device according to claim 3, wherein the step of polishing the film structure outside the recess and the barrier layer on the surface of the recess by using a chemical mechanical polishing process comprises:
removing the barrier layer on the surface of the recess and the film layer structure which is higher than the top surface of the device structure and has at least partial thickness except the recess by adopting a chemical mechanical polishing process in a polishing way, so that the top surface of the film layer structure except the recess after polishing is lower than the top surface of the film layer structure at the recess;
and grinding the depression and the film layer structure which is higher than the top surface of the device structure and part of the thickness of the device structure outside the depression by adopting a chemical mechanical grinding process, wherein the grinding speed of the device structure is lower than that of the film layer structure, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
7. The method for manufacturing a semiconductor device according to claim 2, wherein a device structure is formed in the film layer structure on the first pattern region; or device structures are formed in the film layer structures on the first graphic area and the second graphic area, and the height of the device structure on the first graphic area is higher than that of the device structure on the second graphic area; the bottom wall of the recess is higher than the top surface of the device structure.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the device structure comprises a MIM capacitor or gate structure, and the film structure comprises an insulating dielectric layer.
9. The method of manufacturing a semiconductor device according to claim 7, wherein after forming the barrier layer over the film structure on the first pattern region and the second pattern region and before removing the barrier layer over the film structure outside the recess by using a chemical mechanical polishing process, the method further comprises:
forming a sacrificial layer covering the barrier layer on the first pattern area and the second pattern area, wherein the top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure at the recess;
and grinding the sacrificial layer by adopting a chemical mechanical grinding process until the barrier layer on the film layer structure outside the recess is exposed, wherein the top surface of the exposed barrier layer on the film layer structure outside the recess is flush with the top surface of the residual sacrificial layer on the film layer structure at the recess.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of removing the barrier layer on the film structure outside the recess by using a chemical mechanical polishing process comprises:
and grinding and removing the barrier layer on the film structure outside the recess and the residual sacrificial layer on the film structure at the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the sacrificial layer is greater than that of the barrier layer.
11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the predetermined specification is 100 angstroms.
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| WO2014026549A1 (en) * | 2012-08-13 | 2014-02-20 | 无锡华润上华科技有限公司 | Chemical mechanical polishing method for shallow trench isolation structure |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |