CN110620113A - Semiconductor memory structure and manufacturing method of bit line contact part thereof - Google Patents
Semiconductor memory structure and manufacturing method of bit line contact part thereof Download PDFInfo
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- CN110620113A CN110620113A CN201810637317.4A CN201810637317A CN110620113A CN 110620113 A CN110620113 A CN 110620113A CN 201810637317 A CN201810637317 A CN 201810637317A CN 110620113 A CN110620113 A CN 110620113A
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- bit line
- contact
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- line contact
- isolation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 72
- 238000002955 isolation Methods 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims description 63
- 125000006850 spacer group Chemical group 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910052582 BN Inorganic materials 0.000 claims description 7
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 70
- 238000000151 deposition Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
The invention provides a semiconductor memory structure and a manufacturing method of a bit line contact part thereof, wherein the manufacturing method comprises the step of manufacturing the bit line contact isolation part before the deposition of a bit line contact material, so that the bit line contact part is isolated by the bit line contact isolation part in the deposition stage, and even if the etching is incomplete in the subsequent etching process, the short circuit of the bit line can not be caused. The invention can avoid the situation that the short circuit of the bit line is caused because the contact material is not completely etched, increase the process window of the subsequent bit line etching, and simultaneously prevent the resistance value of the bit line contact from being increased because the contact material is over-etched.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and relates to a semiconductor memory structure and a manufacturing method of a bit line contact part thereof.
Background
In the semiconductor memory structure, a bit line contact portion is provided below a bit line. The existing bit line contact manufacturing method comprises the following steps:
the method comprises the following steps: as shown in fig. 1 and 2, a hard mask layer 103 is formed on a silicon nitride layer 102 on a surface of a substrate 101, a photoresist layer 104 is formed on the hard mask layer, and the photoresist layer is patterned, wherein a plurality of isolation structures 105 are formed in the substrate, fig. 1 shows a top view showing a planar layout of a word line 111, fig. 2 shows a cross-sectional view of a-a' of the structure shown in fig. 1, and then, as shown in fig. 3, a pattern is transferred into the hard mask layer and the silicon nitride layer by etching to form a trench 106.
Step two: implanting ions in the trench reduces contact resistance.
Step three: as shown in fig. 4 and 5, the trench 106 is filled with a contact material 107 and etched to the surface of the silicon nitride layer 102, wherein fig. 4 is a top view, and fig. 5 is a cross-sectional view of the structure shown in fig. 4 along the direction B-B'.
Step four: as shown in fig. 6 and 7, during the etching process of the bit lines 108, the contact material 107 between the bit lines 108 is etched away, and the contact material under the bit lines 108 remains to form bit line contacts 109, wherein a protection layer 110 (not shown in fig. 6) is formed on the bit lines 108, which is shown in fig. 6 as a top view, and fig. 7 is a cross-sectional view of the structure shown in fig. 6 along the direction C-C'.
The existing manufacturing method has the following defects: the contact material between the bitlines is not completely etched in the subsequent etching process and bitline shorts may occur. The reason is that in the process of bit line contact, firstly, a complete line groove is etched, a bit line contact material is deposited, and finally, in the process of bit line etching, the contact material is separated to form a bit line contact, and if the bit line etching process is incomplete, the bit line can be short-circuited. Fig. 8 and 9 show schematic views of the contact material 107 between the bit lines 108 not completely etched, wherein fig. 8 is a top view and fig. 9 is a cross-sectional view of the structure shown in fig. 8 taken along the direction D-D'.
In the prior art, bit line contacts are separated during the etching process of a peripheral Gate (peripheral Gate), contact material below the bit lines is protected, contact material between two bit lines is etched, and if the contact material is not completely etched, the bit lines are short-circuited. On the other hand, if the contacts are separated by over-etching, the resistance of the bit line contacts may increase due to over-etching of the contact material.
Therefore, it is an important technical problem to be solved by those skilled in the art how to provide a semiconductor memory structure and a method for fabricating a bit line contact thereof to prevent bit line short circuit caused by incomplete etching of a contact material and to prevent bit line contact resistance from increasing due to over-etching of the contact material.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor memory structure and a method for manufacturing a bit line contact thereof, which are used to solve the problem in the prior art that a bit line is shorted due to the fact that a contact material is not completely etched, or the resistance of a bit line contact is increased due to the fact that the contact material is over-etched.
To achieve the above and other related objects, the present invention provides a method for fabricating a bit line contact, comprising:
s1: providing a substrate, wherein an etching stop layer is formed on the substrate;
s2: forming a plurality of discretely disposed contact vias in the etch stop layer to form a plurality of bit line contact spacers on the substrate between the word lines to space the contact vias;
s3: forming a contact material in the contact via, the contact material filling the contact via and covering the bit line contact isolation;
s4: removing excess contact material above the bit line contact spacers to form a plurality of initial contacts in the contact vias and spaced by the bit line contact spacer bottoms;
s5: and forming a plurality of bit lines, wherein the bottom surface of each bit line is respectively connected with the top surfaces of the initial contact parts, the top surfaces of the initial contact parts are not completely covered by the bit lines, the parts of the initial contact parts which are not covered by the bit lines are further removed, and the parts of the initial contact parts which are positioned below the bit lines are reserved as the bit line contact parts.
Optionally, forming the contact via comprises:
s2-1: forming a hard mask layer on the etching stop layer;
s2-2: forming a photoresist layer on the hard mask layer, and patterning the photoresist layer;
s2-3: etching the hard mask layer by taking the patterned photoresist layer as a mask so as to transfer the pattern of the photoresist layer to the hard mask layer and pattern the hard mask layer;
s2-4: and etching the etching stop layer by taking the patterned hard mask layer as a mask so as to obtain the contact through hole.
Optionally, a bit line protection layer over the bit line is formed simultaneously when the bit line is formed to protect the bit line during the process of removing the portion of the initial contact not covered by the bit line.
Optionally, in the step of providing the substrate, an isolation structure is further formed in the substrate, the isolation structure defines a plurality of active regions in the substrate, in the step of forming the contact via, the contact via is located above the active regions, a bottom of the contact via is exposed from the active regions, and the bit line contact isolation is located above the isolation structure.
Optionally, the contact via extends downward into the active region, so that the bottom of the contact via is lower than the lower surface of the etch stop layer.
Optionally, the contact via has a greater depth of recess from the upper substrate surface.
Optionally, the substrate includes a plurality of word line groups arranged in parallel, the word line group includes two word lines arranged in parallel, the contact via and the bit line contact isolation portion are both distributed between the two word lines of the word line group corresponding to the plurality of active regions arranged in the same direction.
Optionally, the word line is a linear type, the bit line is a wavy line type, and an extending direction of the bit line is perpendicular to an extending direction of the word line.
Optionally, the length of the contact via in the extending direction of the word line is between 10nm and 70 nm.
Optionally, before forming the contact material, performing ion implantation on the substrate at the bottom of the contact via to reduce the contact resistance of the material at the bottom of the contact via.
Optionally, the bit line contact spacer is made of one material selected from the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride.
The present invention also provides a semiconductor memory structure comprising:
a substrate;
a plurality of bit line contact isolation parts of an etching stop layer, which are separately arranged on the substrate to isolate a plurality of bit line contact regions in the substrate, wherein in an extending direction, the upper surface of the bit line contact region of the substrate and the top surface and the side surface of the bit line contact isolation part form a contact material forming surface with a height difference;
a plurality of bit line contacts of contact material disposed on the bit line contact regions, wherein the bit line contacts are separated from each other by the bit line contact spacers in the extending direction, and the bit line contacts and the bit line contact spacers are separately disposed;
and the bottom surface of each bit line is respectively connected with the top surfaces of the bit line contact parts.
Optionally, the bit line contact region is more recessed in the upper surface of the substrate.
Optionally, the bit line contact region has a more recessed depth of between 1nm and 5 nm.
Optionally, the thickness of the bit line contact isolation is between 20nm and 60 nm.
Optionally, a bit line protection layer is further formed on the bit line.
Optionally, an isolation structure is further formed in the substrate, the isolation structure defines a plurality of active regions in the substrate, the bit line contact is located on the active regions, and the bit line contact isolation is located on the isolation structure.
Optionally, a bottom surface of the bit line contact is lower than the bit line contact isolation bottom surface.
Optionally, the substrate includes a plurality of word line groups arranged in parallel, each word line group includes two word lines arranged in parallel, and the bit line contact portions and the bit line contact isolation portions are both distributed between the two word lines in the word line group, corresponding to the plurality of active regions arranged in the same direction.
Optionally, the word line is a linear type, the bit line is a wavy line type, and an extending direction of the bit line is perpendicular to an extending direction of the word line.
Optionally, the bit line contact spacer is made of one material selected from the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride.
As described above, the semiconductor memory structure and the method for manufacturing the bit line contact thereof according to the present invention have the following advantages: in the manufacturing method of the bit line contact part of the semiconductor memory structure, the bit line contact isolating part is firstly manufactured before the deposition of the bit line contact material, so that the bit line contact part is isolated by the bit line contact isolating part in the deposition stage, and even if the etching is incomplete in the subsequent etching process, the short circuit of the bit line can not be caused. The invention can avoid the situation that the short circuit of the bit line is caused because the contact material is not completely etched, increase the process window of the subsequent bit line etching, and simultaneously prevent the resistance value of the bit line contact from being increased because the contact material is over-etched.
Drawings
Fig. 1-7 are schematic structural diagrams showing steps of a bitline contact fabrication method in the prior art.
Fig. 8-9 are schematic views showing structures of the prior art in which the contact material between the bit lines is not completely etched.
Fig. 10 shows a structural cross-sectional view of a substrate provided for the method of fabricating a bit line contact according to the present invention.
Fig. 11 shows a top view of a structure formed by forming a hard mask layer on the etch stop layer, forming a photoresist layer on the hard mask layer, and patterning the photoresist layer according to the method for forming a bit line contact according to the present invention.
Figure 12a shows a cross-sectional view through E-E' of the structure shown in figure 11.
FIG. 12b is a cross-sectional view of the structure showing the hard mask layer after patterning the hard mask layer according to the method for forming the bit line contact.
Fig. 13 is a top view of the structure presented after forming a plurality of separately disposed contact vias in an etch stop layer for the bit line contact fabrication method of the present invention.
Fig. 14 is a sectional view taken along line F-F' of the structure shown in fig. 13.
FIG. 15 is a top view of the structure after contact material is formed in the contact via for the method of forming a bit line contact according to the present invention.
Fig. 16 is a sectional view taken along line G-G' of the structure shown in fig. 15.
FIG. 17 is a top view of the structure after the removal of the excess contact material over the bit line contact isolation according to the method of forming a bit line contact of the present invention.
Fig. 18 is a cross-sectional view taken in the direction H-H' of the structure shown in fig. 17.
FIG. 19 is a top view of the structure after forming a plurality of bit lines according to the method for forming bit line contacts of the present invention.
FIG. 20 is a top view of the structure of the bit line contact of the present invention after the initial contact is removed from the bit line.
FIG. 21 is a cross-sectional view taken along line I-I' of the structure shown in FIG. 20.
Description of the element reference numerals
101 substrate
102 silicon nitride layer
103 hard mask layer
104 photoresist layer
105 isolation structure
106 grooves
107 contact material
108 bit line
109 bit line contact
110 protective layer
111 word line
201 substrate
202 etch stop layer
203 isolation structure
204 contact via
205 bit line contact isolation
206 hard mask layer
207 photoresist layer
208 word line
209 contact material
210 initial contact part
211 bit line
212 bit line contact
213 bit line protection layer
214 active region
215 bit line contact region
I word line group
Extending direction of X bit line
Extending direction of Y word line
d depth of contact via
Length of w contact via in word line extension direction
t depth
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 10 to 21. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The invention provides a method for manufacturing a bit line contact part, which comprises the following steps:
as shown in fig. 10, step S1 is performed: a substrate 201 is provided having an etch stop layer 202 formed thereon.
Specifically, the substrate 201 may be made of a conventional semiconductor material such as Si, SiGe, SOI, and the like, and in this embodiment, the substrate 201 is a silicon substrate as an example.
Specifically, an isolation structure 203 is further formed in the substrate 201, and the isolation structure 203 defines a plurality of active regions 214 in the substrate 201. In this embodiment, the isolation structure 203 is a Shallow Trench Isolation (STI) structure. The active region may have different layouts according to the requirements of different semiconductor memory structures, and the scope of the present invention should not be limited too much herein.
Specifically, the etch stop layer 202 also has a function of protecting the substrate 201. As an example, the material of the etch stop layer 202 is selected from one of the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride, and in this embodiment, the material of the etch stop layer 202 is preferably silicon nitride.
As shown in fig. 13 and 14, step S2 is executed: a plurality of discretely disposed contact vias 204 are formed in the etch stop layer 202 to form a plurality of bit line contact spacers 205 on the substrate between the word lines to space the contact vias, wherein fig. 13 is shown in a top view and fig. 14 is shown in a cross-sectional view along direction F-F' of the structure shown in fig. 13.
Specifically, the contact via 204 is located above the active region 214, the bottom of the contact via 204 exposes the active region 214, and the bit line contact isolation 205 is located above the isolation structure 203.
Specifically, the contact via 204 is extended downward into the active region 214 by a certain degree of over-etching, so that the bottom of the contact via 204 is lower than the lower surface of the etch stop layer 202. The contact through hole has a more concave depth from the upper surface of the substrate, so that the height difference between the bottom of the bit line contact part and the top of the bit line contact isolation part can be increased, and the separation of the bit line contact part is facilitated. As an example, the depth d of the contact via ranges between 20nm and 60 nm.
As an example, the substrate 201 includes a plurality of word line groups I arranged in parallel, each of the word line groups I including two word lines 208 arranged in parallel. In this embodiment, the word line 208 is buried (embedded in the substrate) or may be conventional (formed on the substrate). It should be noted that, in order to show the relative position relationship between the word lines 208 and the contact vias 204, the boundaries of the word lines 208 are shown by dashed lines in fig. 13, but actually, since the word lines 208 are embedded, when various material layers are formed on the substrate 201, the material layers cover not only the regions between the word lines but also the regions above the word lines, the word lines are not visible in the top view, and the word lines are not re-exposed.
Specifically, the contact vias 204 and the bit line contact spacers 205 are distributed between two of the word lines 208 in the word line group I corresponding to a plurality of active regions arranged in the same direction. As an example, the word line 208 is linear, and the length w of the contact via 204 in the extending direction Y of the word line is between 10nm and 70 nm.
As an example, referring to fig. 11, 12a, 12b, 13 and 14, forming the contact via 204 comprises the steps of:
s2-1: forming a hard mask layer 206 on the etch stop layer 202;
s2-2: forming a photoresist layer 207 on the hard mask layer 206, and patterning the photoresist layer 207, wherein fig. 11 shows a top view of the structure after patterning the photoresist layer 207, fig. 12a shows a cross-sectional view of the structure shown in fig. 11 taken along the direction E-E', and the boundary of the word line 208 is shown in fig. 11 by a dotted line.
S2-3: etching the hard mask layer 206 by using the patterned photoresist layer 207 as a mask to transfer the pattern of the photoresist layer 207 to the hard mask layer 206, so as to pattern the hard mask layer 206, wherein the structure of the patterned hard mask layer 206 is shown in fig. 12 b;
s2-4: the patterned hard mask layer 206 is used as a mask to etch the etch stop layer 202 to obtain the contact via 204 (as shown in fig. 13 and 14).
As an example, the pattern of the photoresist layer 207 is transferred to the hard mask layer 206 by using a plasma dry etching, and then a trench is formed on the substrate, thereby obtaining a plurality of isolated contact through holes 204.
As shown in fig. 15 and 16, step S3 is executed: a contact material 209 is formed in the contact via 204, the contact material 209 filling the contact via 204 and covering the bit line contact isolation 205.
As an example, before forming the contact material 209, the substrate is ion implanted at the bottom of the contact via 204 to reduce the contact resistance of the material at the bottom of the contact via 204.
As an example, the contact material 209 is formed using a chemical vapor deposition method. The contact material 209 may be selected from, but is not limited to, a conductive material such as tungsten. The bit line contact spacer 205 is formed of a material selected from the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride in conformity with the etch stop layer 202.
As shown in fig. 17 and 18, step S4 is executed: excess contact material above the bit line contact spacers 205 is removed to form a plurality of initial contacts 210 in the contact vias and spaced by the bottom of the bit line contact spacers 205, wherein the boundaries of the word lines 208 are shown in dashed lines in fig. 17.
As an example, a plasma dry etching process is used to remove the excess contact material, resulting in a plurality of isolated initial contacts 210.
It should be noted that, in this step, it is not necessary to achieve the pre-separation of the bit line contacts, it is possible to cut off a part or half of the excess contact material above the bit line contact isolation portions, and separate the bit line contacts from the rest part or half of the excess contact material when forming a plurality of bit lines, and the bit line contact isolation portions are mainly used for spacing a plurality of initial contact portions at the bottom in the extending direction of the word lines, and may or may not be spaced for the top of the initial contact portions.
As shown in fig. 19, 20, and 21, step S5 is executed: forming a plurality of bit lines 211, wherein the bottom surface of each bit line 211 is respectively connected to the top surfaces of the plurality of initial contacts 210, and the top surfaces of the initial contacts 210 are not completely covered by the bit lines 211, further removing the portions of the initial contacts 205 that are not covered by the bit lines 211, and leaving the portions of the initial contacts 210 below the bit lines 211 as bit line contacts 212, wherein the boundaries of the word lines 208 are shown by dashed lines in fig. 19 and 20.
As an example, the bit lines 211 are wavy, and the extending direction X of the bit lines is perpendicular to the extending direction Y of the word lines. The wavy bit lines can make full use of space, and are favorable for increasing storage density. Of course, in other embodiments, the bit lines may be linear or other types, and the scope of the present invention should not be limited too much.
As an example, when the bit line 211 is formed, a bit line protection layer 213 positioned over the bit line 211 is simultaneously formed to protect the bit line 211 in a process of removing a portion of the initial contact 210 not covered by the bit line 211.
As an example, a plasma dry etch is used to etch the contact material between the bit lines, leaving the contact material under the bit lines.
Thus, the bit line contact of the semiconductor memory structure is completed. According to the manufacturing method of the bit line contact part, the bit line contact isolation part is manufactured before the deposition of the bit line contact material, so that the bit line contact part is isolated by the bit line contact isolation part in the deposition stage, and even if the etching is incomplete in the subsequent etching process, the short circuit of the bit line cannot be caused. The invention can avoid the situation that the short circuit of the bit line is caused because the contact material is not completely etched, increase the process window of the subsequent bit line etching, and simultaneously prevent the resistance value of the bit line contact from being increased because the contact material is over-etched.
Example two
As shown in fig. 20 and 21, the present invention further provides a semiconductor memory structure, wherein fig. 20 is a top view of the semiconductor memory structure, and fig. 21 is a cross-sectional view taken along the direction I-I' of the structure shown in fig. 20, and it can be seen that the semiconductor memory structure comprises a substrate 201, a plurality of bit line contact spacers 205 of an etch stop layer, a plurality of bit line contacts 212 of a contact material, and a plurality of bit lines 211.
Specifically, a plurality of the bit line contact spacers 205 are separately disposed on the substrate 201 to isolate a plurality of bit line contact regions 215 in the substrate, and in an extending direction, an upper surface of the bit line contact region of the substrate and a top surface and a side surface of the bit line contact spacer constitute a contact material forming surface having a height difference.
Specifically, the plurality of bit line contacts 212 are disposed on the bit line contact regions 215, and in the extending direction, the bit line contacts 212 are separated by the bit line contact spacers 205, and the bit line contacts 212 and the bit line contact spacers 205 are separately disposed.
Specifically, the bottom surface of each of the bit lines 211 is connected to the top surfaces of a plurality of the bit line contacts 212, respectively. In this embodiment, a bit line protection layer 213 is further formed on the bit line 211.
Specifically, the bit line contact regions 215 are recessed further into the top surface of the substrate. As an example, the deeper sinking depth of the bit line contact region 215 is t, in this embodiment, the depth t is between 1nm and 5nm, and the thickness of the bit line contact isolation is between 20nm and 60 nm.
Specifically, an isolation structure 203 is further formed in the substrate 201, and the isolation structure 203 defines a plurality of active regions 214 in the substrate 201. In this embodiment, the isolation structure 203 is a Shallow Trench Isolation (STI) structure. The active region may have different layouts according to the requirements of different semiconductor memory structures, and the scope of the present invention should not be limited too much herein.
Specifically, the bit line contact 212 is located on the active region 214, and the bit line contact isolation 205 is located on the isolation structure 203.
As an example, the bottom surface of the bit line contact 212 is lower than the bottom surface of the bit line contact spacer 205.
As an example, the substrate 201 includes a plurality of word line groups I arranged in parallel, each of the word line groups I includes two word lines 208 arranged in parallel, corresponding to a plurality of active regions arranged in the same direction, and the bit line contacts 212 and the bit line contact spacers 205 are both distributed between the two word lines of the word line group. In the present embodiment, the word line 208 is buried (embedded in the substrate) and is not visible in a top view, and in order to show the relative position relationship between the word line 208 and the bit line contact isolation 205, the bit line contact 212 and the bit line 211, the boundary of the word line 208 is shown by a dotted line in fig. 20.
As an example, the word lines 208 are linear, the bit lines 211 are wavy, and the extending direction X of the bit lines is perpendicular to the extending direction Y of the word lines. In other embodiments, the word lines and bit lines may have other line types as required, and the scope of the present invention should not be limited too much.
As an example, the bit line contact spacer 205 is made of one material selected from the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride.
In the semiconductor memory structure, the bit line contact parts are separated by the bit line contact isolation parts, so that the short circuit of the bit line can be effectively prevented, the process window of subsequent bit line etching is increased, and the resistance value of the bit line contact caused by overetching of a contact material is prevented from being increased.
In summary, in the semiconductor memory structure and the method for fabricating the bit line contact thereof of the present invention, the bit line contact isolation is first fabricated before the deposition of the bit line contact material, so that the bit line contact is isolated by the bit line contact isolation at the deposition stage, and even if the etching is incomplete in the subsequent etching process, the short circuit of the bit line is not caused. The invention can avoid the situation that the short circuit of the bit line is caused because the contact material is not completely etched, increase the process window of the subsequent bit line etching, and simultaneously prevent the resistance value of the bit line contact from being increased because the contact material is over-etched. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (21)
1. A method for manufacturing a bit line contact part is characterized by comprising the following steps:
providing a substrate, wherein an etching stop layer is formed on the substrate;
forming a plurality of discretely disposed contact vias in the etch stop layer to form a plurality of bit line contact spacers on the substrate between the word lines to space the contact vias;
forming a contact material in the contact via, the contact material filling the contact via and covering the bit line contact isolation;
removing excess contact material above the bit line contact spacers to form a plurality of initial contacts in the contact vias and spaced by the bit line contact spacer bottoms; and
and forming a plurality of bit lines, wherein the bottom surface of each bit line is respectively connected with the top surfaces of the initial contact parts, the top surfaces of the initial contact parts are not completely covered by the bit lines, the parts of the initial contact parts which are not covered by the bit lines are further removed, and the parts of the initial contact parts which are positioned below the bit lines are reserved as the bit line contact parts.
2. The method of claim 1, wherein forming the contact via comprises:
forming a hard mask layer on the etching stop layer;
forming a photoresist layer on the hard mask layer, and patterning the photoresist layer;
etching the hard mask layer by taking the patterned photoresist layer as a mask so as to transfer the pattern of the photoresist layer to the hard mask layer and pattern the hard mask layer;
and etching the etching stop layer by taking the patterned hard mask layer as a mask so as to obtain the contact through hole.
3. The method of claim 1, wherein: and simultaneously forming a bit line protection layer positioned above the bit line when the bit line is formed so as to protect the bit line in the process of removing the part of the initial contact part which is not covered by the bit line.
4. The method of claim 1, wherein: in the step of providing the substrate, an isolation structure is further formed in the substrate, and the isolation structure defines a plurality of active regions in the substrate; in the step of forming the contact via, the contact via is located above the active region, the bottom of the contact via exposes the active region, and the bit line contact isolation portion is located above the isolation structure.
5. The method of claim 4, wherein: the contact through hole extends downwards into the active region, so that the bottom of the contact through hole is lower than the lower surface of the etching stop layer.
6. The method of claim 5, wherein: the contact via has a greater depth of recess from the upper surface of the substrate.
7. The method of claim 1, wherein: the substrate comprises a plurality of word line groups which are arranged in parallel, each word line group comprises two word lines which are arranged in parallel, corresponding to the active regions which are arranged in the same direction, and the contact through holes and the bit line contact isolation parts are all distributed between the two word lines in the word line groups.
8. The method of claim 7, wherein: the word line is linear type, the bit line is wavy line type, the extending direction of bit line is perpendicular to the extending direction of word line.
9. The method of claim 7, wherein: the length of the contact through hole in the extending direction of the word line is between 10nm and 70 nm.
10. The method of claim 1, wherein: and before forming the contact material, carrying out ion implantation on the substrate at the bottom of the contact through hole so as to reduce the contact resistance of the material at the bottom of the contact through hole.
11. The method of claim 1, wherein: the bit line contact spacer is made of a material selected from the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride.
12. A semiconductor memory structure, comprising:
a substrate;
a plurality of bit line contact isolation parts of an etching stop layer, which are separately arranged on the substrate to isolate a plurality of bit line contact regions in the substrate, wherein in an extending direction, the upper surface of the bit line contact region of the substrate and the top surface and the side surface of the bit line contact isolation part form a contact material forming surface with a height difference;
a plurality of bit line contacts of contact material disposed on the bit line contact regions, wherein the bit line contacts are separated from each other by the bit line contact spacers in the extending direction, and the bit line contacts and the bit line contact spacers are separately disposed;
and the bottom surface of each bit line is respectively connected with the top surfaces of the bit line contact parts.
13. The semiconductor memory structure of claim 12, wherein: the bit line contact region is more recessed into the upper surface of the substrate.
14. The semiconductor memory structure of claim 13, wherein: the bit line contact region has a more recessed depth of between 1nm and 5 nm.
15. The semiconductor memory structure of claim 12, wherein: the thickness of the bit line contact isolation part is between 20nm and 60 nm.
16. The semiconductor memory structure of claim 12, wherein: a bit line protection layer is further formed on the bit line.
17. The semiconductor memory structure of claim 12, wherein: an isolation structure is further formed in the substrate, the isolation structure defining a plurality of active regions in the substrate, the bit line contact portion being located on the active regions, the bit line contact isolation portion being located on the isolation structure.
18. The semiconductor memory structure of claim 12, wherein: the bottom surface of the bit line contact is lower than the bottom surface of the bit line contact isolation.
19. The semiconductor memory structure of claim 12, wherein: the substrate comprises a plurality of word line groups which are arranged in parallel, each word line group comprises two word lines which are arranged in parallel, the two word lines correspond to a plurality of active regions which are arranged in the same direction, and the bit line contact parts and the bit line contact isolation parts are distributed between the two word lines of the word line groups.
20. The semiconductor memory structure of claim 19, wherein: the word line is linear type, the bit line is wavy line type, the extending direction of bit line is perpendicular to the extending direction of word line.
21. The semiconductor memory structure of claim 12, wherein: the bit line contact spacer is made of a material selected from the group consisting of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and boron nitride.
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| CN201810637317.4A CN110620113A (en) | 2018-06-20 | 2018-06-20 | Semiconductor memory structure and manufacturing method of bit line contact part thereof |
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| CN201810637317.4A CN110620113A (en) | 2018-06-20 | 2018-06-20 | Semiconductor memory structure and manufacturing method of bit line contact part thereof |
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| WO2023197478A1 (en) * | 2022-04-13 | 2023-10-19 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure, and structure thereof |
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| CN107492550A (en) * | 2017-08-08 | 2017-12-19 | 睿力集成电路有限公司 | Memory, its manufacture method and semiconductor devices |
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| CN107342263A (en) * | 2017-07-07 | 2017-11-10 | 睿力集成电路有限公司 | Memory and forming method thereof, semiconductor devices |
| CN107492550A (en) * | 2017-08-08 | 2017-12-19 | 睿力集成电路有限公司 | Memory, its manufacture method and semiconductor devices |
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