WO2023197478A1

WO2023197478A1 - Method for manufacturing semiconductor structure, and structure thereof

Info

Publication number: WO2023197478A1
Application number: PCT/CN2022/107117
Authority: WO
Inventors: 吴玉雷
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-04-13
Filing date: 2022-07-21
Publication date: 2023-10-19
Also published as: CN116981245A

Abstract

The present disclosure relates to the technical field of semiconductors. Disclosed are a method for manufacturing a semiconductor structure, and a structure thereof. The method for manufacturing a semiconductor structure may comprise: providing a substrate, wherein the substrate comprises word lines, which extend in a first direction, and active areas, which extend in a second direction; forming an initial mask on the substrate; on an initial mask layer, forming a plurality of first pattern layers which are arranged at intervals, wherein the first pattern layers extend in a third direction; patterning the initial mask by taking the first pattern layers as masks; on the patterned initial mask, forming a plurality of second pattern layers, which are arranged at intervals, wherein the second pattern layers extend in a fourth direction; patterning the initial mask by taking the second pattern layers as masks, so as to form a mask layer; and patterning the substrate by taking the mask layer as a mask, so as to form a bit line contact pattern in the active area of the substrate.

Description

A method for manufacturing a semiconductor structure and its structure

This disclosure is based on a Chinese patent application with the application number 202210388289.3, the filing date being April 13, 2022, and the application title being "A manufacturing method of a semiconductor structure and its structure", and claims the priority of the Chinese patent application. The entire contents of the Chinese patent application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to, but is not limited to, a method of manufacturing a semiconductor structure and its structure.

Background technique

Memory is a memory component used to store programs and various data information. The random access memory (Random Access Memory, RAM) used in general computer systems can be divided into two types: dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (Static Random-Access Memory, SRAM). Dynamic random access memory is a semiconductor memory device commonly used in computers and consists of many repeating memory cells.

Each memory cell usually includes a capacitor and a transistor. The drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The transistor is connected to the bit line through the bit line contact structure, and the capacitor is connected to the bit line through the capacitor contact window.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and its structure.

According to some embodiments of the disclosure, a first aspect of the embodiments of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate includes a word line extending along a first direction and an active line extending along a second direction. area, the first direction is different from the second direction; forming an initial mask on the substrate; forming a plurality of first pattern layers arranged at intervals on the initial mask layer, the first pattern The layer extends along the third direction; using the first graphic layer as a mask, patterning the initial mask; forming a plurality of second graphic layers arranged at intervals on the patterned initial mask, so The second graphic layer extends along a fourth direction, and the third direction is different from the fourth direction; using the second graphic layer as a mask, the initial mask is patterned to form a mask layer; The mask layer is a mask, patterns the substrate, and forms a bit line contact pattern in the active area of the substrate.

In some embodiments, the angle between the first direction and the second direction is a first angle, and the angle between the third direction and the fourth direction is a second angle, And the first included angle and the second included angle satisfy, where α is the first included angle and β is the second included angle.

In some embodiments, the first included angle ranges from 60° to 80° or from 100° to 120°.

In some embodiments, the initial mask includes a first initial mask and a second initial mask that are stacked in sequence, and the material of the first initial mask is different from the material of the second initial mask; Using the first pattern layer as a mask, the method of patterning the initial mask includes etching at least part of the thickness of the second initial mask to pattern the initial mask.

In some embodiments, using the second pattern layer as a mask, the method of patterning the initial mask includes etching at least part of the thickness of the first initial mask to pattern the initial mask. .

In some embodiments, the material of the first initial mask includes silicon dioxide, and the material of the second initial mask includes silicon oxynitride.

In some embodiments, before forming the second initial mask, the method further includes: forming a first intermediate layer on the surface of the first initial mask; using the second graphics layer as a mask, patterning the Before the initial masking, the method further includes: using the second graphics layer as a mask to pattern the first intermediate layer.

In some embodiments, the method further includes: forming a filling layer, the filling layer is located on the initial mask surface after patterning, and the top surface of the filling layer is higher than the top surface of the initial mask; forming a first protection layer layer, the first protective layer is located on the surface of the filling layer; before patterning the initial mask using the second graphics layer as a mask, it also includes patterning the first protective layer and the filling layer. layer.

In some embodiments, the material of the filling layer includes a spin-coatable agent, and the material of the first protective layer includes silicon oxynitride.

In some embodiments, before forming the first graphic layer, the method further includes: forming a second intermediate layer, the second intermediate layer being located on the surface of the second initial mask; Forming a second protective layer; using the first graphic layer as a mask, before patterning the initial mask, further comprising: using the first graphic layer as a mask, patterning the second protective layer and the The second middle layer.

In some embodiments, the material of the second protective layer includes silicon oxynitride, and the material of the second intermediate layer includes carbon-containing materials.

In some embodiments, before forming the first initial mask, the method further includes: forming a third intermediate layer, the third intermediate layer being located on the surface of the substrate; using the mask layer as a mask, patterning Before patterning the active area, the method further includes: using the mask layer as a mask to pattern the third intermediate layer.

In some embodiments, the material of the third intermediate layer includes carbonaceous material.

In some embodiments, the material of the first graphic layer includes photoresist, and the material of the second graphic layer includes photoresist.

In some embodiments, the orthographic projection of the first graphics layer on the surface of the substrate is a first strip-shaped pattern, and the orthographic projection of the second graphics layer on the substrate is a second strip-shaped pattern, and the The angle between the first strip pattern and the second strip pattern is 70° to 95°.

According to some embodiments of the present disclosure, a second aspect of the embodiments of the present disclosure provides a semiconductor structure formed using the above-mentioned manufacturing method of the semiconductor structure.

The technical solution provided by the embodiment of the present disclosure at least has the following advantages: first forming a first graphic layer arranged at intervals, patterning the initial mask through the first graphic layer, and then forming a second graphic layer arranged at intervals, and using The second graphic layer is an initial mask for mask patterning to form a mask layer. The mask layer is formed through two patternings, and each patterning forms a continuous groove. Through the first graphic layer and the second Patterns are etched layer by layer to form a mask layer with a target pattern, and then by using the mask layer with the target pattern as a mask patterning base to form the required bit line contact pattern on the base, the formation of bit line contacts can be reduced. The difficulty of the pattern.

Other aspects will be apparent after reading and understanding the drawings and detailed description.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, similar reference numbers are used to identify similar elements. The drawings in the following description are of some, but not all, embodiments of the disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

1 to 9 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

Detailed ways

The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the disclosed embodiments. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present disclosure. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments can be arbitrarily combined with each other.

As the process size decreases, it becomes increasingly difficult to transfer the bit line contact pattern layer by layer through the Litho-Etch-Litho-Etch method. In order to achieve the accuracy of the pattern transfer, more advanced technology is required. Photolithography process, the corresponding formation cost will also increase a lot.

Embodiments of the present disclosure disclose a method for manufacturing a semiconductor structure, by first forming a first pattern layer arranged at intervals, patterning an initial mask using the first pattern layer as a mask, and then forming spaced rows on the initial mask. The second graphic layer of the cloth, and the directions of the first graphic layer and the second graphic layer are inconsistent, by patterning the initial mask using the second graphic layer as a mask, a mask layer with the target pattern is formed, and a continuous pattern is formed through patterning The process difficulty of the groove is low, which can reduce the difficulty of the entire production method, and can also reduce the difficulty of the photolithography process and reduce the cost of the entire production method.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in each embodiment of the present disclosure, many technical details are provided to allow the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented.

Referring to FIG. 1 , FIG. 1 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure, including: providing a substrate 100 , and the substrate 100 includes a word line 110 extending along a first direction and an active region 120 extending along a second direction. , the first direction is different from the second direction; an initial mask 140 is formed on the substrate 100; a plurality of first graphic layers 150 arranged at intervals are formed on the initial mask 140, and the first graphic layers 150 extend along the third direction.

In some embodiments, the word line 110 may include a conductive layer 111, a gate oxide layer 112, and a protective layer 113. The gate oxide layer 112 at least covers the sidewalls of the active area 120, and the gate oxide layer 112 may also cover the conductive layer 111. On the bottom side, the protective layer 113 is located on the conductive layer 111. The material of the conductive layer 111 can be a metal material such as tungsten metal. The material of the gate oxide layer 112 can be an oxide such as silicon oxide. The material of the protective layer 113 can be an insulating material such as silicon nitride. Material.

In some embodiments, the conductive layer can also be a multi-layer structure, which can include a diffusion barrier layer and a metal layer. The diffusion barrier layer is located between the metal layer and the gate oxide layer to prevent metal ions from diffusing in the metal layer. The metal layer is In order to improve the conduction rate of the word line, embodiments of the present disclosure do not limit the conductive layer.

In some embodiments, the substrate further includes a substrate 130 and an isolation structure 121. The substrate 130 is connected to the active area 120. The isolation structure 121 is located on the substrate 130. The isolation structure 121 is also located between the active areas 120, and The outer surface of part of the word line 110 is also surrounded by an isolation structure 121 .

In some embodiments, the material of the isolation structure 121 may be an STI (Shallow Trench Isolation) structure, and the material of the isolation structure 121 may be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

In some embodiments, the surface of the substrate 100 further includes a target layer 131 , the target layer 131 is located between the substrate 100 and the initial mask 140 , and the target layer 131 is in contact with the surface of the substrate 100 . The target layer 131 is used to subsequently form a bit line contact pattern on the target layer 131. The material of the target layer 131 can be polysilicon, or the material of the target layer 131 can also be other materials. The target layer 131 is only used as an intermediate process for forming the bit line contact pattern. film layer, the embodiment of the present disclosure does not limit the material of the target layer 131 .

In some embodiments, the material of the substrate 130 may be silicon, germanium or silicon germanium, and the material of the substrate 130 may also be doped. For example, if the material of the substrate 130 is silicon, the substrate 130 may be made of silicon. The base 130 is doped with a trace amount of trivalent elements, such as boron, indium, gallium or aluminum, to form a P-type substrate. Similarly, the substrate 130 is doped with a trace amount of a pentavalent element, such as phosphorus, antimony. , arsenic, etc., thereby forming an N-type substrate. The selection of doping elements of the substrate 130 can be considered based on actual needs and product performance. This disclosure does not limit the material of the substrate 130 and the doped elements.

In some embodiments, the initial mask 140 includes a stacked first initial mask 142 and a second initial mask 143, and the first initial mask 142 and the second initial mask 143 are made of different materials. In some embodiments, the material of the first initial mask 142 includes silicon dioxide, and the material of the second initial mask 143 includes silicon oxynitride. By setting the materials of the first initial mask 142 and the second initial mask 143 to be different, the second initial mask 143 can be patterned first to form the target pattern, and the unnecessary film layers after patterning can be removed. The pattern transfer method forms a target pattern on the first initial mask 142, and then transfers the pattern of the first initial mask 142 to the target layer 131, by setting the distance between the first initial mask 142 and the second initial mask 143. Different materials can avoid the removal of reagents or etching ions from directly contacting the target layer 131 during the removal of unnecessary film layers after patterning, thereby affecting the target layer 131 and thus improving the reliability of the semiconductor structure.

Continuing to refer to FIG. 1 , in some embodiments, before forming the first pattern layer 150 , it also includes: forming a second intermediate layer 180 , the second intermediate layer 180 is located on the surface of the second initial mask 143 ; A second protective layer 190 is formed on the surface of 180 .

By forming the second intermediate layer 180 on the surface of the second initial mask 143, the uniformity of the formed first pattern layer 150 can be improved, thereby improving the accuracy of subsequent patterning, thereby improving the accuracy of subsequent patterning. However, in some embodiments, the material of the second intermediate layer 180 is relatively soft and the shape of the formed second intermediate layer 180 is not good. Therefore, the second protective layer 190 can be formed on the surface of the second intermediate layer 180 , the material of the second protective layer 190 is relatively hard, so the shape of the second intermediate layer 180 can be improved by limiting the position of the second intermediate layer 180, and by forming the second protective layer 190, the second initial mask 143 can be During the subsequent removal of the first pattern layer 150, it is not in contact with the etching reagent used to remove the first pattern layer 150, so that the second initial mask 143 can be protected, thereby improving the accuracy of patterning.

In some embodiments, the material of the second protective layer 190 includes silicon oxynitride, and the material of the second intermediate layer 180 includes carbonaceous materials.

In some embodiments, the second intermediate layer 180 can be formed by spin-coating a carbon-containing material on the surface of the second initial mask 143. The second intermediate layer 180 is formed by using a spin coating process, which has a faster formation time. speed, which is conducive to shortening the manufacturing process time; the corresponding material of the second intermediate layer 180 includes carbon or carbon-containing materials. The texture of carbon or carbon-containing materials is relatively soft and is easily removed by etching, which is conducive to further shortening the manufacturing process of the semiconductor structure. duration.

In some embodiments, silicon oxynitride can be directly deposited on the surface of the second intermediate layer 180 . It can be understood that the material of the second intermediate layer 180 is relatively soft. If the first intermediate layer 180 is directly formed on the surface of the second intermediate layer 180 , The graphic layer 150 may cause the second intermediate layer 180 to deform under the action of gravity of the first graphic layer 150. Therefore, the second protective layer 190 can be formed on the surface of the second intermediate layer 180, and the corresponding second protective layer 190 can be The material may be silicon oxynitride, which is relatively hard. The second protective layer 190 formed on the surface of the second intermediate layer 180 can protect the second intermediate layer 180 from deformation, thereby improving the accuracy of pattern formation.

In some embodiments, before forming the second initial mask 143, the method further includes: forming the first intermediate layer 200 on the surface of the first initial mask 142. The formation of the first intermediate layer 200 can serve as an etching stop during the subsequent patterning of the second initial mask 143. That is, the material of the first intermediate layer 200 is different from the material of the second initial mask 143, so the etching The etching reagent used to etch the second initial mask 143 is different from the etching reagent used to etch the first intermediate layer 200. Therefore, by forming the first intermediate layer, it can be avoided that the etching reagent used to etch the second initial mask 143 is different from the first initial intermediate layer 200. The masks 142 are in contact, thereby preventing the etching reagent used to etch the second initial mask 143 from affecting the first initial mask 142, thereby improving the pattern accuracy of subsequent formation.

In some embodiments, the material of the first intermediate layer 200 may be the same as the material of the second intermediate layer 180, and the method of forming the first intermediate layer 200 may adopt a spin coating process, which has a faster formation rate. It is beneficial to shorten the manufacturing process time; and the material of the first intermediate layer 200 can be carbon or carbon-containing materials. The texture of carbon or carbon-containing materials is relatively soft and can be easily removed by etching, which is beneficial to further shortening the manufacturing process time of the semiconductor structure.

In some embodiments, before forming the first initial mask 142 , it also includes: forming a third intermediate layer 210 , and the third intermediate layer 210 is located on the surface of the target layer 131 . It can be understood that the third intermediate layer 210 can be used to play an etching stop role in the subsequent patterning of the first initial mask 142 , that is, the material of the third intermediate layer 210 is different from the first initial mask 142 . The materials are different, and the etching reagent for etching the first initial mask 142 is different from the etching reagent for etching the third intermediate layer 210 . Therefore, the etching of the first initial mask 142 can be avoided by forming the third intermediate layer 210 The reagent is in contact with the target layer 131, thereby preventing the etching reagent used to etch the first initial mask 142 from affecting the target layer 131, thereby improving the pattern accuracy of subsequent formation.

In some embodiments, the material of the third intermediate layer 210 may be the same as the material of the second intermediate layer 180 , and the method of forming the third intermediate layer 210 may also adopt a spin coating process, which has a faster formation rate. , which is beneficial to shortening the manufacturing process time; and the material of the third intermediate layer 210 may include carbon-containing materials. Carbon or carbon-containing materials are relatively soft and can be easily removed by etching, which is beneficial to further shortening the manufacturing process time of the semiconductor structure.

Referring to FIG. 2, the first pattern layer 150 (refer to FIG. 1) is used as a mask to pattern the initial mask 140.

In some embodiments, the initial mask 140 may include a first initial mask 142 and a second initial mask 143 that are stacked in sequence, and the material of the first initial mask 142 is different from the material of the second initial mask 143; Using the first pattern layer 150 (refer to FIG. 1 ) as a mask, the method of patterning the initial mask 140 includes: etching at least part of the thickness of the second initial mask 143 to pattern the initial mask 140 .

It can be understood that the second initial mask 143 is patterned this time to form grooves extending along the third direction on the second initial mask 143, and the grooves are arranged at intervals. By forming grooves extending along the third direction, Compared with directly forming spaced recessed holes on the second initial mask 143, the grooves are less difficult to form, thereby reducing the formation difficulty of the entire process and reducing the material cost of the entire process.

In some embodiments, using the first graphics layer as a mask, during the process of patterning the initial mask, at least part of the first initial mask can be patterned to form spaced grooves on the first initial mask. .

In some embodiments, before forming the first pattern layer 150, it also includes: forming a second intermediate layer 180 (refer to FIG. 1), the second intermediate layer 180 (refer to FIG. 1) is located on the surface of the second initial mask 143; A second protective layer 190 (refer to FIG. 1 ) is formed on the surface of the second intermediate layer 180 (refer to FIG. 1 ); using the first pattern layer 150 (refer to FIG. 1 ) as a mask, before patterning the initial mask 140 , it also includes: Using the first pattern layer 150 (refer to FIG. 1 ) as a mask, the second protective layer 190 (refer to FIG. 1 ) and the second intermediate layer 180 (refer to FIG. 1 ) are patterned.

By forming the second intermediate layer 180 (refer to FIG. 1) and the second protective layer 190 (refer to FIG. 1), they can cooperate with the first graphic layer. By first forming the second intermediate layer 180 (refer to FIG. 1) and the second protective layer 190 (refer to Figure 1), and then form corresponding patterns on the second initial mask 143, which can avoid over-etching of the second initial mask 143 and help improve the subsequent etching process. The quality of the pattern formed by the second initial mask 143.

In some embodiments, patterning the second initial mask 143 further includes: removing the second intermediate layer 180 (refer to FIG. 1 ), the second protective layer 190 (refer to FIG. 1 ), and the first graphics layer 150 (refer to FIG. 1 ).

Referring to FIG. 3 , a plurality of second graphic layers 160 arranged at intervals are formed on the patterned initial mask 140 . The second graphic layers 160 extend along a fourth direction, and the third direction is different from the fourth direction.

In some embodiments, the material of the first graphic layer 150 (refer to FIG. 1 ) includes photoresist, and the material of the second graphic layer 160 includes photoresist.

Photoresists are classified into two categories: positive and negative according to the image they form. During the photoresist process, after the coating is exposed and developed, the exposed part is dissolved and the unexposed part remains. The coating material is a positive photoresist. If the exposed portion is retained and the unexposed portion is dissolved, the coating material is a negative photoresist.

By selecting the material of the first graphics layer 150 (refer to FIG. 1 ) and the second graphics layer 160 as photoresist, the target pattern can be easily formed on the first graphics layer 150 (refer to FIG. 1 ) and the second graphics layer 160 .

In some embodiments, before forming the second graphics layer 160, the method further includes: forming a filling layer 220, the filling layer 220 is located on the surface of the patterned initial mask 140, and the top surface of the filling layer 220 is higher than the top surface of the initial mask 140. surface; a first protective layer 230 is formed, and the first protective layer 230 is located on the surface of the filling layer 220.

By forming the filling layer 220, the gap in the patterned second initial mask 143 can be filled, thereby increasing the flatness of the second initial mask 143, thereby improving the patterning when the second initial mask 143 is subsequently patterned again. accuracy.

The material of the filling layer 220 is relatively soft, and the formed filling layer 220 has poor morphology. Therefore, the first protective layer 230 can be formed on the surface of the filling layer 220, thereby improving the morphology of the filling layer 220.

In some embodiments, the filling layer 220 can be formed by a spin coating process, and the first protective layer 230 can be formed by chemical vapor deposition. The spin coating process has a faster formation rate and is beneficial to shortening the manufacturing process time; corresponding filling The material of the layer 220 may be a spin-coatable reagent. The material of the spin-coatable reagent has a faster etching rate, which can increase the speed of the entire etching process and reduce the production time of the entire production process.

Referring to FIG. 4 , the second pattern layer 160 is used as a mask to pattern the initial mask 140 to form a mask layer 141 .

In some embodiments, before patterning the initial mask 140 using the second pattern layer 160 as a mask, it further includes patterning the first protective layer 230 (refer to FIG. 3 ) and the filling layer 220 (refer to FIG. 3 ).

By forming the filling layer 220 (refer to FIG. 3 ) and the first protective layer 230 (refer to FIG. 3 ) on the surface of the initial mask 140 , the filling layer 220 (refer to FIG. 3 ) and the first protective layer 230 (refer to FIG. 3 ) can be formed first. A regular pattern is formed in the patterned initial mask 140, and the accuracy of the pattern of the patterned initial mask 140 can be improved.

In some embodiments, patterning the filling layer 220 (refer to FIG. 3) and the first protective layer 230 (refer to FIG. 3) further includes: patterning the second initial mask 143 to form a pattern on the second initial mask 143. Form target graphics.

It can be understood that the extension directions of the first graphics layer 150 (refer to FIG. 1) and the second graphics layer (refer to FIG. 3) are different. By patterning the second initial mask 143 twice, the remaining second initial mask is The film 143 is an overlapping portion of the first pattern layer 150 (refer to FIG. 1 ) and the second pattern layer 160 (refer to FIG. 3 ), and the non-overlapping portion is etched to form the bit line contact pattern 132 . Patterning the target layer 131 by etching grooves twice to form the bit line contact pattern 132 can reduce the difficulty of the entire production process and reduce the material cost of the entire production process.

In some embodiments, before patterning the initial mask 140 using the second graphics layer 160 as a mask, the process further includes: patterning the first intermediate layer 200 using the second graphics layer 160 as a mask.

It can be understood that the target pattern formed on the first intermediate layer 200 has high pattern accuracy, so the target pattern is first formed on the first intermediate layer 200 and the patterning is initialized by using the first intermediate layer 200 as a mask. The mask 140 can improve the pattern accuracy on the initial mask 140 .

In some embodiments, using the second pattern layer 160 as a mask, a method of patterning the initial mask 140 includes: etching at least part of the thickness of the first initial mask 142 to pattern the initial mask 140 . Through multiple patterning methods, the process difficulty of forming the mask layer 141 can be reduced, and the mask layer 141 with precise patterns can be formed, and the material cost used to form the mask layer 141 is also low.

After patterning the initial mask 140, it also includes: removing the second pattern layer 160 (refer to Figure 3), the first protective layer 230 (refer to Figure 3), the filling layer 220 (refer to Figure 3), the second initial mask 143 ( Referring to Figure 3) and the first intermediate layer 200.

In some embodiments, after patterning the second initial mask 143, the first protective layer 230 (refer to Figure 3), the filling layer 220 (refer to Figure 3) and the second graphics layer 160 (refer to Figure 3) can be removed first. The first intermediate layer 200 and the first initial mask 142 are patterned using the second initial mask 143 (refer to FIG. 3 ). After patterning the first initial mask 142, it also includes: removing the first intermediate layer 200.

The first initial mask 142 formed at this time is a mask layer 141 with an interval arrangement pattern. Through multiple patterning methods, the process difficulty of forming the mask layer 141 can be reduced, and a mask layer 141 with accurate patterns can be formed. , and the material cost used to form the mask layer 141 is also low.

Referring to FIGS. 5 to 7 , using the mask layer 141 as a mask, the target layer 131 is patterned to form the bit line contact pattern 132 . After forming the bit line contact pattern 132 , it also includes filling the bit line contact pattern 132 to form a bit line. After the bit line contact structure is formed, a bit line 170 electrically connected to the bit line contact structure can be prepared on the surface of the bit line contact structure.

Referring to FIG. 5 , in some embodiments, before using the mask layer 141 as a mask to pattern the target layer 131 , the method further includes: using the mask layer 141 as a mask to pattern the third intermediate layer 210 .

By first forming regular grooves on the third intermediate layer 210 and then forming corresponding patterns on the target layer 131 , over-etching of the target layer 131 can be avoided, which is beneficial to improving the formation of the target layer 131 during subsequent etching. The quality of the pattern.

Referring to FIG. 6 , target layer 131 is patterned to form bit line contact patterns 132 .

In some embodiments, during the process of patterning the target layer 131, a portion of the active area 120 is also patterned to ensure that the subsequently formed bit line contact structure is in contact with the active area 120.

Referring to FIG. 7 , the bit line contact pattern 132 is filled to form the bit line contact structure 133 . After forming the bit line contact structure 133 , the target layer 131 is also removed (refer to FIG. 6 ).

Referring to FIGS. 8 and 9 , FIG. 8 is a top view of a semiconductor structure provided by an embodiment of the present disclosure, and FIG. 9 is a schematic diagram of the extension direction of each film layer provided by an embodiment of the present disclosure. Bit lines 170 are formed which, in some embodiments, extend along a fifth direction N.

In some embodiments, the included angle between the first direction X and the second direction Y is a first included angle, the included angle between the third direction Z and the fourth direction M is a second included angle, and the first included angle The angle satisfies the second included angle, where α is the first included angle and β is the second included angle.

Referring to Figure 9, in some embodiments, the intersection point of the first direction X and the second direction Y is C, the intersection point of the second direction Y, the third direction Z and the fifth direction N is A, and the intersection point of the third direction Z and the fourth direction The intersection point of the direction M is D, the intersection point of the first direction X and the third direction Z is B, and the intersection point of the first direction, the fourth direction M and the fifth direction N is O. According to the mathematical relationship, it can be seen that ∠ODA=α=∠OBA+∠BOD; ∠OBA=∠BOD=α/2.

By controlling the extension directions of the first graphics layer 150 and the second graphics layer 160, the non-overlapping portion of the projection of the first graphics layer 150 on the substrate 100 and the projection of the second graphics layer 160 on the substrate 100 is the desired target. The required bit line contact pattern 132 can be formed through layer-by-layer etching.

In some embodiments, the first included angle α ranges from 60° to 80° or from 100° to 120°. It can be understood that after the well-spaced active regions 120 are formed, the direction of the active regions 120 is determined, Under the premise that the conditions are met, the area of the bit line contact pattern 132 formed on the active area 120 can be increased by adjusting the extension direction of the word line 110, the extension direction of the first graphic layer 150, and the extension direction of the second graphic layer 160, so that in When the active area 120 is relatively small, a larger area of the bit line contact pattern 132 can be exposed to form the bit line contact pattern, thereby increasing the contact area between the subsequently formed bit line contact structure and the active area 120 and reducing the bit line contact. The contact resistance between the structure and the active region 120 improves the performance of the semiconductor structure.

In some embodiments, the orthographic projection of the first graphic layer 150 on the surface of the substrate 100 is a first strip pattern, the orthographic projection of the second graphic layer 160 on the substrate 100 is a second strip pattern, and the first strip pattern is the same as The included angle of the second strip pattern is 70° to 95°, for example, 83°, 85° or 92°.

By limiting the first strip pattern and the second strip pattern, a process basis can be provided for the subsequent formation of the target pattern, and by limiting the angle between the first strip pattern and the second strip pattern, a direct alignment with the active area 120 can be made. Accurate bit line contact patterns require lower resolution accuracy in the photolithography process, reducing process difficulty and process costs, and can obtain more accurate bit line contact structures on smaller structures.

The present disclosure first forms the first graphic layer 150 arranged at intervals, patterns the initial mask 140 through the first graphic layer 150, and then forms the second graphic layer 160 arranged at intervals, and uses the second graphic layer 160 as a mask. The initial mask 140 is patterned to form the mask layer 141. The mask layer 141 is formed through two patternings, and each patterning is to form a continuous groove through the first graphics layer 150 and the second graphics layer. Etching 160 layers layer by layer to form the mask layer 141 with a target pattern can reduce the difficulty of forming the bit line contact pattern 132.

Embodiments of the present disclosure also provide a semiconductor structure, which can be formed using some or all of the above steps.

Each embodiment or implementation mode in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between various embodiments can be referred to each other.

In the description of this specification, reference to the description of the terms "embodiments," "exemplary embodiments," "some embodiments," "illustrative embodiments," "examples," etc. is intended to be described in connection with the embodiments or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description. It does not indicate or imply that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on the present disclosure.

It will be understood that the terms "first", "second", etc. used in this disclosure may be used to describe various structures in this disclosure, but these structures are not limited by these terms. These terms are used only to distinguish one structure from another.

In one or more of the figures, identical elements are designated with similar reference numbers. For the sake of clarity, various parts of the figures are not drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing processes and techniques, to provide a clearer understanding of the present disclosure. However, as one skilled in the art will appreciate, the present disclosure may be practiced without these specific details.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that it can still be used Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent substitutions are made to some or all of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present disclosure.

Industrial applicability

In the manufacturing method and structure of the semiconductor structure provided by the embodiments of the present disclosure, the difficulty of forming the bit line contact pattern can be reduced.

Claims

A method for manufacturing a semiconductor structure, including:

providing a substrate, the substrate including a word line extending along a first direction and an active area extending along a second direction, the first direction being different from the second direction;

forming an initial mask on the substrate;

Form a plurality of first graphic layers arranged at intervals on the initial mask, and the first graphic layers extend along a third direction;

Using the first graphics layer as a mask, pattern the initial mask;

Forming a plurality of second graphic layers arranged at intervals on the patterned initial mask, the second graphic layers extending along a fourth direction, the third direction being different from the fourth direction;

Using the second graphics layer as a mask, pattern the initial mask to form a mask layer;

Using the mask layer as a mask, the substrate is patterned, and a bit line contact pattern is formed in the active area of the substrate.
The method of manufacturing a semiconductor structure according to claim 1, wherein the angle between the first direction and the second direction is a first angle, and the angle between the third direction and the fourth direction is The included angle is the second included angle, and the first included angle and the second included angle satisfy, where α is the first included angle and β is the second included angle.
The method of manufacturing a semiconductor structure according to claim 2, wherein the first included angle ranges from 60° to 80° or from 100° to 120°.
The method of manufacturing a semiconductor structure according to claim 1, wherein the initial mask includes a first initial mask and a second initial mask that are stacked in sequence, and the material of the first initial mask is different from the material of the first initial mask. The materials of the second initial mask are different; using the first graphics layer as a mask, the method of patterning the initial mask includes:

Etching at least a portion of the thickness of the second initial mask to pattern the initial mask.
The method of manufacturing a semiconductor structure according to claim 4, wherein using the second pattern layer as a mask, the method of patterning the initial mask includes:

Etching at least a portion of the thickness of the first initial mask to pattern the initial mask.
The method of manufacturing a semiconductor structure according to claim 4, wherein the material of the first initial mask includes silicon dioxide, and the material of the second initial mask includes silicon oxynitride.
The method of manufacturing a semiconductor structure according to claim 4, before forming the second initial mask, further comprising: forming a first intermediate layer on the surface of the first initial mask; using the second pattern layer as Masking, before patterning the initial mask, further includes: using the second graphics layer as a mask, patterning the first intermediate layer.
The method of manufacturing a semiconductor structure according to claim 4, before forming the second graphic layer, further comprising:

Forming a filling layer, the filling layer is located on the patterned initial mask surface, and the top surface of the filling layer is higher than the top surface of the initial mask;

Forming a first protective layer, the first protective layer being located on the surface of the filling layer; before using the second graphics layer as a mask to pattern the initial mask, it also includes:

Pattern the first protective layer and the filling layer.
The method of manufacturing a semiconductor structure according to claim 8, wherein the material of the filling layer includes a spin-coatable agent, and the material of the first protective layer includes silicon oxynitride.
The method of manufacturing a semiconductor structure according to claim 4, before forming the first pattern layer, further comprising:

Forming a second intermediate layer located on the surface of the second initial mask; forming a second protective layer on the surface of the second intermediate layer; using the first graphics layer as a mask, patterning Before the initial mask, it also includes:

Using the first pattern layer as a mask, pattern the second protective layer and the second intermediate layer.
The method of manufacturing a semiconductor structure according to claim 10, wherein the material of the second protective layer includes silicon oxynitride, and the material of the second intermediate layer includes a carbon-containing material.
The method of manufacturing a semiconductor structure according to claim 4, before forming the first initial mask, further comprising:

Form a third intermediate layer, the third intermediate layer is located on the surface of the substrate; before using the mask layer as a mask to pattern the active area, it also includes:

Using the mask layer as a mask, the third intermediate layer is patterned.
The method of manufacturing a semiconductor structure according to claim 12, wherein the material of the third intermediate layer includes a carbon-containing material.
The method of manufacturing a semiconductor structure according to claim 1, wherein the material of the first pattern layer includes photoresist, and the material of the second pattern layer includes photoresist.
The method of manufacturing a semiconductor structure according to claim 1, wherein the orthographic projection of the first graphic layer on the surface of the substrate is a first strip pattern, and the orthographic projection of the second graphic layer on the substrate is It is a second strip-shaped figure, and the angle between the first strip-shaped figure and the second strip-shaped figure is 70° to 95°.
A semiconductor structure formed by the manufacturing method according to any one of claims 1 to 15.