CN113675077B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN113675077B CN113675077B CN202110939157.0A CN202110939157A CN113675077B CN 113675077 B CN113675077 B CN 113675077B CN 202110939157 A CN202110939157 A CN 202110939157A CN 113675077 B CN113675077 B CN 113675077B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 124
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 239000000126 substance Substances 0.000 claims abstract description 51
- 238000000227 grinding Methods 0.000 claims abstract description 42
- 238000007517 polishing process Methods 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000005498 polishing Methods 0.000 claims description 41
- 239000003990 capacitor Substances 0.000 claims description 15
- 239000010408 film Substances 0.000 description 156
- 239000000463 material Substances 0.000 description 41
- 238000002955 isolation Methods 0.000 description 22
- 239000002184 metal Substances 0.000 description 16
- 238000005530 etching Methods 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a first pattern area and a second pattern area, a film layer structure is covered on the substrate, a recess is formed in the film layer structure on the second pattern area, and the depth of the recess exceeds a preset specification; forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film structure outside the recess; and grinding the film layer structure outside the recess and the barrier layer on the surface of the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the film layer structure is larger than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification. The invention can improve the flatness of the surfaces of patterns with different densities after the chemical mechanical polishing process, thereby improving the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a method for fabricating a semiconductor device.
Background
In the chip manufacturing process, the pattern density of the device structure in each region on the substrate is different, and the device structure can be divided into a pattern dense region and a pattern sparse region. After depositing thin films on patterns with different densities, a large height difference is formed on the surface of the thin film, and even after Chemical Mechanical Polishing (CMP) process, the thickness of the thin film on the patterns with different densities is still different, so that the flatness of the surface of the device is poor, and the quality of a chip is reduced. The following is a specific description of two examples:
referring to fig. 1a to 1c, taking floating gate fabrication as an example, a substrate 111 includes a pattern dense region a111 and a pattern sparse region a112, shallow trench isolation structures 114 with dense arrangement are formed on the pattern dense region a111, and shallow trench isolation structures 114 with sparse arrangement are formed on the pattern sparse region a 112; as shown in fig. 1a, after depositing a floating gate material layer 113 covering the shallow trench isolation structures 114 on the oxide layer 112 on the top surface of the substrate 111, a first recess 115 is formed in the floating gate material layer 113 between two adjacent shallow trench isolation structures 114 of the pattern sparse region a112, and the depth of the first recess 115 is far beyond the specification; as shown in fig. 1b, the floating gate material layer 113 above the bottom surface of the first recess 115 is removed by photolithography and etching processes, so that the top surfaces of the floating gate material layer 113 on the pattern dense region a111 and the pattern sparse region a112 are flush; as shown in fig. 1c, the chemical mechanical polishing process is used to continue polishing the floating gate material layer 113, so that the floating gate material layer 113 on the top surface of the shallow trench isolation structure 114 is completely polished and removed, and a second recess 116 with a depth exceeding the specification is formed in the floating gate material layer 113 on the pattern sparse region a112 due to the slower polishing rate of the silicon oxide of the shallow trench isolation structure 114 than the polishing rate of the polysilicon of the floating gate material layer 113. Thus, in the examples shown in fig. 1a to 1c, the recess with a depth exceeding the specification is formed after the chemical mechanical polishing process is adopted, which affects the flatness of the surface of the whole device; in addition, in order to reduce the load during the chemical mechanical polishing process, a photolithography and etching process is added, resulting in an increase in cost.
Referring to fig. 2a to 2c, a substrate 121 includes a pattern dense region a121 and a pattern sparse region a122, a first insulating layer 122 is covered on the substrate 121, a MIM capacitor is formed on the first insulating layer 122 on the top surface of the pattern dense region a121, and the MIM capacitor includes a lower metal layer 1231, a second insulating layer 1232, and an upper metal layer 1233 from bottom to top; as shown in fig. 2b, a third insulating layer 124 is formed over the first insulating layer 122 covering the MIM capacitor, such that a first recess 1241 is formed in the third insulating layer 124 over the pattern sparse region a122 to a depth far beyond specification due to the presence of the MIM capacitor; as shown in fig. 2c, the third insulating layer 124 is polished by the chemical mechanical polishing process, since the third insulating layer 124 on the pattern dense region a121 is significantly higher than the third insulating layer 124 on the pattern sparse region a122, the polishing load is very high, and when the third insulating layer 124 at the first recess 1241 is polished to the required thickness h1, the third insulating layer 124 on the pattern dense region a121 still does not reach the required thickness h1, and the second recess 1242 with a depth exceeding the specification is still formed in the third insulating layer 124 on the pattern sparse region a122, which affects the flatness of the whole device surface.
Therefore, how to improve the flatness of the surface of the patterns with different densities after the chemical mechanical polishing process is a problem to be solved.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can improve the flatness of the surfaces of patterns with different densities after a chemical mechanical polishing process, thereby improving the performance of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first pattern area and a second pattern area, a film layer structure is covered on the substrate, a recess is formed in the film layer structure on the second pattern area, and the depth of the recess exceeds a preset specification;
forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film structure outside the recess; the method comprises the steps of,
and grinding the film layer structure outside the concave and the barrier layer on the surface of the concave by adopting a chemical mechanical grinding process, wherein the grinding rate of the film layer structure is larger than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
Optionally, the step of forming the barrier layer to cover the recess includes:
forming a barrier layer to cover the film layer structure on the first pattern area and the second pattern area;
and grinding and removing the barrier layer on the film layer structure outside the recess by adopting a chemical mechanical grinding process, and retaining the barrier layer on the film layer structure at the recess.
Optionally, device structures are formed in the film layer structures on the first pattern region and the second pattern region, and the arrangement density of the device structures on the first pattern region is greater than that on the second pattern region; the recess is located between two adjacent device structures on the second pattern region, and a bottom wall of the recess is higher than a top surface of the device structures.
Optionally, the device structure includes a shallow trench isolation structure extending from the film structure into the substrate; the film layer structure comprises a gate material layer for manufacturing a floating gate or a control gate.
Optionally, after forming the barrier layer to cover the recess and before polishing the barrier layer of the film structure and the recess surface outside the recess using a chemical mechanical polishing process, the method further includes:
and etching to remove the film structure with partial thickness outside the recess, wherein the top surface of the etched film structure outside the recess is not lower than the top surface of the barrier layer on the bottom wall of the recess.
Optionally, the step of polishing the film structure outside the recess and the barrier layer on the surface of the recess by using a chemical mechanical polishing process includes:
removing the barrier layer on the surface of the recess and the film structure outside the recess and higher than the top surface of the device structure by adopting a chemical mechanical polishing process, so that the top surface of the film structure outside the recess after polishing is lower than the top surface of the film structure at the recess;
and grinding the film layer structure which is higher than the top surface of the device structure and the device structure with partial thickness at the concave position and outside the concave position by adopting a chemical mechanical grinding process, wherein the grinding rate of the device structure is smaller than that of the film layer structure, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
Optionally, a device structure is formed in the film layer structure on the first pattern area; or, device structures are formed in the film layer structures on the first pattern region and the second pattern region, and the height of the device structures on the first pattern region is higher than that of the device structures on the second pattern region; the bottom wall of the recess is higher than the top surface of the device structure.
Optionally, the device structure includes a MIM capacitor or gate structure, and the film structure includes an insulating dielectric layer.
Optionally, after forming the barrier layer to cover the film layer structure on the first pattern region and the second pattern region and before removing the barrier layer on the film layer structure except for the recess by using a chemical mechanical polishing process, the method for manufacturing the semiconductor device further includes:
forming a sacrificial layer to cover the barrier layers on the first pattern area and the second pattern area, wherein the top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure at the recess;
and grinding the sacrificial layer by adopting a chemical mechanical grinding process until the barrier layer on the film layer structure outside the recess is exposed, wherein the top surface of the barrier layer on the film layer structure outside the recess exposed is flush with the top surface of the residual sacrificial layer on the film layer structure at the recess.
Optionally, the step of removing the barrier layer on the film structure except the recess by using a chemical mechanical polishing process includes:
and grinding and removing the barrier layer on the film layer structure outside the recess and the residual sacrificial layer on the film layer structure at the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the sacrificial layer is larger than that of the barrier layer.
Optionally, the preset specification is 100 angstroms.
Compared with the prior art, in the manufacturing method of the semiconductor device, for the substrate comprising the first pattern area and the second pattern area, the concave with the depth exceeding the preset specification is formed in the film layer structure on the second pattern area, the concave is covered by forming the barrier layer, the top surface of the barrier layer is lower than the top surface of the film layer structure except the concave, the film layer structure except the concave and the barrier layer on the surface of the concave are polished by adopting the chemical mechanical polishing process, and the polishing rate of the film layer structure is higher than the polishing rate of the barrier layer, so that the height difference of the film layer structure surfaces on the first pattern area and the second pattern area after polishing is within the preset specification, the flatness of the film layer structure with different densities after the chemical mechanical polishing process is improved, and the performance of the semiconductor device is further improved.
Drawings
FIGS. 1 a-1 c are schematic diagrams of a device fabricated by a chemical mechanical polishing process;
FIGS. 2 a-2 c are schematic diagrams of alternative devices fabricated using a chemical mechanical polishing process;
fig. 3 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4a to 4g are schematic device diagrams of a first embodiment of the method for manufacturing a semiconductor device shown in fig. 3;
fig. 5a to 5e are schematic device diagrams of a second embodiment in the method of manufacturing a semiconductor device shown in fig. 3.
Wherein, the reference numerals of fig. 1a to 5e are as follows:
111-a substrate; 112-an oxide layer; 113-a layer of floating gate material; 114-shallow trench isolation structures; 115-a first recess; 116-a second recess; 121-a substrate; 122-a first insulating layer; 1231-an underlying metal layer; 1232-a second insulating layer; 1233-upper metal layer; 124-a third insulating layer; 1241-a first recess; 1242-a second recess; 21-a substrate; 211-a gate dielectric layer; a layer of 22-gate material; 221-recessing; 23-shallow trench isolation structures; 24-a barrier layer; 31-a substrate; 32-a first insulating dielectric layer; 321-a metal interconnect structure; 331-a lower metal layer; 332-a first layer of insulating material; 333-an upper metal layer; 334-a second layer of insulating material; 34-a second insulating dielectric layer; 341-recessing; a 35-barrier layer; 36-sacrificial layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, a method for manufacturing a semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device includes:
step S1, providing a substrate, wherein the substrate comprises a first pattern area and a second pattern area, a film layer structure is covered on the substrate, a dent is formed in the film layer structure on the second pattern area, and the depth of the dent exceeds a preset specification;
s2, forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film layer structure outside the recess;
and S3, grinding the film layer structure outside the concave and the barrier layer on the surface of the concave by adopting a chemical mechanical grinding process, wherein the grinding rate of the film layer structure is larger than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after grinding is within a preset specification.
The method for manufacturing the semiconductor device according to the present embodiment will be described in more detail with reference to fig. 4a to 4g and fig. 5a to 5e, and fig. 4a to 4g and fig. 5a to 5e are schematic longitudinal sectional views of the semiconductor device.
According to step S1, a substrate is provided, wherein the substrate comprises a first pattern area and a second pattern area, a film layer structure is covered on the substrate, a recess is formed in the film layer structure on the second pattern area, and the depth of the recess exceeds a preset specification. The preset specification can be defined according to the type, performance requirement and the like of the manufactured semiconductor device, and refers to the depth requirement acceptable in the manufacturing process of the semiconductor device. The predetermined specification may be 100 angstroms.
In an embodiment of the present invention, device structures are formed in the film structures on the substrates of the first pattern area and the second pattern area, and the arrangement density of the device structures on the substrate of the first pattern area is greater than the arrangement density of the device structures on the substrate of the second pattern area, that is, the distance between two adjacent device structures on the substrate of the first pattern area is smaller than the distance between two adjacent device structures on the substrate of the second pattern area.
When the film structure is deposited on the substrate, as the arrangement density of the device structures on the substrate of the first pattern area is greater than that of the device structures on the substrate of the second pattern area, the space between two adjacent device structures on the substrate of the first pattern area is filled up to prevent the generation of a recess, and a recess is formed in the film structure between two adjacent device structures on the substrate of the second pattern area, wherein the bottom wall of the recess is higher than the top surface of the device structure. The smaller the arrangement density of the device structures on the substrate of the second pattern region (i.e., the larger the distance between two adjacent device structures), the greater the depth of the recess.
Referring to fig. 4a, the substrate 21 includes a first pattern area a21 and a second pattern area a22, the device structure is a shallow trench isolation structure 23, the film structure is a gate material layer 22 for manufacturing a floating gate or a control gate, the gate material layer 22 covers the shallow trench isolation structure 23, a gate dielectric layer 211 is further formed between the gate material layer 22 and the substrate 21, the shallow trench isolation structure 23 extends from the gate material layer 22 into the substrate 21 through the gate dielectric layer 211, and the arrangement density of the shallow trench isolation structures 23 on the first pattern area a21 is greater than the arrangement density of the shallow trench isolation structures 23 on the second pattern area a22, so that a recess 221 is formed in the gate material layer 22 between two adjacent shallow trench isolation structures 23 on the second pattern area a22, and the bottom wall of the recess 221 is higher than the top surface of the shallow trench isolation structure 23. The depth of the recess 221 exceeds a predetermined specification, so that the difference in height between the surfaces of the gate material layer 22 on the substrate 21 of the first pattern region a21 and the second pattern region a22 exceeds the predetermined specification, resulting in reduced surface flatness of the device. The depth of the recess 221 is, for example, 600 to 800 angstroms.
Or in another embodiment of the present invention, a device structure is formed in the film structure on the substrate of the first pattern area, no device structure is formed in the film structure on the substrate of the second pattern area, and a recess with a depth exceeding a preset specification is formed in the film structure on the second pattern area by the height of the device structure; or, the device structures are formed in the film structures on the substrates of the first pattern area and the second pattern area, and the height of the device structure on the substrate of the first pattern area is obviously higher than that of the device structure on the substrate of the second pattern area, so that the depth of the concave beyond the preset specification is formed in the film structure on the second pattern area. And, a bottom wall of the recess is higher than a top surface of the device structure. After depositing the film structure on the substrate, until the film structure on the substrate of the second pattern area reaches the required height of the device, if only the film structure on the substrate of the first pattern area is formed with the device structure, the higher the device structure in the film structure on the substrate of the first pattern area is, the greater the depth of the recess in the film structure on the substrate of the second pattern area is; and if the device structures are formed in the film structures on the substrates of the first pattern area and the second pattern area, the greater the height difference between the device structures on the substrate of the first pattern area and the device structures on the substrate of the second pattern area, the greater the depth of the concave in the film structures on the substrate of the second pattern area.
The device structure may be a MIM capacitor or a gate structure, and the film structure may be an insulating dielectric layer.
Taking a film structure on the substrate of the first pattern area as an example, a device structure is formed in the film structure on the substrate of the second pattern area, no device structure is formed in the film structure on the substrate of the second pattern area, and the device structure is an MIM capacitor, referring to fig. 5a, the substrate 31 includes a first pattern area a31 and a second pattern area a32, a first insulating medium layer 32 and a second insulating medium layer 34 are sequentially covered on the substrate 31, an MIM capacitor is formed on the first insulating medium layer 32 of the first pattern area a31, an MIM capacitor is not formed on the first insulating medium layer 32 of the second pattern area a32, and the second insulating medium layer 34 buries the MIM capacitor; after depositing the second insulating dielectric layer 34 over the first insulating dielectric layer 32, if the height h2 of the second insulating dielectric layer 34 over the second pattern region a32 meets the device requirement, the top surface of the second insulating dielectric layer 34 over the first pattern region a31 is higher than the top surface of the second insulating dielectric layer 34 over the second pattern region a32 due to the existence of the MIM capacitor, that is, a recess 341 is formed in the second insulating dielectric layer 34 over the second pattern region a32, and the bottom wall of the recess 341 is higher than the top surface of the MIM capacitor. The depth of the recess 341 exceeds a preset specification, so that the difference in height between the surfaces of the second insulating dielectric layer 34 on the substrate 31 in the first pattern area a31 and the second pattern area a32 exceeds the preset specification, resulting in a reduction in the surface flatness of the device.
The MIM capacitor includes a lower metal layer 331, a first insulating material layer 332, and an upper metal layer 333 from bottom to top, where a metal interconnect structure 321 is formed in the first insulating dielectric layer 32, and the lower metal layer 331 is electrically connected to the metal interconnect structure 321. The area of the lower metal layer 331 in the MIM capacitor may be larger than the areas of the first insulating material layer 332 and the upper metal layer 333, a second insulating material layer 334 may be covered on the top surface of the lower metal layer 331 not covered by the first insulating material layer 332, on the side surface of the first insulating material layer 332, and on the side and top surfaces of the upper metal layer 333, and the second insulating material layer 334 may be buried by the second insulating medium layer 34.
Or in other embodiments of the present invention, device structures are formed in the film structures on the substrate of the first pattern area and the second pattern area, the arrangement density of the device structures on the substrate of the first pattern area is greater than the arrangement density of the device structures on the substrate of the second pattern area, and the height of the device structures on the substrate of the first pattern area is higher than the device structures on the substrate of the second pattern area, so that the recess formed in the film structures on the substrate of the second pattern area further exceeds the preset specification.
Note that, the device structure and the film structure are not limited to the types of the above embodiments, and the device structure and the film structure may be appropriately selected according to the types of the semiconductor devices to be manufactured.
According to step S2, a barrier layer is formed to cover the recess, the top surface of the barrier layer being lower than the top surface of the film structure outside the recess. The bottom surface of the barrier layer is higher than the top surface of the device structure, i.e. the top surfaces of the film layer structures on the substrates of the first pattern region and the second pattern region are both higher than the top surface of the device structure.
The step of forming the barrier layer to cover the recess includes: firstly, forming a barrier layer to cover the film layer structures on the substrates of the first pattern area and the second pattern area, wherein the top surface of the barrier layer on the film layer structure outside the recess is higher than the top surface of the barrier layer on the film layer structure at the recess; and then, adopting a chemical mechanical polishing process to polish and remove the barrier layer on the film layer structure outside the recess, and retaining the barrier layer on the film layer structure at the recess. Wherein, the top surface of the barrier layer on the bottom wall of the recess is lower than the top surface of the film layer structure outside the recess, and the top surface of the barrier layer on the side wall of the recess may be flush with or slightly lower than the top surface of the film layer structure outside the recess.
In an embodiment of the present invention, if the arrangement density of the device structures on the substrate of the first pattern area is greater than the arrangement density of the device structures on the substrate of the second pattern area, and the recess is formed in the film structure between two adjacent device structures on the substrate of the second pattern area, the area occupied by the recess is small, so that when the barrier layer on the film structure except for the recess is removed by polishing through a chemical mechanical polishing process, the barrier layer on the film structure at the recess is not polished, and further the barrier layer on the film structure at the recess can be retained.
Referring to fig. 4 b-4 c, the step of forming the barrier layer 24 to cover the recess includes: first, as shown in fig. 4b, a barrier layer 24 is formed to cover the gate material layer 22 on the first pattern region a21 and the second pattern region a22, and the barrier layer 24 also covers the recess 221; then, as shown in fig. 4c, the barrier layer 24 on the gate material layer 22 outside the recess 221 is removed by chemical mechanical polishing, so that the barrier layer 24 on the gate material layer 22 at the recess 221 is remained. Wherein, during the polishing process, the barrier layer 24 on top of the sidewall of the recess 221 is also polished away, so that the top surface of the barrier layer 24 on the sidewall of the recess 221 may be flush with the top surface of the gate material layer 22 outside the recess 221 or slightly lower than the top surface of the gate material layer 22 outside the recess 221.
In another embodiment of the present invention, if only the device structure is formed in the film structure on the substrate of the first pattern region, or the device structure on the substrate of the first pattern region is higher than the device structure on the substrate of the second pattern region, the method for manufacturing a semiconductor device further includes, after forming the barrier layer to cover the film structures on the substrates of the first pattern region and the second pattern region and before removing the barrier layer on the film structure outside the recess by using a chemical mechanical polishing process: forming a sacrificial layer to cover the barrier layers on the first pattern area and the second pattern area, wherein the top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure at the recess due to the recess; and grinding the sacrificial layer by adopting a chemical mechanical grinding process until the barrier layer on the film layer structure outside the recess is exposed, wherein the top surface of the barrier layer on the film layer structure outside the recess exposed is flush with the top surface of the residual sacrificial layer on the film layer structure at the recess. The top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure outside the recess, so that the polishing rate of the sacrificial layer on the film layer structure outside the recess is higher than that of the sacrificial layer on the film layer structure outside the recess during polishing, and further, when the sacrificial layer on the film layer structure outside the recess is completely removed, a part of thickness of the sacrificial layer remains on the film layer structure outside the recess.
And removing the barrier layer on the film structure except the concave by adopting a chemical mechanical polishing process, wherein the step of removing the barrier layer on the film structure except the concave comprises the following steps of: and grinding and removing the barrier layer on the film layer structure outside the recess and the residual sacrificial layer on the film layer structure at the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the sacrificial layer is larger than that of the barrier layer, so that the barrier layer on the film layer structure outside the recess is ground and removed to expose the film layer structure, and meanwhile, the residual sacrificial layer on the film layer structure at the recess is ground and removed to expose the barrier layer. In this embodiment, since the area occupied by the device structure on the substrate of the first pattern area is small, and the recess is formed due to the height of the device structure on the substrate of the first pattern area or the height difference between the device structures on the substrate of the first pattern area and the substrate of the second pattern area, the recess is at least located in the whole film structure on the second pattern area, and the area occupied by the recess is large, if the sacrificial layer is not formed on the film structure in the recess, when the barrier layer on the film structure other than the recess is removed by polishing with the chemical mechanical polishing process, the barrier layer on the film structure in the recess is also contacted with the polishing pad and is removed by polishing; therefore, when the barrier layer on the film layer structure except the concave is removed by grinding, the residual sacrificial layer is covered on the film layer structure at the concave, so that the barrier layer on the film layer structure at the concave can be protected from being removed by grinding. Referring to fig. 5b to 5d, the step of forming the barrier layer to cover the recess includes: first, as shown in fig. 5b, a barrier layer 35 is formed to cover the first pattern region a31 and the second pattern region a32 on the second insulating dielectric layer 34, the barrier layer 35 also covers the recess 341, and the top surface of the barrier layer 35 on the second insulating dielectric layer 34 except for the recess 341 is higher than the top surface of the barrier layer 35 on the second insulating dielectric layer 34 at the recess 341; then, as shown in fig. 5b, a sacrificial layer 36 is formed to cover the barrier layer 35 on the first pattern region a31 and the second pattern region a32, and the top surface of the sacrificial layer 36 on the second insulating dielectric layer 34 except the recess 341 is higher than the top surface of the sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341; next, as shown in fig. 5c, the sacrificial layer 36 is polished by a chemical mechanical polishing process until the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341 is exposed, and the top surface of the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341 exposed is flush with the top surface of the remaining sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341; next, as shown in fig. 5d, the blocking layer 35 on the second insulating dielectric layer 34 except for the recess 341 is removed by polishing through a chemical mechanical polishing process until the underlying second insulating dielectric layer 34 is exposed, and the remaining sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341 is also removed by polishing until the underlying blocking layer 35 is exposed, wherein the remaining sacrificial layer 36 on the second insulating dielectric layer 34 at the recess 341 can protect the underlying blocking layer 35 from being removed by polishing. Since the thickness of the sacrificial layer 36 remaining on the second insulating dielectric layer 34 at the recess 341 is greater than the thickness of the barrier layer 35 on the second insulating dielectric layer 34 outside the recess 341, the polishing rate of the sacrificial layer 36 is greater than the polishing rate of the barrier layer 35.
And according to the step S3, a chemical mechanical polishing process is adopted to polish the film layer structure outside the recess and the barrier layer on the surface of the recess, and the polishing rate of the film layer structure is larger than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first pattern area and the second pattern area after polishing is within a preset specification. Then, the difference in height between the surface of the film layer structure on the first pattern area and the surface of the film layer structure on the second pattern area after grinding is 0; or, the film layer structure on the first pattern area and/or the second pattern area after grinding can form a dent, and the depth of the dent is within a preset specification.
In an embodiment of the present invention, if the arrangement density of the device structures on the first pattern area is greater than the arrangement density of the device structures on the second pattern area, after the forming of the barrier layer to cover the recess and before the polishing of the barrier layer on the surface of the recess and the film layer structure outside the recess by using the chemical mechanical polishing process, the method further includes: etching to remove the film structure with partial thickness outside the recess, wherein the top surface of the etched film structure outside the recess is not lower than the top surface of the barrier layer on the bottom wall of the recess; and after etching, the barrier layer on the sidewall of the recess may remain. The etching selectivity ratio of the film structure to the barrier layer is very high, so that the barrier layer on the film structure at the concave part can be used as a hard mask, and the barrier layer on the film structure at the concave part is hardly etched when the film structure outside the concave part is etched, thereby avoiding the film structure at the concave part from being etched; in addition, the photoetching process is not required to be executed before etching, so that the photomask is saved.
And removing the film layer structure with partial thickness except the concave by adopting an etching process before the subsequent chemical mechanical polishing process is adopted, so that the height difference between the top surface of the film layer structure except the concave and the top surface of the barrier layer on the film layer structure at the concave is reduced, and the load during the subsequent chemical mechanical polishing process can be reduced. Referring to fig. 4d, the gate material layer 22 is etched to remove a portion of the thickness outside the recess 221, and the top surface of the gate material layer 22 outside the recess 221 after etching is higher than the top surface of the barrier layer 24 on the bottom wall of the recess 221; the etch selectivity of the gate material layer 22 to the barrier layer 24 is so high that the barrier layer 24 on the inner surface of the recess 221 is hardly etched when the gate material layer 22 is etched.
And the step of polishing the film layer structure outside the recess and the barrier layer on the surface of the recess by adopting a chemical mechanical polishing process comprises the following steps: removing the barrier layer on the surface of the recess and the film structure outside the recess and higher than the top surface of the device structure by adopting a chemical mechanical polishing process, so that the top surface of the film structure outside the recess after polishing is lower than the top surface of the film structure at the recess; and grinding the film layer structure which is higher than the top surface of the device structure and part of the thickness of the device structure at the concave position and outside the concave position by adopting a chemical mechanical grinding process, wherein the grinding rate of the device structure is smaller than that of the film layer structure. When the film layer structure on the top surface of the device structure is completely removed and the thickness of the removed part of the device structure is ground, although the grinding rate of the device structure is smaller than that of the film layer structure, the top surface of the film layer structure at the concave part is obviously higher than the top surface of the film layer structure outside the concave part after the barrier layer on the surface of the concave part is removed, so that when the device structure is ground to remove the thickness of the part, the part of the film layer structure at the concave part, which is higher than the film layer structure, is just ground, and the height difference of the film layer structure surfaces on the first pattern area and the second pattern area after grinding is within a preset specification.
Referring to fig. 4e to 4g, the step of polishing the film structure outside the recess 221 and the barrier layer 24 on the surface of the recess 221 by using a chemical mechanical polishing process includes: first, as shown in fig. 4e, a chemical mechanical polishing process is used to polish the barrier layer 24 on the surface of the recess 221 and the gate material layer 22 outside the recess 221 and above the top surface of the shallow trench isolation structure 23, where the top surface of the gate material layer 22 is lower than the top surface of the barrier layer 24 when the barrier layer 24 is polished to remove a part of the thickness because the polishing rate of the barrier layer 24 is lower than the polishing rate of the gate material layer 22; as shown in fig. 4f, when the barrier layer 24 is completely removed, the height of the gate material layer 22 above the top surface of the shallow trench isolation structure 23 outside the recess 221 is further lower than the height of the gate material layer 22 above the top surface of the shallow trench isolation structure 23 at the recess 221; then, as shown in fig. 4g, the gate material layer 22 and a part of the thickness of the shallow trench isolation structure 23 outside the recess 221 and at the recess 221 are polished by a chemical mechanical polishing process, and the polishing rate of the shallow trench isolation structure 23 is smaller than the polishing rate of the gate material layer 22, so that the difference in height between the polished surfaces of the gate material layer 22 on the first pattern area a21 and the second pattern area a22 is within a preset specification.
In the embodiment shown in fig. 4a to 4g, the material of the gate material layer 22 is, for example, polysilicon, the material of the barrier layer 24 is, for example, at least one of silicon oxide, silicon nitride and silicon oxynitride, and the material of the shallow trench isolation structure 23 is, for example, at least one of silicon oxide, silicon nitride and silicon oxynitride.
In another embodiment of the present invention, if only the device structure is formed in the film structure on the substrate of the first pattern area, or the device structure on the substrate of the first pattern area is higher than the device structure on the substrate of the second pattern area, in this step, the film structure exposed outside the recess and the barrier layer exposed at the recess are polished by using a chemical mechanical polishing process, because the top surface of the film structure exposed outside the recess is higher than the top surface of the barrier layer exposed at the recess, and the polishing rate of the film structure is higher than the polishing rate of the barrier layer, the portion of the film structure exposed outside the recess is just removed while the barrier layer at the recess is removed, so that the difference in height between the film structure surfaces on the first pattern area and the second pattern area after polishing is within a preset specification.
Referring to fig. 5e, the second insulating dielectric layer 34 exposed in the area outside the recess 341 and the barrier layer 35 exposed in the recess 341 are polished by using a chemical mechanical polishing process, so that the polished second insulating dielectric layer 34 in the area outside the recess 341 and the polished second insulating dielectric layer 34 in the recess 341 can reach the required height h2 of the device, and further the height difference between the surfaces of the second insulating dielectric layer 34 on the first pattern area a31 and the second pattern area a32 is within a preset specification.
In the embodiment shown in fig. 5a to 5e, the material of the second insulating medium layer 34 is, for example, silicon oxide, the material of the barrier layer 35 is, for example, at least one of silicon nitride, silicon carbide and nitrogen doped silicon carbide, and the material of the sacrificial layer 36 is, for example, silicon oxide or polysilicon.
In summary, for the substrate including the first pattern area and the second pattern area, the film structure on the second pattern area is formed with the recess with the depth exceeding the preset specification, the top surface of the barrier layer is lower than the top surface of the film structure outside the recess by forming the barrier layer to cover the recess, and the chemical mechanical polishing process is adopted to polish the film structure outside the recess and the barrier layer on the surface of the recess, and the polishing rate of the film structure is greater than the polishing rate of the barrier layer, so that the difference of the heights of the film structure surfaces on the first pattern area and the second pattern area after polishing is within the preset specification, thereby improving the flatness of the different density pattern surfaces after the chemical mechanical polishing process, and further improving the performance of the semiconductor device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (4)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first pattern area and a second pattern area, a film layer structure is covered on the substrate, a recess is formed in the film layer structure on the second pattern area, and the depth of the recess exceeds a preset specification;
forming a barrier layer to cover the recess, wherein the top surface of the barrier layer is lower than the top surface of the film structure outside the recess; the method comprises the steps of,
adopting a chemical mechanical polishing process to polish the film layer structure outside the recess and the barrier layer on the surface of the recess, wherein the polishing rate of the film layer structure is larger than that of the barrier layer, so that the height difference of the film layer structure surfaces on the first graph area and the second graph area after polishing is within a preset specification;
wherein the step of forming the barrier layer to cover the recess comprises:
forming a barrier layer to cover the film layer structure on the first pattern area and the second pattern area;
forming a sacrificial layer to cover the barrier layers on the first pattern area and the second pattern area, wherein the top surface of the sacrificial layer on the film layer structure outside the recess is higher than the top surface of the sacrificial layer on the film layer structure at the recess;
grinding the sacrificial layer by adopting a chemical mechanical grinding process until the barrier layer on the film layer structure outside the recess is exposed, wherein the top surface of the barrier layer on the film layer structure outside the recess exposed is flush with the top surface of the residual sacrificial layer on the film layer structure at the recess;
and grinding and removing the barrier layer on the film layer structure outside the recess and the residual sacrificial layer on the film layer structure at the recess by adopting a chemical mechanical grinding process, wherein the grinding rate of the sacrificial layer is larger than that of the barrier layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a device structure is formed in the film layer structure on the first pattern region; or, device structures are formed in the film layer structures on the first pattern region and the second pattern region, and the height of the device structures on the first pattern region is higher than that of the device structures on the second pattern region; the bottom wall of the recess is higher than the top surface of the device structure.
3. The method of manufacturing a semiconductor device of claim 2, wherein the device structure comprises a MIM capacitor or gate structure and the film structure comprises an insulating dielectric layer.
4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the predetermined specification is 100 angstroms.
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| WO2014026549A1 (en) * | 2012-08-13 | 2014-02-20 | 无锡华润上华科技有限公司 | Chemical mechanical polishing method for shallow trench isolation structure |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |