CN113671339A - Apparatus and method for verifying probe abnormality and contact abnormality and wafer testing method - Google Patents
Apparatus and method for verifying probe abnormality and contact abnormality and wafer testing method Download PDFInfo
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- CN113671339A CN113671339A CN202111109029.XA CN202111109029A CN113671339A CN 113671339 A CN113671339 A CN 113671339A CN 202111109029 A CN202111109029 A CN 202111109029A CN 113671339 A CN113671339 A CN 113671339A
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- 238000012360 testing method Methods 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 55
- 230000005856 abnormality Effects 0.000 title claims description 37
- 238000010998 test method Methods 0.000 claims abstract description 5
- 230000002159 abnormal effect Effects 0.000 claims description 10
- 235000012431 wafers Nutrition 0.000 description 26
- 238000001514 detection method Methods 0.000 description 3
- 238000004832 voltammetry Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Abstract
The invention provides a device and a method for verifying probe abnormity and contact abnormity and a wafer test method, wherein the device comprises: the device comprises a first pad area and a second pad area, wherein the first pad area and the second pad area both comprise a plurality of pads, the pads of the first pad area are communicated, the pads of the second pad area are arranged in a disconnected mode, and the pads of the first pad area and the pads of the second pad area are disconnected; and the first resistor and the second resistor have the same resistance value, two adjacent pads in the first pad area are communicated through the first resistor, one of the two adjacent pads is connected with the second resistor, and the other pads in the first pad area are connected with the second resistor. Whether the contact between the probe and the pad is good or not is tested, whether the probe is short-circuited or not is detected, and the problems of contact abnormity of the probe and short-circuiting of the probe can be detected in real time, so that the wafer testing efficiency and accuracy are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a device and a method for verifying probe abnormity and contact abnormity and a wafer testing method.
Background
In the field of semiconductor testing, a probe card is mostly used for wafer testing, before testing, Alignment (Alignment) is performed on a wafer, a PAD (PAD) is pricked according to a set prick depth value (Over Drive), then the prick condition is checked through Contact Check (Contact Check), and at the moment, the Contact condition of the probe can be judged only through the needle mark morphology under a microscope.
Particularly in reliability tests of wafers including room temperature tests and high temperature tests, the wafer may swell during the high temperature tests, making the probe contacts more difficult to control. The inaccuracy of probe contact has a great impact on wafer testing efficiency. In addition, the probe card belongs to consumable materials, is generally used according to the use time recommended by a supplier, is not used for monitoring the use condition, but can also have short circuit and the like, and can influence the test accuracy.
In summary, the rough method for inspecting the contact of the probe cannot meet the current wafer test requirements, and it is very necessary to quantitatively and real-timely monitor the contact condition of the probe card and the use condition of the probe card.
Disclosure of Invention
The invention aims to provide a device and a method for verifying probe abnormity and contact abnormity and a wafer test method, which can detect the problems of contact abnormity of a probe and whether the probe is short-circuited in real time, so that the wafer test is more accurate and the test efficiency is higher.
In order to achieve the above object, the present invention provides an apparatus for verifying probe abnormality and contact abnormality for testing whether a plurality of probes are short-circuited and whether a contact resistance of a test probe pad is abnormal, comprising:
the device comprises a first pad area and a second pad area, wherein the first pad area and the second pad area both comprise a plurality of pads, the pads of the first pad area are communicated, the pads of the second pad area are disconnected, and the pads of the first pad area and the pads of the second pad area are disconnected; and
the circuit comprises a first resistor and a second resistor which have the same resistance value, wherein two adjacent pads in the first pad area are communicated through the first resistor, one of the two adjacent pads is connected with the second resistor, and the other pads in the first pad area are connected with the second resistor.
Optionally, in the apparatus for verifying probe abnormality and contact abnormality, the plurality of pads of the first pad area and the plurality of pads of the second pad area form a shape of one row and a plurality of columns.
Optionally, in the apparatus for verifying probe abnormality and contact abnormality, the first pad area includes a first pad, a second pad, a third pad, a fourth pad and a fifth pad, and the first pad, the second pad, the third pad, the fourth pad and the fifth pad are sequentially arranged in a line.
Optionally, in the apparatus for verifying probe abnormality and contact abnormality, one end of the first resistor is connected to the first pad, the other end of the first resistor is connected to the second pad, one end of the second resistor is connected to the second pad and the third pad, and the other end of the second resistor is connected to the fourth pad and the fifth pad.
Optionally, in the device for verifying probe abnormality and contact abnormality, the first resistance and the second resistance are both 5 Ω to 10 Ω.
The invention also provides a method for verifying probe abnormity and contact abnormity, which comprises the following steps:
and testing the contact resistance of the probe by using the first pad area, and testing whether the probe is short-circuited by using the second pad area.
Optionally, in the method for verifying the probe abnormality and the contact abnormality, the method for testing the contact resistance of the probe by using the first pad area includes:
the method of measuring the resistance by adopting a two-end method is adopted, two probes are respectively communicated with a first pad and a second pad, and the resistance value between the first pad and the second pad is measured and recorded as a first resistance value;
adopting a four-end method to test the resistor, respectively communicating two probes with a second pad and a fifth pad, and testing the resistance value between the second pad and the fifth pad, and marking as a second resistance value;
judging whether the difference value of the first resistance value and the second resistance value is smaller than a first set value or not;
if yes, the contact resistance of the probe is normal;
if not, the contact resistance of at least one probe is abnormal.
Optionally, in the method for verifying the probe abnormality and the contact abnormality, the first set value is 1 Ω.
Optionally, in the method for verifying probe abnormality and contact abnormality, the method for testing whether the probe is short-circuited using the second pad area includes:
communicating a plurality of the probes with the pads of the second pad area, respectively;
testing the resistance value between any two pads;
and if the resistance value between the two pads is smaller than a second set value, judging that the two probes corresponding to the two pads are in short circuit.
The invention also provides a wafer testing method, which comprises the following steps:
s11: dividing the wafer into a plurality of test areas;
s12: verifying whether the probe has an abnormality and/or whether the probe has an abnormality in contact with the test area by using a method for verifying the abnormality of the probe and the abnormality in contact;
s13: if so, repairing the probe card, and if not, testing the test area;
s14: and testing the next test area, and repeating the steps S12-S13 until all the test areas are tested.
In the device and the method for verifying the probe abnormity and the contact abnormity and the wafer test method provided by the invention, whether the contact between the probe and the pad is good or not is firstly tested, whether the probe is short-circuited or not is then detected, the reliability or the yield of a plurality of test areas of the wafer is tested under the condition of ensuring the good contact and the non-short circuit, and the device and the method can be used for verifying the probe before testing the test areas each time, so that the problems of the contact abnormity of the probe and the short circuit of the probe can be detected in real time, the wafer test efficiency is improved, and the wafer test accuracy is improved.
Drawings
FIG. 1 is a schematic view of an apparatus for verifying probe anomalies and contact anomalies according to an embodiment of the present invention;
FIG. 2 is a flow chart of a wafer testing method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the division of a wafer test area according to an embodiment of the present invention;
in the figure: 110-a first pad area, 111-a first pad, 112-a second pad, 113-a third pad, 114-a fourth pad, 115-a fifth pad, 120-a second pad area, 121-a sixth pad, 122-a seventh pad, 211-a test area.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 1, the present invention provides a device for verifying probe abnormality and contact abnormality, which is used for testing whether a plurality of probes of a probe are short-circuited and testing whether contact resistance of the probe is abnormal, and comprises:
a first pad area 110 and a second pad area 120, wherein the first pad area 110 and the second pad area 120 each include a plurality of pads, the pads of the first pad area 110 are connected with each other, the pads of the second pad area are disconnected with each other, and the pads of the first pad area 110 and the pads of the second pad area 120 are disconnected with each other; and
a first resistor R1 and a second resistor R2 with the same resistance value, wherein two adjacent pads in the first pad area 110 are communicated through the first resistor R1, and one of the pads is communicated with the rest of the pads through the second resistor R2, namely, one of the two adjacent pads is connected with the second resistor, and the rest of the pads in the first pad area are connected with the second resistor.
Preferably, the plurality of pads of the first pad area and the plurality of pads of the second pad area form a shape of one row and a plurality of columns. As an example, the first pad area includes 5 pads, which are a first pad111, a second pad112, a third pad, a fourth pad114, and a fifth pad115, and the first pad111, the second pad112, the third pad, the fourth pad114, and the fifth pad115 are sequentially arranged in a row. The second area includes two pads, which are a sixth pad and a seventh pad, respectively, and the sixth pad and the seventh pad are also located in the same row, and are also located in the same row as the first pad111, the second pad112, the third pad113, the fourth pad114, and the fifth pad 115.
Further, the two resistors are a first resistor R1 and a second resistor R2, respectively, one end of the first resistor R1 is connected to the first pad111, the other end of the first resistor R1 is connected to the second pad112, one end of the second resistor R2 is connected to the second pad112 and the third pad113, and the other end of the second resistor R2 is connected to the fourth pad114 and the fifth pad 115. The connection mode of the first pad111, the second pad112 and the first resistor R1 is set by adopting a method for testing the resistor by using a two-end method, and the method for testing the resistor by using the two-end method is also called voltammetry; the connection mode of the second resistor R2, the second pad112, the third pad113, the fourth pad114 and the fifth pad115 is set by adopting a method for testing the resistor by adopting a four-terminal method, and the method for testing the resistor by adopting the four-terminal method is also called a Kelvin four-wire detection method.
Furthermore, the first resistor R1 and the second resistor R2 are both 5 Ω -10 Ω. The resistance values of the first resistor R1 and the second resistor R2 can be set according to the contact resistance of the probe, and the contact resistance of a common probe is less than 1 omega, so the resistance values of the first resistor R1 and the second resistor R2 are selected within 5 omega-10 omega.
The method for communicating the probe and the pad in the embodiment of the invention can be a method for pricking the probe on the pad, and the pricking depth can be determined before verification. For example, the contact resistance values of the probes under different OD values are collected, the OD value ranges from 15um to 50um, the OD value when the resistance value is the smallest is taken as the common OD value, wherein the OD value is the depth of being stuck on the pad, and the common OD value can be taken as the depth of being stuck on the pad when the test probe is abnormal according to the embodiment of the present invention.
The invention also provides a method for verifying probe abnormity and contact abnormity, which comprises the following steps:
the first pad111 area is used for testing the contact resistance of the probe, and the second pad112 area is used for testing whether the probe is short-circuited.
Further, the method for testing the contact resistance of the probe by using the first pad111 area comprises the following steps:
adopting a method (voltammetry) for testing a resistor by using a two-end method, respectively communicating the two probes with the first pad111 and the second pad112, and testing a resistance value between the first pad111 and the second pad112, and marking the resistance value as a first resistance value;
adopting a four-terminal method (kelvin four-wire detection method) to test the resistance, communicating the two probes with the second pad112 and the fifth pad115 respectively, and testing the resistance between the second pad112 and the fifth pad115, and marking as a second resistance;
judging whether the difference value of the first resistance value and the second resistance value is smaller than a first set value or not;
if yes, the contact resistance of the probe is normal;
if not, the contact resistance of at least one probe is abnormal.
Further, the first set value is 1 Ω. Specifically, the value obtained by subtracting the second resistance value from the first resistance value is actually the resistance value of the contact resistor of the probe, and whether the contact is normal can be determined by determining whether the resistance value of the contact resistor is smaller than 1 Ω. That is to say, the method for testing the first resistor adopts a method for testing the resistor by a two-terminal method, namely, a voltammetry method, and more specifically, two probes are respectively communicated with the first pad111 and the second pad112, and a resistance value between the first pad111 and the second pad112 is tested and recorded as a first resistance value. The method for testing the second resistor adopts a method for testing the resistor by a four-terminal method, namely a kelvin four-wire detection method, and more specifically, two probes are respectively communicated with the second pad112 and the fifth pad115, and the resistance value between the second pad112 and the fifth pad115 is tested and is marked as a second resistance value.
Further, the method for testing whether the probe is short-circuited by using the second pad112 area includes:
communicating a plurality of said probes with the pads of said second pad112 region, respectively;
testing the resistance value between any two pads;
and if the resistance value between the two pads is smaller than a second set value which is infinite, judging that the two probes corresponding to the two pads are in short circuit. Specifically, the number of pads in the second pad112 area is at least two, that is, how many pads can be set by the probe, the probes correspond to one pad one by one, the probes are pricked on the pads, and the resistance between any two pads is tested. More specifically, two pads and two probes may be exemplified, for example, the two probes are a first probe and a second probe, the two pads are a sixth pad121 and a seventh pad122, the first probe is stuck on the sixth pad121, the second probe is stuck on the seventh pad122, whether the first probe and the second probe are short-circuited can be determined by testing the resistance between the sixth pad121 and the seventh pad122 and determining whether the resistance is infinite, and if the resistance between the sixth pad121 and the seventh pad122 is not infinite, it is determined that the short-circuit between the first probe and the second probe is abnormal.
Referring to fig. 2, the present invention further provides a wafer testing method, including:
s11: dividing the wafer into a plurality of test areas 211, as shown in fig. 3;
s12: starting a test, and verifying whether the probe has an abnormality and/or whether the probe contacts the test area by using a method for verifying the abnormality and the contact abnormality of the probe;
s13: if the probe is abnormal and/or the contact of the probe is abnormal, stopping the test, repairing the probe card, and if not, testing the test area;
s14: and testing the next test area, and repeating the steps S12-S13 until all the test areas are tested. The test on the wafer may be a reliability test or a yield test, and in other embodiments of the present invention, the test may also be a test on other aspects of the wafer.
In summary, in the apparatus and method for verifying probe anomalies and contact anomalies and the wafer testing method provided in the embodiments of the present invention, by the apparatus and method of the present invention, it is first tested whether the contact between the probe and the pad is good, and then it is detected whether the probe is short-circuited, under the condition that good contact and no short-circuit are ensured, reliability or yield of a plurality of test areas of the wafer is tested, and before testing the test areas each time, the apparatus and method of the present invention are used to verify the probe, so that the problems of probe contact anomalies and probe short-circuits can be detected in real time, thereby improving the efficiency of testing the wafer and improving the accuracy of wafer testing.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An apparatus for verifying abnormality of probes and contact abnormality for testing whether a plurality of probes are short-circuited and whether contact resistance of a probe pad is abnormal, comprising:
the device comprises a first pad area and a second pad area, wherein the first pad area and the second pad area both comprise a plurality of pads, the pads of the first pad area are communicated, the pads of the second pad area are disconnected, and the pads of the first pad area and the pads of the second pad area are disconnected; and
the circuit comprises a first resistor and a second resistor which have the same resistance value, wherein two adjacent pads in the first pad area are communicated through the first resistor, one of the two adjacent pads is connected with the second resistor, and the other pads in the first pad area are connected with the second resistor.
2. The apparatus for validating probe anomalies and contact anomalies as defined in claim 1, wherein the plurality of pads of the first pad zone and the plurality of pads of the second pad zone constitute a row and column shape.
3. The apparatus for verifying probe anomalies and contact anomalies according to claim 1, wherein the first pad area includes a first pad, a second pad, a third pad, a fourth pad, and a fifth pad, the first pad, the second pad, the third pad, the fourth pad, and the fifth pad being sequentially arranged in a row.
4. The apparatus for verifying probe abnormality and contact abnormality according to claim 3, wherein one end of the first resistor is connected to the first pad, the other end thereof is connected to the second pad, one end of the second resistor is connected to the second pad and the third pad, and the other end thereof is connected to the fourth pad and the fifth pad.
5. The apparatus for verifying probe anomalies and contact anomalies as set forth in claim 4, wherein the first resistance and the second resistance are each 5 Ω to 10 Ω.
6. A method of verifying probe anomalies and contact anomalies using the apparatus for verifying probe anomalies and contact anomalies of any one of claims 1-5, comprising:
and testing the contact resistance of the probe by using the first pad area, and testing whether the probe is short-circuited by using the second pad area.
7. The method of verifying probe anomalies and contact anomalies as set forth in claim 6, wherein the method of testing contact resistance of a probe using the first pad area includes:
the method of measuring the resistance by adopting a two-end method is adopted, two probes are respectively communicated with a first pad and a second pad, and the resistance value between the first pad and the second pad is measured and recorded as a first resistance value;
adopting a four-end method to test the resistor, respectively communicating two probes with a second pad and a fifth pad, and testing the resistance value between the second pad and the fifth pad, and marking as a second resistance value;
judging whether the difference value of the first resistance value and the second resistance value is smaller than a first set value or not;
if yes, the contact resistance of the probe is normal;
if not, the contact resistance of at least one probe is abnormal.
8. The method of validating probe anomalies and contact anomalies as defined in claim 7, wherein the first set point is 1 Ω.
9. The method of validating probe anomalies and contact anomalies as defined in claim 6, wherein the method of testing whether the probe is shorted using the second pad area includes:
communicating a plurality of the probes with the pads of the second pad area, respectively;
testing the resistance value between any two pads;
and if the resistance value between the two pads is smaller than a second set value, judging that the two probes corresponding to the two pads are in short circuit.
10. A wafer testing method, comprising:
s11: dividing the wafer into a plurality of test areas;
s12: verifying whether the probe has an abnormality and/or whether the probe has an abnormality in contact with a test area by using the method for verifying abnormality and contact abnormality of the probe according to any one of claims 6 to 9;
s13: if so, repairing the probe card, and if not, testing the test area;
s14: and testing the next test area, and repeating the steps S12-S13 until all the test areas are tested.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115015817A (en) * | 2022-05-20 | 2022-09-06 | 丹东富田精工机械有限公司 | Device and method for detecting probe state abnormity and contact abnormity on line |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2137813Y (en) * | 1992-07-02 | 1993-07-07 | 施大申 | High resistance resistor with four or three terminal |
| JP2001311743A (en) * | 2000-04-28 | 2001-11-09 | Hioki Ee Corp | Contact probe and circuit board inspection device |
| CN1482468A (en) * | 2002-09-13 | 2004-03-17 | 中芯国际集成电路制造（上海）有限公 | Structure and method for testing contact resistance of detecting probe |
| US7030633B1 (en) * | 2004-12-03 | 2006-04-18 | Chunong Qiu | Four-terminal methods for resistivity measurement of semiconducting materials |
| CN101275994A (en) * | 2007-03-27 | 2008-10-01 | 和舰科技(苏州)有限公司 | Method for monitoring probe card state |
| CN102004187A (en) * | 2010-09-21 | 2011-04-06 | 江苏大学 | Method for measuring super-small DC resistance by series-wound additional resistance difference value method |
| CN102062847A (en) * | 2010-11-08 | 2011-05-18 | 上海集成电路研发中心有限公司 | Method for detecting semiconductor parameter measurement system |
| JP2012013590A (en) * | 2010-07-02 | 2012-01-19 | Hioki Ee Corp | Measurement device and substrate inspection apparatus |
| CN204102893U (en) * | 2014-10-17 | 2015-01-14 | 中芯国际集成电路制造(北京)有限公司 | A kind of semi-conductor test structure |
| US20150137849A1 (en) * | 2013-11-19 | 2015-05-21 | Shinko Electric Industries Co., Ltd. | Probe card and method for manufacturing probe card |
| CN205720446U (en) * | 2016-06-03 | 2016-11-23 | 中芯国际集成电路制造（天津）有限公司 | The test structure of contact resistance and the test structure of device resistance |
| JP2017026407A (en) * | 2015-07-21 | 2017-02-02 | 日置電機株式会社 | Circuit board inspection device, and contact check method |
| CN110794332A (en) * | 2019-11-14 | 2020-02-14 | 浙江晨泰科技股份有限公司 | Residual current transformer detection system for fire detection detector and detection method thereof |
| CN111025016A (en) * | 2019-12-18 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Resistance testing method of Kelvin structure |
| US20200233033A1 (en) * | 2019-01-17 | 2020-07-23 | Intel Corporation | Test probe for wafer-level and panel-level testing |
-
2021
- 2021-09-22 CN CN202111109029.XA patent/CN113671339B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2137813Y (en) * | 1992-07-02 | 1993-07-07 | 施大申 | High resistance resistor with four or three terminal |
| JP2001311743A (en) * | 2000-04-28 | 2001-11-09 | Hioki Ee Corp | Contact probe and circuit board inspection device |
| CN1482468A (en) * | 2002-09-13 | 2004-03-17 | 中芯国际集成电路制造（上海）有限公 | Structure and method for testing contact resistance of detecting probe |
| US7030633B1 (en) * | 2004-12-03 | 2006-04-18 | Chunong Qiu | Four-terminal methods for resistivity measurement of semiconducting materials |
| CN101275994A (en) * | 2007-03-27 | 2008-10-01 | 和舰科技(苏州)有限公司 | Method for monitoring probe card state |
| JP2012013590A (en) * | 2010-07-02 | 2012-01-19 | Hioki Ee Corp | Measurement device and substrate inspection apparatus |
| CN102004187A (en) * | 2010-09-21 | 2011-04-06 | 江苏大学 | Method for measuring super-small DC resistance by series-wound additional resistance difference value method |
| CN102062847A (en) * | 2010-11-08 | 2011-05-18 | 上海集成电路研发中心有限公司 | Method for detecting semiconductor parameter measurement system |
| US20150137849A1 (en) * | 2013-11-19 | 2015-05-21 | Shinko Electric Industries Co., Ltd. | Probe card and method for manufacturing probe card |
| CN204102893U (en) * | 2014-10-17 | 2015-01-14 | 中芯国际集成电路制造(北京)有限公司 | A kind of semi-conductor test structure |
| JP2017026407A (en) * | 2015-07-21 | 2017-02-02 | 日置電機株式会社 | Circuit board inspection device, and contact check method |
| CN205720446U (en) * | 2016-06-03 | 2016-11-23 | 中芯国际集成电路制造（天津）有限公司 | The test structure of contact resistance and the test structure of device resistance |
| US20200233033A1 (en) * | 2019-01-17 | 2020-07-23 | Intel Corporation | Test probe for wafer-level and panel-level testing |
| CN110794332A (en) * | 2019-11-14 | 2020-02-14 | 浙江晨泰科技股份有限公司 | Residual current transformer detection system for fire detection detector and detection method thereof |
| CN111025016A (en) * | 2019-12-18 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Resistance testing method of Kelvin structure |
Non-Patent Citations (1)
| Title |
|---|
| （美）迪特尔·K.施罗德: "半导体材料与器件表征", vol. 2014, 西安交通大学出版社, pages: 47 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115015817A (en) * | 2022-05-20 | 2022-09-06 | 丹东富田精工机械有限公司 | Device and method for detecting probe state abnormity and contact abnormity on line |
| CN115015817B (en) * | 2022-05-20 | 2023-08-11 | 丹东富田精工机械有限公司 | Device and method for detecting abnormal state and abnormal contact of probe on line |
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