CN1136656C - Electronic analog swtich - Google Patents
Electronic analog swtich Download PDFInfo
- Publication number
- CN1136656C CN1136656C CNB988073315A CN98807331A CN1136656C CN 1136656 C CN1136656 C CN 1136656C CN B988073315 A CNB988073315 A CN B988073315A CN 98807331 A CN98807331 A CN 98807331A CN 1136656 C CN1136656 C CN 1136656C
- Authority
- CN
- China
- Prior art keywords
- transistor
- trap
- mos transistor
- conducting channel
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Abstract
An analogue switch formed on a semiconductor substrate comprises input and output ports (204, 205), and a first enhancement mode MOS transistor (201) formed in an isolated well in the substrate material and having its gate (G) connected to receive a control signal (207), and having one end (S) of its conducting channel and its well (W) connected to the input port (204). A second enhancement mode MOS transistor (202) is formed in an isolated well in the substrate, and has one end (S) of its conducting channel and its well (W) connected to the input port (204), and has its gate (G) connected to the other end (D) of the conducting channel of the first transistor (201). A third enhancement mode MOS transistor (203) is formed in an isolated well in the substrate, and has its gate (G) connected to receive the complement (208) of the said control signal, and has its conducting channel (D, S) connected between the output port (205) and the other end (D) of the conducting channel of the second transistor (202), and has its well (W) connected to one of the supply lines (OV) of the switch. Control means (210) are connected to the gate (G) of the second transistor (202) for maintaining the second transistor (202) in an opposite state to that of the first transistor (201).
Description
Technical field
The present invention relates to electronic analog swtich, relate in particular to the analog switch that uses MOS transistor.
Background technology
Comprise that the transistorized analog switch of metal-oxide semiconductor (MOS) (MOS) has generally included p-raceway groove and n-channel MOS transistor.The n-channel transistor has the body that is connected to the device negative power line usually.But when the source electrode of nmos device was more negative than negative supply, the source electrode of nmos device and the PN junction diode between the body were with forward bias.Electric current just flows into the node that connects analog switch from negative supply like this.This electric current flow impairment the high resistance break that closes of switch of expectation.
For example, Horowitz and Hill describe and show the typical C mos transistor switch in 142 and 143 pages of last Fig. 3 .36 of 2nd Ed.Cambridge University Press " electronic technology (The Art of Electronics) ".PMOS transistor AND gate nmos pass transistor is connected in parallel, the opposite control signal of described transistor receive logic.This layout is used for guaranteeing that the conducting resistance of switch is enough low.But, as mentioned above, when input drops to 0v when following,, therefore damaged the pass resistance break because this landing causes the forward bias of PN junction in the nmos pass transistor.
The international patent application that publication number is WO97/24807 discloses a kind of analog switch, and described analog switch comprises two MOS transistor; First transistor is connected between input port and second transistor gate.The first transistor serves as comparator, and conducting when the voltage beyond the normal range (NR) is added in the input.
Summary of the invention
The present invention seeks to when switch is in off-state, to improve the maximum permission operating voltage of analog switch.
According to the present invention, a kind of analog switch that is formed on the Semiconductor substrate is provided, comprising: first and second power ports, be respectively applied for and be connected to first and second power lines, first power line with respect to the second source line for just; Input port and output port; First reinforcing MOS transistor is formed in the isolation well of backing material, and its grid is connected to receive control signal, and an end of its conducting channel and trap thereof connect input port; Second reinforcing MOS transistor is formed in the isolation well in the substrate, and an end of its conducting channel and trap thereof connect input port, and its grid connects the other end of the first transistor conducting channel; The 3rd reinforcing MOS transistor, be formed in the isolation well in the substrate, its grid is connected to receive the complement code signal of described control signal, the two ends of its conducting channel are connected between the other end of output port and transistor seconds conducting channel, and its trap connects first or second source port of switch; And control device, be connected to the grid of transistor seconds, be used to keep transistor seconds and the first transistor to be in inverse state, control device comprises reinforcing MOS transistor, the grid of this enhancement transistor is connected to receive control signal, and the two ends of the conducting channel of this enhancement transistor are connected between the grid of a described power port and transistor seconds.
In above-mentioned switch, the conducting channel material type of each MOS transistor is identical with substrate, and is formed in the trap with the semi-conducting material of backing material type opposite.
Wherein, backing material is a n-N-type semiconductor N material, and trap material is a p-N-type semiconductor N material, and transistor is a nmos pass transistor, and the 3rd transistorized trap connects the second source port of switch.
Perhaps wherein, backing material is a p-N-type semiconductor N material, and trap material is a n-N-type semiconductor N material, and transistor is the PMOS transistor, and the 3rd transistorized trap connects first power port of switch.
Each transistor is formed in the groove that the oxide material of electric insulation isolates.
Wherein, each MOS transistor is a nmos device, and the trap of the 3rd MOS transistor connects the second source port of switch.Perhaps each MOS transistor is the PMOS device, and the trap of the 3rd MOS transistor connects first power port of switch.
In above-mentioned switch, described control device comprises the device that is used to make the second MOS transistor conducting.Wherein, described enhancement transistor is the PMOS transistor, and described transistorized conducting channel is connected to first power port of switch.Perhaps, described enhancement transistor is a nmos pass transistor, and described transistorized conducting channel is connected to the second source port of switch.
Described control device can comprise switch resistance.
Description of drawings
Fig. 1 shows the circuit diagram of conventional simulation switch;
Fig. 2 shows the overall circuit figure of first embodiment of the invention;
Fig. 3 shows the modification of Fig. 2 embodiment;
Fig. 4 shows the circuit diagram of Fig. 3 embodiment modification; And
Fig. 5 schematically shows the mos transistor structure that uses in embodiments of the present invention.
Embodiment
The simulation mos transistor switch 100 of routine shown in Figure 1 comprises nmos pass transistor 101 and PMOS transistor 102.Switch has input port 104 and output port 105.When switch is in on-state, is connected to input port 104 by the signal of switch, and sends to output port 105.The grid G connection control signal input 107 of nmos pass transistor 101, the grid G connection control signal input 108 of PMOS transistor 102.
The negative power line of nmos pass transistor body connection device, the PMOS transistor body connects positive power line simultaneously.In example shown in Figure 1, these power lines are respectively 0v and 5v.
When control input 107 for low (being 0v) and control input 108 during for high (being 5v), switch is an off-state, so do not carry electric current between input and output port 104 and 105.
But if the signal at input port 104 places drops to voltage (0v) that the nmos pass transistor substrate connected when following, the PN junction diode that then forms between the body of nmos pass transistor 101 and the source electrode becomes forward bias.Like this, electric current can flow into the input node from negative supply.The flow impairment of this electric current the high resistance break that closes of switch of expectation.
Fig. 2 shows the first embodiment of the present invention 200, and it comprises first, second and the 3rd nmos pass transistor 201,202 and 203.The grid G of first nmos pass transistor 201 connects control input 207.The source S of first MOS transistor and trap W are connected to the input port 204 of device.Therefore transistor 201 is with enhancement mode work.
The second and the 3rd MOS transistor 202 and 203 is connected with its conducting channel of connecting between device input port 204 and output port 205.That is, the source S of transistor 202 connects input port, and the drain D of transistor 202 connects the source S of transistor 203, and the drain electrode mouth of transistor 203 connects output port 205.The grid G of second MOS transistor 202 connects the drain D and the control device 210 of first MOS transistor 201.
The grid G of the 3rd transistor 203 connects the second control input, 208, the second control inputs 208 and receives the complement code signal that is added to the signal in the first control input 207, and the trap W of this device connects the negative power line of switch.
In order to make switch be in off-state, height (5V) control signal is added to control input 207, low (0V) control signal is added to control signal 208.High control signal makes transistor 201 conductings, causes the grid G of transistor 202 to be pulled down to the voltage level of input port 204.Like this, the gate source voltage Vgs of transistor 202 is maintained at 0v, guarantees that transistor 202 remains on cut-off state.
The grid G of the 3rd transistor 203 remains on 0v under this cut-off state, guarantee that the 3rd transistor 203 also remains on cut-off state.
In order to connect switch, in control input 207, add low (0v) signal, in control input 208, increase (5v) signal.These signals end the first transistor 201, thereby allow device 210 that transistor seconds is changed to conducting.The 3rd transistor also is changed to conducting, so switch is in on-state.
Different with aforementioned circuit shown in Figure 1, even the voltage in the control input 204 is lower than the threshold voltage of negative supply voltage up to transistor 201, transistor 201 and 202 source electrode and the PN junction between the body keep not offset under cut-off state.As a result, leakage current can not flow between the input and output port 204 and 205 of switch.
Like this, the cut-off state negative voltage range that is added on the input port 204 is greatly improved in the aforementioned circuit design.Possible maximum negative voltage is then mainly based on the reverse breakdown voltage of back-biased PN junction between each transistorized trap W and the drain D, and is subjected to the restriction of transistor 201 threshold values.
Only show nmos device although be appreciated that Fig. 2, the transistor that embodies circuit of the present invention can be the PMOS device.
Fig. 3 shows the modification of Fig. 2 circuit, and wherein device 210 is made of PMOS transistor 211.Inverter 212 is connected between the grid of control input the 207 and the 3rd transistor 203, so that be added to the complement code signal of importing the control signal on 207 for transistor provides.
In addition, the 2nd PMOS transistor 213 and the second and the 3rd nmos pass transistor 202 and 203 are connected in parallel, and are connected to receive control signal 214.Custom circuit as shown in Figure 1, PMOS transistor 213 is used to reduce the conducting resistance of switch, and connects switch by low input control signal.
Fig. 3 circuit has whole advantages of Fig. 2 circuit, especially compares with prior art equipment, and the maximum negative voltage that input port 204 allows when switch is in open position is improved.
Fig. 4 shows the improvement figure of Fig. 3 design, wherein comprises additional diode 215 between the source S of first nmos pass transistor 201 and input port 204 and trap W are connected.
In this design, the grid source threshold voltage vt of second MOS transistor 202 must make that it can keep transistor 202 to be in cut-off state when transistor 201 conductings greater than the forward voltage drop of diode.
Being appreciated that the description of the embodiment of the invention specifically with reference to the MOS transistor of particular type, also is easy but replace described transistor with the MOS transistor of opposite types.
For example, the 3rd MOS transistor can be the PMOS transistor, in this case, and the positive power line of this transistorized trap interface unit.
Replacing each transistor in the described circuit with a plurality of parallel connections or series connection device also is to understand easily.
Perhaps, the second and/or the 3rd transistor can be replaced by a plurality of devices, and the raceway groove of these devices is one another in series and connects and grid is public.The trap that connects these series connection devices is public each other.
First MOS transistor can be replaced by a plurality of devices, and the raceway groove of these devices is connected in series and grid is public.Trap can be public and be connected to input port, also can be connected near the trap of the raceway groove end of input port with each and separate.
Fig. 2, the 3 and 4 described embodiment of the invention can effectively be utilized the trench isolations characteristic.
In trench isolations, the MOS device can be placed in the groove of the resistive isolation that separates.Fig. 5 shows the schematic diagram of a this MOS device.
Form device on substrate 50, its trap 52 is isolated by oxide layer 51 and backing material.Backing material is p-type or n-type, and trap material also can be wherein a kind of material type (the n-type is used for the PMOS transistor, and the p-type is used for nmos pass transistor).Between connecting 54 and 55, the drain electrode of device and source electrode form conducting channel 53.Control conducting in a usual manner with gate terminal 56.
Perhaps, make MOS transistor and backing material " knot is isolated " by the trap that forms the semi-conducting material opposite with the substrate semiconductor material type.
Claims (11)
1. analog switch that is formed on the Semiconductor substrate (50) comprises:
First and second power ports are respectively applied for and are connected to first and second power lines, first power line with respect to the second source line for just;
Input port (204) and output port (205);
First reinforcing MOS transistor (201) is formed in the isolation well of backing material, and its grid (G) is connected to receive control signal (207), and an end (S) of its conducting channel and trap thereof connect input port (204);
Second reinforcing MOS transistor (202) is formed in the isolation well in the substrate (50), and an end (S) of its conducting channel and trap thereof connect input port (204), and its grid (G) connects the other end (D) of the first transistor (201) conducting channel;
The 3rd reinforcing MOS transistor (203), be formed in the isolation well in the substrate (50), its grid (G) is connected to receive the complement code signal (208) of described control signal, the two ends of its conducting channel are connected between the other end (D) of output port (205) and transistor seconds (202) conducting channel, and its trap connects first or second source port of switch; And
Control device (210), be connected to the grid (G) of transistor seconds (202), be used to keep transistor seconds (202) and the first transistor (201) to be in inverse state, control device comprises reinforcing MOS transistor (211), the grid (G) of this enhancement transistor (211) is connected to receive control signal, and the two ends of the conducting channel of this enhancement transistor (211) are connected between the grid of a described power port and transistor seconds (202).
2. analog switch according to claim 1, wherein, the conducting channel material type of each MOS transistor (201,202,203) is identical with substrate (50), and is formed in the trap with the semi-conducting material of backing material type opposite.
3. analog switch according to claim 2, wherein, backing material (50) is a n-N-type semiconductor N material, and trap material is a p-N-type semiconductor N material, and transistor (201,202,203) is a nmos pass transistor, and the 3rd transistorized trap connects the second source port of switch.
4. analog switch according to claim 2, wherein, backing material (50) is a p-N-type semiconductor N material, trap material is a n-N-type semiconductor N material, transistor (201,202,203) be the PMOS transistor, the trap (W) of the 3rd transistor (203) connects first power port of switch.
5. analog switch according to claim 1, wherein, each transistor (201,202,203) is formed in the groove that the oxide material of electric insulation isolates.
6. analog switch according to claim 5, wherein, each MOS transistor (201,202,203) is a nmos device, the trap of the 3rd MOS transistor (W) connects the second source port of switch.
7. analog switch according to claim 5, wherein, each MOS transistor (201,202,203) is the PMOS device, the trap (W) of the 3rd MOS transistor (203) connects first power port of switch.
8. according to each described analog switch among the claim 1-7, wherein, described control device (210) comprises the device that is used to make the second MOS transistor conducting.
9. analog switch according to claim 1 and 2, wherein, described enhancement transistor is the PMOS transistor, described transistorized conducting channel is connected to first power port of switch.
10. analog switch according to claim 1 and 2, wherein, described enhancement transistor is a nmos pass transistor, described transistorized conducting channel is connected to the second source port of switch.
11. analog switch according to claim 1 and 2, wherein, described control device (210) comprises switch resistance.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9714986.8 | 1997-07-16 | ||
| GB9714986A GB2327544B (en) | 1997-07-16 | 1997-07-16 | Electronic analogue switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1264508A CN1264508A (en) | 2000-08-23 |
| CN1136656C true CN1136656C (en) | 2004-01-28 |
Family
ID=10815949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB988073315A Expired - Fee Related CN1136656C (en) | 1997-07-16 | 1998-07-13 | Electronic analog swtich |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US6046622A (en) |
| EP (1) | EP0995269B1 (en) |
| JP (1) | JP4149129B2 (en) |
| KR (1) | KR20010015560A (en) |
| CN (1) | CN1136656C (en) |
| AU (1) | AU8542298A (en) |
| CA (1) | CA2296403A1 (en) |
| DE (1) | DE69803073T2 (en) |
| ES (1) | ES2165692T3 (en) |
| GB (1) | GB2327544B (en) |
| HK (1) | HK1018135A1 (en) |
| WO (1) | WO1999004493A1 (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19934297C1 (en) | 1999-07-21 | 2000-10-05 | Siemens Ag | Semiconductor integrated circuit with NMOS transistors |
| US6404267B1 (en) * | 1999-07-21 | 2002-06-11 | Cooper Industries | High side MOSFET drive |
| EP1199801A1 (en) * | 2000-10-19 | 2002-04-24 | STMicroelectronics S.r.l. | Circuit for current injection control in analog switches |
| DE10133470C2 (en) * | 2001-07-10 | 2003-05-28 | Element One Multimedia Ohg | Device for moving a screen and a keyboard from a rest to a use position |
| TWI277290B (en) * | 2002-01-17 | 2007-03-21 | Semiconductor Energy Lab | Electric circuit |
| KR100485130B1 (en) * | 2002-10-17 | 2005-04-25 | 재단법인서울대학교산학협력재단 | Switching method of transistor and switching circuit using the same |
| CN100411304C (en) * | 2003-09-08 | 2008-08-13 | 通用电气公司 | Method and apparatus for high-voltage switching of ultrasound transducer array |
| JP3983220B2 (en) * | 2003-12-24 | 2007-09-26 | 沖電気工業株式会社 | Analog switch |
| ATE405990T1 (en) * | 2004-01-19 | 2008-09-15 | Nxp Bv | MOS SWITCHING NETWORK |
| EP1739834A1 (en) | 2005-06-29 | 2007-01-03 | Svenska Grindmatriser AB | An analogue switch, a switch system and a method for use therewith |
| KR100880378B1 (en) * | 2007-02-22 | 2009-01-23 | 삼성전자주식회사 | Transmission gate switch, system using its and data in/out method thereof |
| US8344789B2 (en) * | 2010-01-20 | 2013-01-01 | Intersil Americas Inc. | Analog switch with internal device body control |
| US9245886B2 (en) * | 2013-07-12 | 2016-01-26 | Xilinx, Inc. | Switch supporting voltages greater than supply |
| KR101901693B1 (en) * | 2013-12-27 | 2018-09-27 | 삼성전기 주식회사 | Switching circuit and high frequency switch including the same |
| CN111431514B (en) * | 2020-06-11 | 2020-09-29 | 深圳市鼎阳科技股份有限公司 | Broadband buffering analog switch circuit and integrated circuit |
| TWI774083B (en) * | 2020-10-13 | 2022-08-11 | 瑞昱半導體股份有限公司 | Switch circuit |
| CN113783563B (en) * | 2021-11-01 | 2022-06-28 | 成都市安比科技有限公司 | Negative voltage low leakage current switch circuit |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5813027A (en) * | 1981-07-17 | 1983-01-25 | Toshiba Corp | Analog switch device |
| JPS5813030A (en) * | 1981-07-17 | 1983-01-25 | Toshiba Corp | Analog switch device |
| EP0088291B1 (en) * | 1982-02-26 | 1985-07-10 | Kabushiki Kaisha Toshiba | Mos switch circuit |
| US4513212A (en) * | 1982-07-22 | 1985-04-23 | Electronics Pty. Ltd. | Automatic P-well clamping for CMOS integrated circuit |
| JPS6020394A (en) * | 1983-07-14 | 1985-02-01 | Ricoh Co Ltd | Power source switching circuit |
| JPS6154711A (en) * | 1984-08-27 | 1986-03-19 | Yokogawa Hokushin Electric Corp | Analog switch |
| US4857984A (en) * | 1984-12-26 | 1989-08-15 | Hughes Aircraft Company | Three-terminal MOS integrated circuit switch |
| JPS6398214A (en) * | 1986-10-15 | 1988-04-28 | Hitachi Ltd | Analog switch |
| JPH01157614A (en) * | 1987-12-14 | 1989-06-20 | Mitsubishi Electric Corp | Cmos analog switch for input/output switching |
| JPH01317022A (en) * | 1988-06-16 | 1989-12-21 | Toshiba Corp | Power supply switching circuit |
| JP2642465B2 (en) * | 1989-01-17 | 1997-08-20 | 株式会社東芝 | Analog signal input circuit |
| KR940009696B1 (en) * | 1991-10-08 | 1994-10-15 | 현대전자산업주식회사 | Hot carrier prevention circuit |
| JPH0746108A (en) * | 1993-07-28 | 1995-02-14 | Oki Electric Ind Co Ltd | Cmos analog switch |
| US5442218A (en) * | 1993-09-30 | 1995-08-15 | At&T Global Information Solutions Company | CMOS power fet driver including multiple power MOSFET transistors connected in parallel, each carrying an equivalent portion of the total driver current |
| US5666082A (en) * | 1995-12-29 | 1997-09-09 | Maxin Integrated Products, Inc. | Fault protection using parallel output CMOS devices for integrated circuit analog switches |
-
1997
- 1997-07-16 GB GB9714986A patent/GB2327544B/en not_active Revoked
-
1998
- 1998-07-09 US US09/112,523 patent/US6046622A/en not_active Expired - Lifetime
- 1998-07-13 KR KR1020007000070A patent/KR20010015560A/en not_active Application Discontinuation
- 1998-07-13 JP JP2000503601A patent/JP4149129B2/en not_active Expired - Fee Related
- 1998-07-13 ES ES98936420T patent/ES2165692T3/en not_active Expired - Lifetime
- 1998-07-13 AU AU85422/98A patent/AU8542298A/en not_active Abandoned
- 1998-07-13 EP EP98936420A patent/EP0995269B1/en not_active Expired - Lifetime
- 1998-07-13 DE DE69803073T patent/DE69803073T2/en not_active Expired - Lifetime
- 1998-07-13 CA CA002296403A patent/CA2296403A1/en not_active Abandoned
- 1998-07-13 CN CNB988073315A patent/CN1136656C/en not_active Expired - Fee Related
- 1998-07-13 WO PCT/EP1998/004352 patent/WO1999004493A1/en not_active Application Discontinuation
-
1999
- 1999-07-15 HK HK99103054A patent/HK1018135A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0995269B1 (en) | 2001-12-19 |
| US6046622A (en) | 2000-04-04 |
| GB9714986D0 (en) | 1997-09-24 |
| JP4149129B2 (en) | 2008-09-10 |
| ES2165692T3 (en) | 2002-03-16 |
| HK1018135A1 (en) | 1999-12-10 |
| DE69803073D1 (en) | 2002-01-31 |
| AU8542298A (en) | 1999-02-10 |
| GB2327544A (en) | 1999-01-27 |
| DE69803073T2 (en) | 2002-06-20 |
| EP0995269A1 (en) | 2000-04-26 |
| GB2327544B (en) | 2001-02-07 |
| KR20010015560A (en) | 2001-02-26 |
| CA2296403A1 (en) | 1999-01-28 |
| CN1264508A (en) | 2000-08-23 |
| WO1999004493A1 (en) | 1999-01-28 |
| JP2001510951A (en) | 2001-08-07 |
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