CN113659947B

CN113659947B - High-performance high-power low-noise TR chip

Info

Publication number: CN113659947B
Application number: CN202110854865.4A
Authority: CN
Inventors: 黄杨; 罗力伟; 王祁钰; 杨柯
Original assignee: Sichuan Yifeng Electronic Science & Technology Co ltd
Current assignee: Sichuan Yifeng Electronic Science & Technology Co ltd
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2022-04-08
Anticipated expiration: 2041-07-28
Also published as: CN113659947A

Abstract

The invention discloses a high-performance high-power low-noise TR chip, belongs to the technical field of wireless communication, and aims to solve the problems that a power amplifier chip which can meet the requirements of Ka-band high power, high efficiency, broadband high gain, low standing wave and miniaturization and can maintain high performance is lacked in the prior art, and a low-noise amplifier chip which can meet the requirements of a receiving end on low power consumption, low noise, high sensitivity and high performance is lacked. The invention provides a 10W amplifier through a three-stage amplifying circuit and a low noise amplifier through a four-stage amplifying circuit, and simultaneously integrates a 10W transmitting power amplifier and a receiving low noise amplifier on a TR chip. The 10W amplifier chip can keep high performance under the application scenes of high power, high efficiency, high gain of broadband, low standing wave and miniaturization of the Ka wave band, and simultaneously, the low-power consumption, low noise, high sensitivity and high performance low-noise amplifier chip of a receiving end is met.

Description

High-performance high-power low-noise TR chip

Technical Field

The invention belongs to the technical field of wireless communication, and particularly relates to a high-performance high-power low-noise TR chip.

Background

After silicon (Si) and gallium arsenide (GaAs), gallium nitride (GaN) materials with excellent high-temperature, high-voltage and high-frequency characteristics are called as representatives of third-generation semiconductors, devices and circuits based on the GaN materials become hot and important points of international research at present, and GaN has the characteristics of wide material gap, high electronic saturation rate, strong breakdown field, high temperature resistance, high voltage resistance and the like, and has important significance in the technical field of wireless communication. According to frequency division, microwaves are widely applied to a radar system due to the wavelength, the frequency bandwidth and the special atmospheric propagation characteristics of the microwaves, so that the rapid development of a microwave transceiving component is promoted, a power amplifier is the most critical component of the transceiving component, and the performance indexes of the power amplifier, the efficiency, the bandwidth and the like directly influence the performance of the whole transceiving component. At present, microwave monolithic integrated circuits have become a major development direction in various high-tech fields, so that it is very important to research power amplifier chips and low noise amplifiers in the frequency band.

In the prior art, for a microwave radar transmitting system, a transmitting end needs to provide enough transmitting power, and because a plurality of power amplifier chips are adopted in the transmitting system to perform power synthesis so as to provide enough transmitting power, a single power amplifier chip has high power, high efficiency and excellent performance, so that the number of chips can be effectively reduced, the cost is reduced, the power consumption is reduced, and the working stability is ensured. With the development of wireless communication, the Ka-band system is widely applied, such as automobile anti-collision radar, test radar, and the like. But the Ka wave band system has higher cost and few domestic mature products. However, with the development of technology, especially MMIC chips, the cost of Ka band systems will be greatly reduced. At present, a Ka band microwave monolithic integrated circuit has become a key development direction in various high-tech fields at present, and with the development of 5G communication technology, a part of a microwave communication frequency band will enter a civil category in the future, so that it becomes especially important for researching a TX chip of the frequency band.

Therefore, the prior art lacks a power amplifier chip which can meet the requirements of high power, high efficiency, broadband, high gain, low standing wave and high performance in the application scene of miniaturization of the Ka band, and lacks a low-noise amplifier chip which can meet the requirements of low power consumption, low noise, high sensitivity and high performance of a receiving end.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a high-performance high-power low-noise TR chip, which aims to: the high-performance 10W amplifier chip is maintained in the application scene of high power, high efficiency, broadband, high gain, low standing wave and miniaturization of the Ka waveband, the low-noise amplifier with low power consumption, low noise, high sensitivity and high performance of a receiving end is simultaneously met, and the Ka waveband 10W amplifier chip and the K waveband low-noise amplifier are integrated on the same chip.

In order to achieve the purpose, the invention adopts the technical scheme that: the high-performance high-power low-noise TR chip comprises a 10W amplifier and a low-noise amplifier, wherein circuits of the 10W amplifier are used for inputting and outputting power amplification radio-frequency signals, the 10W amplifier is sequentially connected through a three-stage amplifying circuit to form a signal channel, the 10W amplifier is a symmetrical circuit with two parts of circuit structures and component values which are completely the same, the power amplification radio-frequency signals are divided into two paths after entering the 10W amplifier, and the two paths of the power amplification radio-frequency signals are amplified by the two symmetrical circuits and then synthesized and output at a radio-frequency output end to realize the amplification of the power amplification radio-frequency signals;

the low-noise amplifier is used for inputting and outputting low-noise radio-frequency signals, and the low-noise amplifiers are sequentially connected through four stages of amplifiers to amplify the power of the low-noise radio-frequency signals.

Preferably, one of the symmetrical circuits of the 10W amplifier of the invention comprises an input matching network, the input matching network is connected with an input stage circuit, the input stage circuit is connected with an external circuit, the other end of the input matching network is connected with a first stabilizing network, a first bias circuit and a second bias circuit are connected between the input matching network and the first stabilizing network, one end of the first bias circuit is connected with a source VG1, the other end of the first bias circuit is connected with the second bias circuit, the other end of the second bias circuit is connected with a fourth bias circuit, the second bias circuit is connected with a second bias circuit of another symmetrical circuit, the first stabilizing network is connected with a gate of a Q1 transistor, a source of the Q1 transistor is grounded, a drain of the Q1 transistor is connected with the first matching network, and a first drain circuit is connected between a drain of the Q1 transistor and the first matching network, the first drain circuit is connected with a first drain circuit of another symmetrical circuit, the other end of the first drain circuit is connected with a power supply VD1 end, the first matching network is connected with a second stabilizing network and a third stabilizing network, a third bias circuit is connected between the first matching network and the second stabilizing network, a fourth bias circuit is connected between the first matching network and the third stabilizing network, the other end of the fourth bias circuit is connected with a fifth bias circuit, the second stabilizing network is connected with the grid electrode of a Q2 transistor, the source electrode of the Q2 transistor is grounded, the drain electrode of the Q2 transistor is connected with the second matching network, the third stabilizing network is connected with the grid electrode of a Q3 transistor, the source electrode of the Q3 transistor is grounded, the drain electrode of the Q3 transistor is connected with the second matching network, and a second drain circuit is connected between the drain electrodes of the Q2 transistor and the Q3 transistor and the second matching network, the second drain circuit is connected with a second drain circuit of another symmetrical circuit, the other end of the second drain circuit is connected with a VD2 end of a power supply, the second matching network is respectively connected with a fourth stabilizing network, a fifth stabilizing network, a sixth stabilizing network and a seventh stabilizing network, a sixth bias circuit is connected between the second matching network and the fourth stabilizing network, a fifth bias circuit is connected between the second matching network and the seventh stabilizing network, the fourth stabilizing network is connected with the grid of the Q4 transistor, the source of the Q4 transistor is grounded, the fifth stabilizing network is connected with the grid of the Q5 transistor, the source of the Q5 transistor is grounded, the sixth stabilizing network is connected with the grid of the Q6 transistor and the source of the Q6 transistor is grounded, the seventh stabilizing network is connected with the grid of the Q7 transistor, the source of the Q7 transistor is grounded, the drain of the Q4 transistor, the drain of the third stabilizing network is connected with the third stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, the fourth stabilizing network is connected with the fourth stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, and the fourth stabilizing network, respectively, and the fourth stabilizing network, and the, The drain electrode of the Q5 transistor, the drain electrode of the Q6 transistor and the drain electrode of the Q7 transistor are connected with a third matching network, the third matching network is connected with an output matching network, a third drain electrode circuit is connected between the third matching network and the output matching network, the other end of the third drain electrode circuit is connected with a VD3 end of a power supply, the output matching network is connected with an output stage circuit, and the output stage circuit is connected with an external circuit;

the low noise amplifier comprises a first impedance matching network, one end of the first impedance matching network is connected with an external circuit, the other end of the first impedance matching network is connected with a grid electrode of a Q8 transistor, a first grid bias circuit is connected between the first impedance matching network and a Q8 transistor, the first grid bias circuit is respectively connected with a second grid bias circuit, a third grid bias circuit, a fourth grid bias circuit and a power supply VLg end, a source electrode of a Q8 transistor is connected with two identical microstrip lines Ls, the other ends of the two microstrip lines Ls are respectively grounded, a drain electrode of the Q8 transistor is connected with a second impedance matching network, a first drain bias circuit is connected between a drain electrode of the Q8 transistor and the second impedance matching network, the first drain bias circuit is respectively connected with the second drain bias circuit, the third drain bias circuit and the fourth drain bias circuit, and the second impedance matching network is connected with a grid electrode of a Q9 transistor, a second grid bias circuit is connected between the second impedance matching network and the grid of the Q9 transistor, the other end of the second grid bias circuit is connected with the ends of the first grid bias circuit, the third grid bias circuit, the fourth grid bias circuit and a power supply VLg, the source of the Q9 transistor is connected with two identical microstrip lines Ls, the other ends of the two microstrip lines Ls are respectively grounded, the drain of the Q9 transistor is connected with the third impedance matching network, a second drain bias circuit is connected between the drain of the Q9 transistor and the third impedance matching network, the second drain bias circuit is respectively connected with the first drain bias circuit, the third drain bias circuit and the fourth drain bias circuit, the third impedance matching network is connected with the grid of the Q10 transistor, a third grid bias circuit is connected between the third impedance matching network and the grid of the Q10 transistor, and the other end of the third grid bias circuit is connected with the first grid bias circuit, The second grid bias circuit, the fourth grid bias circuit and the power VLg end are connected, the source of the Q10 transistor is connected with two identical microstrip lines Ls, the other ends of the two microstrip lines Ls are respectively grounded, the drain of the Q10 transistor is respectively connected with the third impedance matching network and the fourth impedance matching network, a third drain bias circuit is connected between the drain of the Q10 transistor and the fourth impedance matching network, the third drain bias circuit is respectively connected with the first drain bias circuit, the second drain bias circuit and the fourth drain bias circuit, the fourth impedance matching network is connected with the grid of the Q11 transistor, the fourth grid bias circuit is connected between the fourth impedance matching network and the grid of the Q11 transistor, and the other end of the fourth grid bias circuit is connected with the first grid bias circuit, the second grid bias circuit, the third grid bias circuit and the power VLg end, the source electrode of the Q11 transistor is connected with two identical microstrip lines Ls, the other ends of the two microstrip lines Ls are respectively grounded, the drain electrode of the Q11 transistor is connected with a fifth impedance matching network, a fourth drain electrode biasing circuit and a fifth drain electrode biasing circuit are connected between the drain electrode of the Q11 transistor and the fifth impedance matching network, the fourth drain electrode biasing circuit is respectively connected with the first drain electrode biasing circuit, the second drain electrode biasing circuit and the third drain electrode biasing circuit, the other end of the fifth drain electrode biasing circuit is connected with the end VLd of a power supply, and the fifth impedance matching network is connected with an external circuit.

Preferably, the first bias circuit, the second bias circuit, the third bias circuit, the fourth bias circuit, the fifth bias circuit and the sixth bias circuit of the 10W amplifier have the same structure and the same component values, the first bias circuit is composed of an R1 resistor, an R2 resistor, an R3 resistor, a C3 capacitor, a C4 capacitor and an L1 inductor, the R1 resistor, the L1 inductor and the R2 resistor are sequentially connected in series, the other end of the R1 resistor is connected with a first stabilizing network, the other end of the R2 resistor is connected with a VG1 end, a C3 capacitor is connected between the R2 resistor and a VG1 end, the other end of the C3 capacitor is grounded, a R3 resistor is connected between the R2 resistor and the VG1 end, a R3 resistor is connected in series with a C4 capacitor, and the other end of the C4 capacitor is grounded; the second bias circuit is composed of an R6 resistor, an R7 resistor, an R8 resistor, a C19 capacitor, a C20 capacitor and an L2 inductor, the R6 resistor, the L2 inductor and the R7 resistor are sequentially connected in series, the other end of the R6 resistor is connected with the first stabilizing network, the other end of the R7 resistor is respectively connected with the fourth bias circuit and the fifth bias circuit, the R7 resistor is connected with the R7 resistor of another symmetric circuit, the R7 resistor is connected with the C19 capacitor, the other end of the C19 capacitor is grounded, the R7 resistor is further connected with the series circuit of the R8 resistor and the C20 capacitor, and the other end of the C20 capacitor is grounded; the third bias circuit is composed of an R12 resistor, an R13 resistor, an R14 resistor, a C13 capacitor, a C14 capacitor and an L3 inductor, the R12 resistor, the L3 inductor and the R13 resistor are sequentially connected in series, the other end of the R12 resistor is connected with the second stabilizing network, the other end of the R13 resistor is further connected with a C13 capacitor and an R14 resistor, the other end of the C13 capacitor is grounded, the R14 resistor and the C14 capacitor are connected in series to form a circuit, and the other end of the C14 capacitor is grounded; the fourth bias circuit is composed of an R9 resistor, an R10 resistor, an R11 resistor, a C21 capacitor, a C22 capacitor and an L4 inductor, the R9 resistor, the L4 inductor and the R10 resistor are sequentially connected in series, the other end of the R9 resistor is connected with a third stabilizing network, the other end of the R10 resistor is connected with a C21 capacitor and the R11 resistor, the other end of the C21 capacitor is grounded, the R11 resistor is connected with the C22 capacitor in series, and the other end of the C22 capacitor is grounded. The fifth bias circuit is composed of an R21 resistor, an R22 resistor, an R23 resistor, a C33 capacitor, a C34 capacitor and an L6 inductor, the R21 resistor, the L6 inductor and the R22 resistor are sequentially connected in series, the other end of the R21 resistor is connected with a seventh stabilizing network, the other end of the R22 resistor is connected with a C33 capacitor and an R23 resistor, the other end of the C33 capacitor is grounded, the R23 resistor is connected with a C34 capacitor in series, the other end of the C34 capacitor is grounded, the sixth bias circuit is composed of an R18 resistor, an R19 resistor, an R20 resistor, a C35 capacitor, a C36 capacitor and an L5 inductor, the R18 resistor, the L5 inductor and the R19 resistor are sequentially connected in series, the other end of the R18 resistor is connected with a fourth stabilizing network, the other end of the R19 resistor is connected with a C36 capacitor and an R20 resistor, the other end of the C36 capacitor is grounded, and the other end of the R20 resistor is connected with a C20 resistor and a C20 capacitor in series.

Preferably, the first drain circuit of the invention comprises an R resistor, a C capacitor, an M microstrip line and a C capacitor, wherein the M microstrip line and the M microstrip line are connected in series, a drain of a Q transistor is connected between the M microstrip line and the M microstrip line, the other end of the M microstrip line is connected to a VD terminal of a power supply, a C capacitor is arranged on a line between the M microstrip line and the VD terminal of the power supply, the other end of the C capacitor is grounded, a circuit in which an R resistor and a C capacitor are connected in series is further connected between the M microstrip line and the VD terminal of the power supply, the other end of the C capacitor is grounded, the other end of the M microstrip line is connected to a C capacitor, the other end of the C capacitor is grounded, the C capacitor is connected to the M microstrip line of another symmetrical circuit, and the second drain circuit comprises an R resistor, a C capacitor, an M microstrip line and a C capacitor, the M13 microstrip line, the M12 microstrip line and the M38 microstrip line are sequentially connected in series, the other end of the M13 microstrip line is connected with a power supply VD2 end, a C2 capacitor is arranged on a line between the M13 microstrip line and the power supply VD2 end, the other end of the C2 capacitor is grounded, a circuit formed by connecting an R2 resistor and the C2 capacitor in series is further connected between the M2 microstrip line and the power supply VD2 end, the other end of the C2 capacitor is grounded, the C2 capacitor is connected with the M2 microstrip line of another symmetrical circuit in series, the third drain circuit is formed by connecting an R2 resistor, the C2 capacitor and the M2 microstrip line, the M2 end is connected with the power supply VD2 end in series, the other end of the M2 microstrip line is connected with a third matching network, the C2 capacitor and the C2 resistor are connected between the M2 end of the power supply VD2 microstrip line, and the capacitor of the M2 is grounded, the R28 resistor is connected with the C54 capacitor in series, and the other end of the C54 capacitor is grounded.

Preferably, the input stage circuit of the invention is composed of an M1 microstrip line and a C0 capacitor, the other end of the M1 microstrip line is connected with the input end of an external circuit, the other end of the M1 microstrip line is connected with an input matching network and a C0 capacitor, the other end of the C0 capacitor is grounded, the input matching network comprises an M2 microstrip line, a C1 capacitor, an M3 microstrip line and a C2 capacitor, the C1 capacitor, the M2 microstrip line and the M3 microstrip line are sequentially connected in series, a C2 capacitor is connected on a connection line between the M2 microstrip line and the M3 microstrip line, the other end of the C2 capacitor is grounded, the other end of the C1 capacitor is connected with the input stage circuit, and the other end of the M3 microstrip line is connected with a first stabilizing network.

Preferably, the first stabilizing network, the second stabilizing network, the third stabilizing network, the fourth stabilizing network, the fifth stabilizing network, the sixth stabilizing network and the seventh stabilizing network have the same circuit structure and component values, and are all connecting circuits of two capacitors and one resistor, and the fourth stabilizing network, the fifth stabilizing network, the sixth stabilizing network and the seventh stabilizing network are connected with each other.

Preferably, the first matching network of the present invention includes an M5 microstrip line, a C9 capacitor, a C10 capacitor, an M6 microstrip line, an M7 microstrip line, a C11 capacitor, an M8 microstrip line, an M9 microstrip line, and a C12 capacitor, one end of the M5 microstrip line is connected to the drain of the Q1 transistor, the other end of the M5 microstrip line is connected to the C10 capacitor, a C9 capacitor is connected between the M5 microstrip line and the C10 capacitor, the other end of the C9 capacitor is grounded, the other end of the C10 capacitor is connected to the M6 microstrip line and the M7 microstrip line, the M6 microstrip line is connected to the M8 microstrip line and the C11 capacitor, the other end of the C11 capacitor is grounded, the other end of the M8 microstrip line is connected to the second stabilizing network, the M7 microstrip line is connected to the M9 microstrip line and the C12 capacitor, the other end of the C12 capacitor is grounded, and the other end of the M9 microstrip line is connected to the third stabilizing network.

Preferably, the second matching network of the present invention includes an M10 microstrip line, an M11 microstrip line, an M14 microstrip line, an M15 microstrip line, a C25 capacitor, a C26 capacitor, an M16 microstrip line, an M17 microstrip line, a C27 capacitor, a C30 capacitor, an M18 microstrip line, an M19 microstrip line, an M20 microstrip line, an M21 microstrip line, a C28 capacitor, a C29 capacitor, a C31 capacitor, and a C32 capacitor, the M32 microstrip line, the M32 capacitor are sequentially connected in series, the M32 microstrip line and the M32 microstrip line are connected between a second drain circuit M32 microstrip line and the M32 microstrip line, a C32 capacitor is connected between the M32 microstrip line and the M32 microstrip line, the M32 microstrip line is connected between the M32 microstrip line and the M32 line, the M32 line is connected between the M32 line, the M32 line and the M32 line are connected in series, the M32 line and the M32 line are connected between the M32 line, the M32 line and the M32 line are connected between the M32 line, the M32 line and the M32 line, the M32 line are connected between the M32 line, the M32 line and the M32 line are connected in series capacitor, the other end of the C26 capacitor is grounded, the other end of the C27 capacitor is connected with an M18 microstrip line and an M19 microstrip line respectively, the other end of the M18 microstrip line is connected with a C28 capacitor and a fourth stabilizing network, the other end of the C28 capacitor is grounded, the other end of the M19 microstrip line is connected with a C29 capacitor and a fifth stabilizing network, the other end of the C29 capacitor is grounded, the other end of the C30 capacitor is connected with an M20 microstrip line and an M21 microstrip line respectively, the other end of the M20 microstrip line is connected with a C31 capacitor and a sixth stabilizing network, the other end of the C31 capacitor is grounded, the other end of the M21 microstrip line is connected with a C32 capacitor and a seventh stabilizing network, and the other end of the C32 capacitor is grounded.

Preferably, the third matching network of the present invention includes an M22 microstrip line, an M23 microstrip line, an M24 microstrip line, an M25 microstrip line, an M26 microstrip line, an M27 microstrip line, an M28 microstrip line, an M29 microstrip line, a C45 capacitor, a C46 capacitor, a C47 capacitor, a C48 capacitor, a C49 capacitor, a C50 capacitor, an M30 microstrip line, an M31 microstrip line, a C51 capacitor, a C52 capacitor, an M32 microstrip line, an M33 microstrip line and an M34 microstrip line, the M22 microstrip line and the M22 microstrip line are connected in series, the other end of the M22 microstrip line is connected to a drain of the Q22 transistor, the C22 capacitor is connected to a line between the M22 microstrip line and the M22 microstrip line, the C22 microstrip line is grounded, the M22 microstrip line and the M22 line are connected in series, the M22 line is connected to a drain of the Q22 transistor, the M22 line is connected to a ground, the C22 line is connected to the M22 and the M22 line, the M22 line is connected to the M22, the M22 capacitor and the M22 line is connected to the M22, the other end of the M24 microstrip line is connected with a drain of a Q6 transistor, a C28 capacitor is connected on a line between the M24 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, the M28 microstrip line is connected with the M28 microstrip line in series, the other end of the M28 microstrip line is connected with a drain of a Q28 transistor, a C28 capacitor is connected on a line between the M28 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, the M28 microstrip line and the M28 microstrip line are connected in series in sequence, a C28 capacitor and an M28 microstrip line are respectively connected between the M28 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, a C28 capacitor is connected between the M28 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, the M28 microstrip line, the M28 and the M28 microstrip line are connected in series in sequence, The other end of the C48 capacitor is grounded, a C52 capacitor is connected between the M31 microstrip line and the M33 microstrip line, the other end of the C52 capacitor is grounded, the M32 microstrip line and the M33 microstrip line are both connected with the M34 microstrip line, and the M34 microstrip line is respectively connected with the third drain circuit and the output matching network.

Preferably, the output matching network of the present invention includes an M36 microstrip line, one end of the M36 microstrip line is connected to the third matching network, the other end of the M36 microstrip line is connected to the output stage circuit, the output stage circuit includes a C55 capacitor and an M37 microstrip line, the C55 capacitor and the M37 microstrip line are sequentially connected in series, and the M37 microstrip line is connected to the peripheral circuit.

Preferably, the circuit structure of the first gate bias circuit, the second gate bias circuit, the third gate bias circuit and the fourth gate bias circuit is completely the same as the values of all components, and all the components comprise an Rg1 resistor, an Rg resistor, a Cg1 capacitor, a Cg2 capacitor and an Lg inductor, one end of the Lg inductor of the first gate bias circuit is respectively connected with the gate of the Q8 transistor and the first impedance matching network, the Lg inductor is connected with the Rg1 resistor in series, the other end of the Rg1 resistor is connected with the VLg end of a power supply, the Lg inductor and the Rg1 resistor are indirectly connected with the Rg resistor and the Cg1 capacitor respectively, the other end of the Cg1 capacitor is grounded, the resistor is connected with the Cg2 capacitor in series, and the other end of the Cg2 capacitor is grounded.

Preferably, the circuit structures and the component values of the first drain bias circuit, the second drain bias circuit, the third drain bias circuit, the fourth drain bias circuit and the fifth drain bias circuit are completely the same, and the first drain bias circuit, the second drain bias circuit, the third drain bias circuit, the fourth drain bias circuit and the fifth drain bias circuit are all composed of a Rd resistor, a Cd1 capacitor, a Cd2 capacitor and an Ld inductor, one end of the Ld inductor of the first drain bias circuit is connected with the drain of the Q8 transistor and the second impedance matching network, the other end of the Ld inductor is connected with a Rd resistor Cd1 capacitor, the other end of the Cd1 capacitor is grounded, the Rd resistor is connected with a Cd2 capacitor in series, and the other end of the Cd2 capacitor is grounded.

Preferably, the first impedance matching network of the present invention includes an LL1 microstrip line, a CL1 capacitor, and a CL2 capacitor, the CL1 capacitor and the LL1 microstrip line are sequentially connected in series, a CL2 capacitor is connected to a connection line between the LL1 microstrip line and the CL1 capacitor, the other end of the CL2 capacitor is grounded, the other end of the CL1 capacitor is connected to a peripheral signal input, and the other end of the LL1 microstrip line is connected to a Q8 transistor gate and a first gate bias circuit;

the second impedance matching network comprises an LL2 microstrip line, a CL3 capacitor and a CL4 capacitor, the CL3 capacitor and the LL2 microstrip line are sequentially connected in series, a CL4 capacitor is connected to a connection line between the LL2 microstrip line and the CL3 capacitor, the other end of the CL4 capacitor is grounded, one end of the CL3 capacitor is connected with a drain of a Q8 transistor and a first drain bias circuit, and the other end of the LL2 microstrip line is connected with a gate of the Q9 transistor and a second gate bias circuit;

the third impedance matching network comprises an LL3 microstrip line, an LL4 microstrip line, a CL5 capacitor, a CL6 capacitor, a CL7 capacitor and an RL1 resistor, wherein the CL6 capacitor, the LL3 microstrip line, the CL7 capacitor, the RL1 resistor and the LL4 microstrip line are sequentially connected in series, a CL5 capacitor is connected to a connecting line between the LL3 microstrip line and the CL6 capacitor, the other end of the CL5 capacitor is grounded, the other end of the CL6 capacitor is connected with a drain of a Q9 transistor and a second drain bias circuit, the LL3 microstrip line is also respectively connected with a gate of the Q10 transistor and a third gate bias circuit, and the LL4 microstrip line is respectively connected with a drain of the Q10 transistor and the third drain bias circuit;

the fourth impedance matching network comprises an LL5 microstrip line, a CL8 capacitor, a CL9 capacitor and an LL6 microstrip line, the LL5 microstrip line, the CL8 capacitor and the LL6 microstrip line are sequentially connected in series, a CL9 capacitor is connected to a connecting line between the LL6 microstrip line and the CL8 capacitor, the other end of the CL9 capacitor is grounded, the other end of the LL6 microstrip line is respectively connected with a drain of a Q10 transistor and a third drain bias circuit, and the other end of the LL6 microstrip line is respectively connected with a grid of a Q11 transistor and a fourth gate bias circuit;

the fifth impedance matching network comprises an LL7 microstrip line and a CL10 capacitor LL8 microstrip line, the LL8 microstrip line and the CL10 capacitor are sequentially connected in series, a connecting line between the LL8 microstrip line and the CL10 capacitor is connected with the LL7 microstrip line, the other end of the LL7 microstrip line is grounded, the other end of the CL10 capacitor is respectively connected with a drain of a Q11 transistor, a fourth drain bias circuit and a fifth drain bias circuit, and the other end of the LL8 microstrip line is connected with a peripheral circuit.

The technical scheme of the invention has the following advantages/beneficial effects:

1. the circuit structure of the 10W amplifier is vertically symmetrical about the central line of the input and output ports of the radio-frequency signals, and the upper circuit and the lower circuit are completely the same, so that the phase and the amplitude of the upper signal and the lower signal are ensured to have high consistency, and the power synthesis loss of the upper signal and the lower signal at the output end is reduced.

2. The whole signal path of the TR chip adopts the capacitor and the microstrip line for impedance matching, the capacitor and the microstrip line are convenient to realize and adjust, the loss is small, and the loss introduced by a matching device is effectively reduced.

3. The invention adopts a special bias circuit and a drain electrode circuit, and has the functions of providing direct current power supply and preventing high-frequency self-excitation while finishing impedance matching.

4. The stability of the circuit can be conveniently and effectively adjusted by adopting the stable network of the resistor and capacitor structure, the stability of the circuit can be improved by adjusting the values of the capacitor and the resistor, and the insertion loss of the structure is small.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a chip peripheral interface according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of the signal path structure of the 10W amplifier of the present invention.

Fig. 3 is a schematic diagram of the signal path structure of the low noise amplifier of the present invention.

Fig. 4 is a schematic diagram of the overall circuit structure of the 10W amplifier of the present invention.

Fig. 5 is a schematic diagram of the overall circuit structure of the low noise amplifier of the present invention.

Fig. 6 is a schematic diagram of the input stage circuit structure of the 10W amplifier of the invention.

Fig. 7 is a schematic diagram of the input matching network circuit of the 10W amplifier of the present invention.

Fig. 8 shows the first, second, third, fourth, fifth and sixth bias circuit structures of the 10W amplifier of the present invention.

Fig. 9 is a schematic circuit diagram of the first, second, third, fourth, fifth, sixth and seventh stable networks of the 10W amplifier of the invention.

FIG. 10 is a schematic diagram of a first drain circuit of the 10W amplifier of the present invention.

Fig. 11 is a schematic diagram of a first matching network circuit of the 10W amplifier of the present invention.

FIG. 12 is a schematic diagram of a second drain circuit of the 10W amplifier of the present invention.

Fig. 13 is a schematic diagram of a second matching network circuit of the 10W amplifier of the present invention.

Fig. 14 is a schematic diagram of a third matching network circuit of the 10W amplifier of the present invention.

FIG. 15 is a schematic diagram of a third drain circuit of the 10W amplifier of the present invention.

Fig. 16 is a schematic diagram of the circuit structure of the output matching network of the 10W amplifier of the present invention.

Fig. 17 is a schematic diagram of the circuit structure of the output stage of the 10W amplifier of the present invention.

Fig. 18 is a schematic diagram of a first impedance matching network structure of the low noise amplifier of the present invention.

FIG. 19 is a schematic diagram of the first, second, third and fourth gate bias circuits of the low noise amplifier of the present invention.

FIG. 20 is a schematic diagram of the first, second, third, fourth, and fifth drain bias circuits of the low noise amplifier of the present invention.

Fig. 21 is a schematic diagram of a second impedance matching network structure of the low noise amplifier of the present invention.

Fig. 22 is a schematic diagram of a third impedance matching network structure of the low noise amplifier of the present invention.

Fig. 23 is a schematic diagram of a fourth impedance matching network structure of the low noise amplifier of the present invention.

Fig. 24 is a schematic diagram of a fifth impedance matching network structure of the low noise amplifier of the present invention.

Fig. 25 is a graph of the input return loss of a 10W amplifier of the present invention.

Fig. 26 is a graph of the output return loss of a 10W amplifier of the present invention.

Fig. 27 is a graph of the input return loss of the low noise amplifier of the present invention.

Fig. 28 is a graph of the output return loss of the low noise amplifier of the present invention.

Fig. 29 is a signal gain plot for a 10W amplifier of the present invention.

Fig. 30 is a signal gain plot for a low noise amplifier of the present invention.

FIG. 31 is a graph of Power Added Efficiency (PAE) for a chip of the present invention.

Fig. 32 is a graph of output power (Pout) of the chip of the present invention.

Fig. 33 is a graph of the noise figure of the low noise amplifier of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, not all of the embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the detailed description of the embodiments of the present invention provided below is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention.

Example 1:

as shown in fig. 1, the invention provides a high-performance high-power low-noise TR chip, which includes a 10W amplifier and a low-noise amplifier, wherein a circuit of the 10W amplifier is used for inputting and outputting a power amplifier radio frequency signal, the 10W amplifier is connected in sequence through a three-stage amplifying circuit to form a signal channel, the 10W amplifier is a symmetrical circuit with two parts of circuit structures and identical component values, the power amplifier radio frequency signal is equally divided into two paths after entering the 10W amplifier, and the two parts of the symmetrical circuit are amplified and then synthesized and output at a radio frequency output end, so that the power amplification of the power amplifier radio frequency signal power is realized;

The upper circuit and the lower circuit of the TR chip are respectively supplied with power, 6 power supply interfaces are shared in total, the power supply interfaces comprise 1 VG1, 1 VD1, 1 VD2, 1 VD3, 1 VLg and 1 VLd, when a power amplifier transmitting end of the TR chip normally works, the power supply voltage VG1= -1.1V of a power amplifier biasing circuit, the power supply voltage VD1= VD2 = VD3=12V of a power amplifier drain circuit, the VLg ═ 3V and the VLd ═ 0V; when the low-noise receiving end of the TR chip normally works, the power supply voltage VLg of the bias circuit of the low-noise amplifier is not less than-1.1V, VLd is not less than 5V, the power supply voltage VD1 of the drain circuit of the power amplifier is not less than VD2, not less than VD3, and VG1 is not less than-3V.

The TR chip of the invention adopts a silicon-based GaN process with the gate length of 100nm, the power amplifier working in a Ka wave band transmitting branch has better high-frequency, high-power and high-efficiency characteristics, the working frequency band is 26GHz-30GHz, the circuit of the chip adopts 3-level amplification, the small signal gain is greater than 22dB, the final-level 8-path synthesis can realize the output power of 10W (40dBm), the circuit size is effectively reduced under the condition of ensuring the required power output, the Power Additional Efficiency (PAE) is greater than 30%, the input and output return loss is greater than 10dB, the chip has the advantages of high power, high efficiency, miniaturization, low standing wave and the like, the low-noise amplifier working in a K wave band receiving branch has better low power consumption, low noise, high sensitivity and high performance, the working frequency band is 18GHz-22GHz, the circuit of the chip adopts 4-level amplification, the small signal gain is greater than 27dB, the input and output return loss is more than 10dB, the noise system is less than 1.6dB, the receiving low-noise amplifier chip has the advantages of low power consumption, low noise, high sensitivity, miniaturization, low standing wave and the like, and meanwhile, a 10W transmitting power amplifier and a receiving low-noise amplifier are integrated on one TR chip.

As shown in fig. 2, fig. 3, fig. 4 and fig. 5, one of the symmetrical circuits of the 10W amplifier of the present invention includes an input matching network, the input matching network is connected to an input stage circuit, the input stage circuit is connected to an external circuit, the other end of the input matching network is connected to a first stabilizing network, a first bias circuit and a second bias circuit are connected between the input matching network and the first stabilizing network, one end of the first bias circuit is connected to a terminal VG1, the other end of the first bias circuit is connected to a second bias circuit, the other end of the second bias circuit is connected to a fourth bias circuit, the second bias circuit is connected to a second bias circuit of another symmetrical circuit, the first stabilizing network is connected to a gate of a Q1 transistor, a source of the Q1 transistor is grounded, a drain of the Q1 transistor is connected to the first matching network, a drain of the Q1 transistor is connected to the first matching network, the first drain circuit is connected with a first drain circuit of another symmetrical circuit, the other end of the first drain circuit is connected with a power supply VD1 end, the first matching network is connected with a second stabilizing network and a third stabilizing network, a third bias circuit is connected between the first matching network and the second stabilizing network, a fourth bias circuit is connected between the first matching network and the third stabilizing network, the other end of the fourth bias circuit is connected with a fifth bias circuit, the second stabilizing network is connected with the grid electrode of a Q2 transistor, the source electrode of the Q2 transistor is grounded, the drain electrode of the Q2 transistor is connected with the second matching network, the third stabilizing network is connected with the grid electrode of a Q3 transistor, the source electrode of the Q3 transistor is grounded, the drain electrode of the Q3 transistor is connected with the second matching network, and a second drain circuit is connected between the drain electrodes of the Q2 transistor and the Q3 transistor and the second matching network, the second drain circuit is connected with a second drain circuit of another symmetrical circuit, the other end of the second drain circuit is connected with a VD2 end of a power supply, the second matching network is respectively connected with a fourth stabilizing network, a fifth stabilizing network, a sixth stabilizing network and a seventh stabilizing network, a sixth bias circuit is connected between the second matching network and the fourth stabilizing network, a fifth bias circuit is connected between the second matching network and the seventh stabilizing network, the fourth stabilizing network is connected with the grid of the Q4 transistor, the source of the Q4 transistor is grounded, the fifth stabilizing network is connected with the grid of the Q5 transistor, the source of the Q5 transistor is grounded, the sixth stabilizing network is connected with the grid of the Q6 transistor and the source of the Q6 transistor is grounded, the seventh stabilizing network is connected with the grid of the Q7 transistor, the source of the Q7 transistor is grounded, the drain of the Q4 transistor, the drain of the third stabilizing network is connected with the third stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, the fourth stabilizing network is connected with the fourth stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, and the fourth stabilizing network are connected with the fourth stabilizing network, and the fourth stabilizing network, respectively, and the fourth stabilizing network, and the, The drain electrode of the Q5 transistor, the drain electrode of the Q6 transistor and the drain electrode of the Q7 transistor are connected with a third matching network, the third matching network is connected with an output matching network, a third drain electrode circuit is connected between the third matching network and the output matching network, the other end of the third drain electrode circuit is connected with a VD3 end of a power supply, the output matching network is connected with an output stage circuit, and the output stage circuit is connected with an external circuit;

The gate width of the Q1 transistor is 6 x 65um, the gate width of the Q2 transistor is 6 x 75um, the gate width of the Q3 transistor is 6 x 75um, the gate width of the Q4 transistor is 8 x 65um, the gate width of the Q5 transistor is 8 x 65um, the gate width of the Q6 transistor is 8 x 65um, the gate width of the Q7 transistor is 8 x 65um, the gate width of the Q8 transistor is 4 x 50um, the gate width of the Q9 transistor is 4 x 50um, the gate width of the Q10 transistor is 4 x 50um, and the gate width of the Q11 transistor is 4 x 50 um; the chip is used for transmitting and receiving a TR system chip of signals, the length and the width of the chip are 0.1mm, and the chip is designed by adopting a silicon-based GaN material process with the gate length of 100 nm.

As shown in fig. 8, the first bias circuit, the second bias circuit, the third bias circuit, the fourth bias circuit, the fifth bias circuit and the sixth bias circuit of the 10W amplifier of the present invention have the same structure and the same component values, the first bias circuit is composed of an R1 resistor, an R2 resistor, an R3 resistor, a C3 capacitor, a C4 capacitor and an L1 inductor, the R1 resistor, the L1 inductor and the R2 resistor are sequentially connected in series, the other end of the R1 resistor is connected to a first stabilizing network, the other end of the R2 resistor is connected to a VG1 terminal, a C3 capacitor is connected between the R2 resistor and a VG1 terminal, the other end of the C3 capacitor is grounded, a R3 resistor is connected between the R2 resistor and a VG1 terminal, a R3 resistor is connected to a C4 capacitor in series, and the other end of the C4 capacitor is grounded; r1 resistance is 15 ohm, R2 resistance is current-limiting resistor, prevent that transistor grid current from too big burning, the resistance size is 20 ohm, L1 inductance chokes high frequency signal and gets into DC power supply, the size is 1nH, C3 electric capacity is high frequency decoupling capacitor, the size is 1pF, R3 resistance and C4 electric capacity series connection for the interference of low frequency signal in the filtering power supply, R3 resistance is 10 ohm, C4 electric capacity is 3 pF.

The second bias circuit is composed of an R6 resistor, an R7 resistor, an R8 resistor, a C19 capacitor, a C20 capacitor and an L2 inductor, the R6 resistor, the L2 inductor and the R7 resistor are sequentially connected in series, the other end of the R6 resistor is connected with the first stabilizing network, the other end of the R7 resistor is respectively connected with the fourth bias circuit and the fifth bias circuit, the R7 resistor is connected with the R7 resistor of another symmetric circuit, the R7 resistor is connected with the C19 capacitor, the other end of the C19 capacitor is grounded, the R7 resistor is further connected with the series circuit of the R8 resistor and the C20 capacitor, and the other end of the C20 capacitor is grounded; the third bias circuit is composed of an R12 resistor, an R13 resistor, an R14 resistor, a C13 capacitor, a C14 capacitor and an L3 inductor, the R12 resistor, the L3 inductor and the R13 resistor are sequentially connected in series, the other end of the R12 resistor is connected with the second stabilizing network, the other end of the R13 resistor is further connected with a C13 capacitor and an R14 resistor, the other end of the C13 capacitor is grounded, the R14 resistor and the C14 capacitor are connected in series to form a circuit, and the other end of the C14 capacitor is grounded; the fourth bias circuit is composed of an R9 resistor, an R10 resistor, an R11 resistor, a C21 capacitor, a C22 capacitor and an L4 inductor, the R9 resistor, the L4 inductor and the R10 resistor are sequentially connected in series, the other end of the R9 resistor is connected with a third stabilizing network, the other end of the R10 resistor is connected with a C21 capacitor and the R11 resistor, the other end of the C21 capacitor is grounded, the R11 resistor is connected with the C22 capacitor in series, and the other end of the C22 capacitor is grounded. The fifth bias circuit is composed of an R21 resistor, an R22 resistor, an R23 resistor, a C33 capacitor, a C34 capacitor and an L6 inductor, the R21 resistor, the L6 inductor and the R22 resistor are sequentially connected in series, the other end of the R21 resistor is connected with a seventh stabilizing network, the other end of the R22 resistor is connected with a C33 capacitor and an R23 resistor, the other end of the C33 capacitor is grounded, the R23 resistor is connected with a C34 capacitor in series, the other end of the C34 capacitor is grounded, the sixth bias circuit is composed of an R18 resistor, an R19 resistor, an R20 resistor, a C35 capacitor, a C36 capacitor and an L5 inductor, the R18 resistor, the L5 inductor and the R19 resistor are sequentially connected in series, the other end of the R18 resistor is connected with a fourth stabilizing network, the other end of the R19 resistor is connected with a C36 capacitor and an R20 resistor, the other end of the C36 capacitor is grounded, and the other end of the R20 resistor is connected with a C20 resistor and a C20 capacitor in series. The topological structures of the second bias circuit, the third bias circuit, the fourth bias circuit, the fifth bias circuit and the sixth bias circuit are completely the same as those of the first bias circuit, and the values and functions of the components are also the same.

As shown in fig. 10, the first drain circuit of the present invention is composed of an R5 resistor, a C7 capacitor, a C8 capacitor, an M4 microstrip line, an M37 microstrip line, and a C56 capacitor, where the M4 microstrip line is connected in series with the M37 microstrip line, a drain of a Q1 transistor is connected between the M4 microstrip line and the M37 microstrip line, the other end of the M4 microstrip line is connected to a VD1 terminal, a C7 capacitor is arranged on a line between the M4 microstrip line and the VD1 terminal, the other end of the C7 capacitor is grounded, a circuit in which an R5 resistor is connected in series with a C8 capacitor is further connected between the M4 microstrip line and the VD1 terminal, the other end of the C8 capacitor is grounded, the other end of the M37 microstrip line is connected to a C56 capacitor, the other end of the C56 capacitor is grounded, and the C56 capacitor is connected to an M37 microstrip line 29 line of another symmetrical circuit;

the resistor R5 and the capacitor C8 are connected in series to filter interference of low-frequency signals in a power supply, the resistor R5 is 10 ohms, the capacitor C8 is 3pF, the M4 microstrip line and the capacitor C7 participate in impedance matching of a circuit and control high-frequency signals to enter a direct-current power supply, the M37 microstrip line supplies power to a drain electrode of a lower symmetrical circuit, and the capacitor C56 plays a role in inhibiting signal interference of an upper symmetrical circuit and a lower symmetrical circuit.

As shown in fig. 12, the second drain circuit is composed of an R17 resistor, a C23 capacitor, a C24 capacitor, an M13 microstrip line, an M12 microstrip line, an M38 microstrip line, and a C57 capacitor, the M13 microstrip line, the M12 microstrip line, and the M38 microstrip line are sequentially connected in series, the other end of the M13 microstrip line is connected to a VD2 terminal, a C23 capacitor is provided on a line between the M13 microstrip line and the VD2 terminal, the other end of the C23 capacitor is grounded, a circuit in which an R17 resistor is connected in series with a C24 capacitor is further connected between the M13 microstrip line and the VD2 terminal, the other end of the C24 capacitor is grounded, the other end of the M38 microstrip line is connected to a C57 capacitor, the other end of the C57 capacitor is grounded, the C57 capacitor is connected to an M microstrip line 38 of another symmetrical circuit,

the resistor R17 and the capacitor C24 are connected in series to filter interference of low-frequency signals in a power supply, the resistor R17 is 10 ohms, the capacitor C24 is 3pF, the M13 microstrip line and the capacitor C23 participate in impedance matching of a circuit and control high-frequency signals to enter a direct-current power supply, the M38 microstrip line supplies power to a drain electrode of a lower symmetrical circuit, and the capacitor C57 plays a role in inhibiting signal interference of an upper symmetrical circuit and a lower symmetrical circuit.

As shown in fig. 15, the third drain circuit is composed of an R28 resistor, a C53 capacitor, a C54 capacitor, and an M35 microstrip line, the M35 microstrip line is connected in series with the VD3 power supply end, the other end of the M35 microstrip line is connected to the third matching network, a C53 capacitor and an R28 resistor are connected between the M35 microstrip line and the VD3 power supply end, the other end of the C53 capacitor is grounded, the R28 resistor is connected in series with the C54 capacitor, and the other end of the C54 capacitor is grounded.

The capacitor C53 filters the interference of low-frequency signals at the VD3 end of a power supply, the R28 resistor is 10 ohms, the C54 capacitor is 3pF, the M35 microstrip line and the C53 capacitor participate in impedance matching of the circuit and restrain high-frequency signals from entering a direct-current power supply.

As shown in fig. 6 and 7, the input stage circuit of the present invention is composed of an M1 microstrip line and a C0 capacitor, the other end of the M1 microstrip line is connected to an input end of an external circuit, the other end of the M1 microstrip line is connected to an input matching network and the C0 capacitor, the other end of the C0 capacitor is grounded, the input matching network includes an M2 microstrip line, a C1 capacitor, an M3 microstrip line, and a C2 capacitor, the C1 capacitor, the M2 microstrip line, and the M3 microstrip line are sequentially connected in series, a C2 capacitor is connected to a connection line between the M2 microstrip line and the M3 microstrip line, the other end of the C2 capacitor is grounded, the other end of the C1 capacitor is connected to the input stage circuit, and the other end of the M3 microstrip line is connected to a first stabilizing network.

The C1 capacitor of the invention has the function of isolating direct current and simultaneously prevents direct current from entering the radio frequency input end.

As shown in fig. 9, the first stabilizing network, the second stabilizing network, the third stabilizing network, the fourth stabilizing network, the fifth stabilizing network, the sixth stabilizing network and the seventh stabilizing network of the present invention have the same circuit structure and the same component values, and are all connection circuits of two capacitors and one resistor, and the fourth stabilizing network, the fifth stabilizing network, the sixth stabilizing network and the seventh stabilizing network are connected to each other.

The first stabilizing network comprises a C5 capacitor, an R4 resistor and a C6 capacitor, wherein the C5 capacitor, the R4 resistor and the C6 capacitor are connected in parallel; the second stabilizing network comprises a C15 capacitor, an R15 resistor and a C16 capacitor, wherein the C15 capacitor, the R15 resistor and the C16 capacitor are connected in parallel; the third stabilizing network comprises a C17 capacitor, an R16 resistor and a C18 capacitor, wherein the C17 capacitor, the R16 resistor and the C18 capacitor are connected in parallel; the fourth stabilizing network comprises a C37 capacitor, an R24 resistor and a C38 capacitor, wherein the C37 capacitor, the R24 resistor and the C38 capacitor are connected in parallel; the fifth stabilizing network comprises a C39 capacitor, an R25 resistor and a C40 capacitor, wherein the C39 capacitor, the R25 resistor and the C40 capacitor are connected in parallel; the sixth stabilizing network comprises a C41 capacitor, an R26 resistor and a C42 capacitor, wherein the C41 capacitor, the R26 resistor and the C42 capacitor are connected in parallel; the seventh stabilizing network comprises a C43 capacitor, an R27 resistor and a C44 capacitor, and the C43 capacitor, the R27 resistor and the C44 capacitor are connected in parallel.

As shown in fig. 11, the first matching network of the present invention includes an M5 microstrip line, a C9 microstrip line, a C10 microstrip line, an M6 microstrip line, an M7 microstrip line, a C11 microstrip line, an M8 microstrip line, an M9 microstrip line, and a C12 capacitor, one end of the M5 microstrip line is connected to the drain of the Q1 transistor, the other end of the M5 microstrip line is connected to the C10 capacitor, a C9 capacitor is connected between the M5 microstrip line and the C10 capacitor, the other end of the C9 capacitor is grounded, the other end of the C10 capacitor is connected to the M6 microstrip line and the M7 microstrip line, the M6 microstrip line is connected to the M8 microstrip line and the C11 capacitor, the other end of the C11 capacitor is grounded, the other end of the M8 microstrip line is connected to the second stabilizing network, the M7 microstrip line is connected to the M9 microstrip line and the C12 capacitor, the other end of the C12 capacitor is grounded, and the other end of the M9 microstrip line is connected to the third stabilizing network.

The first matching network of the present invention is used to match the output impedance of the Q1 transistor to the input impedance of the Q2 and Q3 transistors.

As shown in fig. 13, the second matching network of the present invention includes an M10 microstrip line, an M11 microstrip line, an M14 microstrip line, an M15 microstrip line, a C25 capacitor, a C26 capacitor, an M16 microstrip line, an M17 microstrip line, a C27 capacitor, a C30 capacitor, an M18 microstrip line, an M19 microstrip line, an M20 microstrip line, an M21 microstrip line, a C28 capacitor, a C29 capacitor, a C31 capacitor, and a C32 capacitor, where the M32 microstrip line, the M32 capacitor, and the C32 capacitor are sequentially connected in series, the M32 microstrip line and the M32 microstrip line are connected between a second drain circuit M32 microstrip line and the M32 microstrip line, a C32 capacitor is connected between the M32 microstrip line and the M32 microstrip line, the M32 microstrip line and the M32 line are sequentially connected in series, the M32 microstrip line and the M32 line are connected between the M32 line, the M32 capacitor M32 line and the M32 line, the M32 line and the M32 line are connected in series, the other end of the C26 capacitor is grounded, the other end of the C27 capacitor is connected with an M18 microstrip line and an M19 microstrip line respectively, the other end of the M18 microstrip line is connected with a C28 capacitor and a fourth stabilizing network, the other end of the C28 capacitor is grounded, the other end of the M19 microstrip line is connected with a C29 capacitor and a fifth stabilizing network, the other end of the C29 capacitor is grounded, the other end of the C30 capacitor is connected with an M20 microstrip line and an M21 microstrip line respectively, the other end of the M20 microstrip line is connected with a C31 capacitor and a sixth stabilizing network, the other end of the C31 capacitor is grounded, the other end of the M21 microstrip line is connected with a C32 capacitor and a seventh stabilizing network, and the other end of the C32 capacitor is grounded.

The second matching network of the present invention is used to match the output impedance of the Q2 transistor and the Q3 transistor to the input impedance of the Q4 transistor, the Q5 transistor, the Q6 transistor, and the Q7 transistor.

As shown in fig. 14, the third matching network of the present invention includes an M22 microstrip line, an M23 microstrip line, an M24 microstrip line, an M25 microstrip line, an M26 microstrip line, an M27 microstrip line, an M28 microstrip line, an M29 microstrip line, a C45 capacitor, a C46 capacitor, a C47 capacitor, a C48 capacitor, a C49 capacitor, a C50 capacitor, an M30 microstrip line, an M31 microstrip line, a C51 capacitor, a C52 capacitor, an M32 microstrip line, an M33 microstrip line, and an M34 microstrip line, the M22 microstrip line and the M22 microstrip line are connected in series, the other end of the M22 microstrip line is connected to a drain of the Q22 transistor, a C22 capacitor is connected between the M22 microstrip line and the M22 microstrip line, the C22 microstrip line is connected to the ground, the M22 microstrip line is connected to the M22 line, the M22 line is connected to the C22 and the M22 line, the M22 line are connected to the M22 capacitor and the M22 line, the other end of the M24 microstrip line is connected with a drain of a Q6 transistor, a C28 capacitor is connected on a line between the M24 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, the M28 microstrip line is connected with the M28 microstrip line in series, the other end of the M28 microstrip line is connected with a drain of a Q28 transistor, a C28 capacitor is connected on a line between the M28 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, the M28 microstrip line and the M28 microstrip line are connected in series in sequence, a C28 capacitor and an M28 microstrip line are respectively connected between the M28 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, a C28 capacitor is connected between the M28 microstrip line and the M28 microstrip line, the other end of the C28 capacitor is grounded, the M28 microstrip line, the M28 and the M28 microstrip line are connected in series in sequence, The other end of the C48 capacitor is grounded, a C52 capacitor is connected between the M31 microstrip line and the M33 microstrip line, the other end of the C52 capacitor is grounded, the M32 microstrip line and the M33 microstrip line are both connected with the M34 microstrip line, and the M34 microstrip line is respectively connected with the third drain circuit and the output matching network.

The third matching network of the present invention is used to match the output impedance of the Q4 transistor, the Q5 transistor, the Q6 transistor, and the Q7 transistor to the output matching network circuit.

As shown in fig. 16 and 17, the output matching network of the present invention includes an M36 microstrip line, one end of the M36 microstrip line is connected to the third matching network, the other end of the M36 microstrip line is connected to the output stage circuit, the output stage circuit includes a C55 capacitor and an M37 microstrip line, the C55 capacitor and the M37 microstrip line are sequentially connected in series, and the M37 microstrip line is connected to the peripheral circuit.

The C55 capacitor is used for blocking direct current at the output end of the 10W amplifier.

As shown in fig. 19, the circuit structures of the first gate bias circuit, the second gate bias circuit, the third gate bias circuit and the fourth gate bias circuit are completely the same as the values of all components, and all the first gate bias circuit, the second gate bias circuit, the third gate bias circuit and the fourth gate bias circuit are composed of an Rg1 resistor, an Rg resistor, a Cg1 capacitor, a Cg2 capacitor and an Lg inductor, one end of the Lg inductor of the first gate bias circuit is respectively connected with the gate of the Q8 transistor and the first impedance matching network, the Lg inductor is connected in series with the Rg1 resistor, the other end of the Rg1 resistor is connected with the VLg end of a power supply, the Lg inductor and the Rg1 resistor are indirectly connected with the Rg resistor and the Cg1 capacitor respectively, the other end of the Cg1 capacitor is grounded, the resistor is connected in series with the Cg2 capacitor, and the other end of the Cg2 capacitor is grounded. According to the invention, the Rg1 resistor is 2000 ohm and is a current-limiting resistor to prevent the over-large burning of the grid current of the transistor, the Lg microstrip line is used as an inductance to throttle a high-frequency signal to enter a direct-current power supply, the length is 800um, the Cg1 capacitor is a high-frequency decoupling capacitor with the size of 2pF, the Rg resistor is connected with the Cg2 capacitor in series and is used for filtering the interference of the low-frequency signal in the power supply, the Rg resistor is 10 ohm, and the Cg2 capacitor is 3 pF.

As shown in fig. 20, the circuit structures and the component values of the first drain bias circuit, the second drain bias circuit, the third drain bias circuit, the fourth drain bias circuit and the fifth drain bias circuit are completely the same, and the first drain bias circuit, the second drain bias circuit, the third drain bias circuit, the fourth drain bias circuit and the fifth drain bias circuit are all composed of a Rd resistor, a Cd1 capacitor, a Cd2 capacitor and an Ld inductor, one end of the Ld inductor of the first drain bias circuit is connected with the drain of the Q8 transistor and the second impedance matching network, the other end of the Ld inductor is connected with a Cd1 capacitor, the other end of the Cd1 capacitor is grounded, the Rd resistor is connected in series with the Cd2 capacitor, and the other end of the Cd2 capacitor is grounded.

The capacitor Cd1 filters interference of low-frequency signals in a power supply, the resistance of the Rd is 10 ohms, the capacitance Cd2 is 3pF, the Ld microstrip line and the capacitor Cd1 participate in impedance matching of the circuit and inhibit high-frequency signals from entering the direct-current power supply.

As shown in fig. 18, the first impedance matching network of the present invention includes an LL1 microstrip line, a CL1 capacitor, and a CL2 capacitor, where the CL1 capacitor and the LL1 microstrip line are sequentially connected in series, a CL2 capacitor is connected to a connection line between the LL1 microstrip line and the CL1 capacitor, the other end of the CL2 capacitor is grounded, the other end of the CL1 capacitor is connected to a peripheral signal input, and the other end of the LL1 microstrip line is connected to a gate of a Q8 transistor and a first gate bias circuit;

the CL1 capacitor of the invention has the function of isolating direct current and simultaneously prevents direct current from entering the radio frequency input end.

As shown in fig. 21, the second impedance matching network includes an LL2 microstrip line, a CL3 capacitor, and a CL4 capacitor, the CL3 capacitor and the LL2 microstrip line are sequentially connected in series, a CL4 capacitor is connected to a connection line between the LL2 microstrip line and the CL3 capacitor, the other end of the CL4 capacitor is grounded, one end of the CL3 capacitor is connected to the drain of the Q8 transistor and the first drain bias circuit, and the other end of the LL2 microstrip line is connected to the gate of the Q9 transistor and the second gate bias circuit;

the second impedance matching network of the low noise amplifier of the present invention is used to match the output impedance of the Q8 transistor to the input impedance of the Q9 transistor.

As shown in fig. 22, the third impedance matching network includes an LL3 microstrip line, an LL4 microstrip line, a CL5 capacitor, a CL6 capacitor, a CL7 capacitor, and an RL1 resistor, the CL6 capacitor, the LL3 microstrip line, the CL7 capacitor, the RL1 resistor, and the LL4 microstrip line are sequentially connected in series, a CL5 capacitor is connected to a connection line between the LL3 microstrip line and the CL6 capacitor, the other end of the CL5 capacitor is grounded, the other end of the CL6 capacitor is connected to the drain of the Q9 transistor and the second drain bias circuit, the LL3 microstrip line is further connected to the gate of the Q10 transistor and the third gate bias circuit, and the LL4 is connected to the drain of the microstrip line of the Q10 transistor and the third drain bias circuit;

the third impedance matching network of the invention realizes the matching of the output impedance of the Q9 transistor and the input impedance of the Q10 transistor on the one hand, and realizes the gain negative feedback action of the Q10 transistor on the other hand.

As shown in fig. 23, the fourth impedance matching network includes an LL5 microstrip line, a CL8 capacitor, a CL9 capacitor, and an LL6 microstrip line, the LL5 microstrip line, the CL8 capacitor, and the LL6 microstrip line are sequentially connected in series, a CL9 capacitor is connected to a connection line between the LL6 microstrip line and the CL8 capacitor, the other end of the CL9 capacitor is grounded, the other end of the LL6 microstrip line is respectively connected to a drain of the Q10 transistor and a third drain bias circuit, and the other end of the LL6 microstrip line is respectively connected to a gate of the Q11 transistor and a fourth gate bias circuit;

the fourth impedance matching network of the present invention is used to match the output impedance of the Q10 transistor to the input impedance of the Q11 transistor.

As shown in fig. 24, the fifth impedance matching network includes an LL7 microstrip line and a CL10 capacitor LL8 microstrip line, the LL8 microstrip line and the CL10 capacitor are sequentially connected in series, an LL7 microstrip line is connected to a connection line between the LL8 microstrip line and the CL10 capacitor, the other end of the LL7 microstrip line is grounded, the other end of the CL10 capacitor is respectively connected to the drain of the Q11 transistor, the fourth drain bias circuit and the fifth drain bias circuit, and the other end of the LL8 microstrip line is connected to a peripheral circuit.

The fifth impedance matching network of the present invention is used to match the output impedance of the Q11 transistor to the 50 ohm impedance of the peripheral circuit.

Fig. 31 and 32 show the output power (Pout) and the Power Added Efficiency (PAE) of the TR chip 10W amplifier, in the 26GHz-30GHz operating band, the saturation output power of the chip is about 40dBm, and the power added efficiency is greater than 32%; FIG. 29 shows a small signal gain curve for a power amplifier, where the small signal gain of the power amplifier is greater than 22dB in the 26GHz-30GHz operating band, and the gain decreases as the frequency increases; FIGS. 25 and 26 show input and output return curves for a power amplifier with input and output return losses greater than 12dB in the 26GHz-30GHz operating band; FIG. 33 shows the noise figure of the TR chip LNA, which is less than 1.55dB at the 18GHz-22GHz operating band; FIG. 30 shows a small signal gain curve of a TR chip low noise amplifier, where the small signal gain of the power amplifier is greater than 27dB in the 18GHz-22GHz operating band, and the gain decreases as the frequency increases; FIGS. 27 and 28 show input and output return curves for a power amplifier with input and output return loss greater than 10dB at an operating frequency band of 18GHz-22 GHz; the size of the whole TR chip is that the TR chip has the advantages of small size, high output power, small standing wave, high efficiency, low noise coefficient and the like compared with the existing chip, and the integrated chip is a high-performance power amplifier and low-noise amplifier integrated chip suitable for a TR communication system.

The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the spirit and scope of the invention, and these modifications and adaptations should be considered within the scope of the invention.

Claims

1. A high-performance high-power low-noise TR chip is characterized by comprising a 10W amplifier and a low-noise amplifier,

the 10W amplifier is a symmetrical circuit with two parts of circuit structures and component values identical, the power amplifier radio-frequency signal is divided into two paths after entering the 10W amplifier, and the power amplifier radio-frequency signal is amplified by the two parts of symmetrical circuits and then synthesized and output at a radio-frequency output end, so that the power of the power amplifier radio-frequency signal is amplified;

the low-noise amplifier is used for inputting and outputting low-noise radio-frequency signals, and the low-noise amplifiers are sequentially connected through four stages of amplifiers to amplify the power of the low-noise radio-frequency signals;

one of the symmetrical circuits of the 10W amplifier comprises an input matching network, the input matching network is connected with an input stage circuit, the input stage circuit is connected with an external circuit, the other end of the input matching network is connected with a first stabilizing network, a first bias circuit and a second bias circuit are connected between the input matching network and the first stabilizing network, one end of the first bias circuit is connected with a power VG1 end, the other end of the first bias circuit is connected with the second bias circuit, the other end of the second bias circuit is connected with a fourth bias circuit, the second bias circuit is connected with a second bias circuit of another symmetrical circuit, the first stabilizing network is connected with a grid electrode of a Q1 transistor, a source electrode of the Q1 transistor is grounded, a drain electrode of the Q1 transistor is connected with the first matching network, and a first drain electrode circuit is connected between the drain electrode of the Q1 transistor and the first matching network, the first drain circuit is connected with a first drain circuit of another symmetrical circuit, the other end of the first drain circuit is connected with a power VD1 end, the first matching network is connected with a second stabilizing network and a third stabilizing network, a third bias circuit is connected between the first matching network and the second stabilizing network, a fourth bias circuit is connected between the first matching network and the third stabilizing network, the other end of the fourth bias circuit is connected with a fifth bias circuit, the second stabilizing network is connected with the grid electrode of a Q2 transistor, the source electrode of the Q2 transistor is grounded, the drain electrode of the Q2 transistor is connected with the second matching network, the third stabilizing network is connected with the grid electrode of a Q3 transistor, the source electrode of the Q3 transistor is grounded, the drain electrode of the Q3 transistor is connected with the second matching network, and a second drain circuit is connected between the drain electrodes of the Q2 transistor and the Q3 transistor and the second matching network, the second drain circuit is connected with a second drain circuit of another symmetrical circuit, the other end of the second drain circuit is connected with a VD2 end of a power supply, the second matching network is respectively connected with a fourth stabilizing network, a fifth stabilizing network, a sixth stabilizing network and a seventh stabilizing network, a sixth bias circuit is connected between the second matching network and the fourth stabilizing network, a fifth bias circuit is connected between the second matching network and the seventh stabilizing network, the fourth stabilizing network is connected with the grid of a Q4 transistor, the source of the Q4 transistor is grounded, the fifth stabilizing network is connected with the grid of a Q5 transistor, the source of the Q5 transistor is grounded, the sixth stabilizing network is connected with the grid of a Q6 transistor, the source of a Q6 transistor is grounded, the seventh stabilizing network is connected with the grid of a Q7 transistor, the source of the Q7 transistor is grounded, the drain of the Q4 transistor, The drain electrode of the Q5 transistor, the drain electrode of the Q6 transistor and the drain electrode of the Q7 transistor are connected with a third matching network, the third matching network is connected with an output matching network, a third drain electrode circuit is connected between the third matching network and the output matching network, the other end of the third drain electrode circuit is connected with a VD3 end of a power supply, the output matching network is connected with an output stage circuit, and the output stage circuit is connected with an external circuit;

2. The TR chip of claim 1, wherein said 10W amplifier has the same structure of the first, second, third, fourth, fifth and sixth bias circuits, and the component values are the same, the first bias circuit is composed of an R1 resistor, an R2 resistor, an R3 resistor, a C3 capacitor, a C4 capacitor and an L1 inductor, the R1 resistor, the L1 inductor and the R2 resistor are sequentially connected in series, the other end of the R1 resistor is connected with the first stabilizing network, the other end of the R2 resistor is connected with the end of a power source VG1, a C3 capacitor is connected between the R2 resistor and the end of a power supply VG1, the other end of the C3 capacitor is grounded, the resistor R2 is connected with the end of a power source VG1 and is also connected with a resistor R3, the resistor R3 is connected with a capacitor C4 in series, and the other end of the capacitor C4 is grounded;

the second bias circuit is composed of an R6 resistor, an R7 resistor, an R8 resistor, a C19 capacitor, a C20 capacitor and an L2 inductor, the R6 resistor, the L2 inductor and the R7 resistor are sequentially connected in series, the other end of the R6 resistor is connected with the first stabilizing network, the other end of the R7 resistor is respectively connected with the fourth bias circuit and the fifth bias circuit, the R7 resistor is connected with the R7 resistor of another symmetric circuit, the R7 resistor is connected with the C19 capacitor, the other end of the C19 capacitor is grounded, the R7 resistor is further connected with the series circuit of the R8 resistor and the C20 capacitor, and the other end of the C20 capacitor is grounded;

the third bias circuit is composed of an R12 resistor, an R13 resistor, an R14 resistor, a C13 capacitor, a C14 capacitor and an L3 inductor, the R12 resistor, the L3 inductor and the R13 resistor are sequentially connected in series, the other end of the R12 resistor is connected with the second stabilizing network, the other end of the R13 resistor is further connected with a C13 capacitor and an R14 resistor, the other end of the C13 capacitor is grounded, the R14 resistor and the C14 capacitor are connected in series to form a circuit, and the other end of the C14 capacitor is grounded;

the fourth bias circuit is composed of an R9 resistor, an R10 resistor, an R11 resistor, a C21 capacitor, a C22 capacitor and an L4 inductor, the R9 resistor, the L4 inductor and the R10 resistor are sequentially connected in series, the other end of the R9 resistor is connected with a third stabilizing network, the other end of the R10 resistor is connected with a C21 capacitor and the R11 resistor, the other end of the C21 capacitor is grounded, the R11 resistor is connected with the C22 capacitor in series, and the other end of the C22 capacitor is grounded;

the fifth bias circuit is composed of an R21 resistor, an R22 resistor, an R23 resistor, a C33 capacitor, a C34 capacitor and an L6 inductor, the R21 resistor, the L6 inductor and the R22 resistor are sequentially connected in series, the other end of the R21 resistor is connected with a seventh stabilizing network, the other end of the R22 resistor is connected with a C33 capacitor and an R23 resistor, the other end of the C33 capacitor is grounded, the R23 resistor is connected with a C34 capacitor in series, the other end of the C34 capacitor is grounded, the sixth bias circuit is composed of an R18 resistor, an R19 resistor, an R20 resistor, a C35 capacitor, a C36 capacitor and an L5 inductor, the R18 resistor, the L5 inductor and the R19 resistor are sequentially connected in series, the other end of the R18 resistor is connected with a fourth stabilizing network, the other end of the R19 resistor is connected with a C36 capacitor and an R20 resistor, the other end of the C36 capacitor is grounded, and the other end of the R20 resistor is connected with a C20 resistor and a C20 capacitor in series.

3. The TR chip with high performance, high power and low noise as claimed in claim 1, wherein said first drain circuit is composed of R5 resistor, C7 capacitor, C8 capacitor, M4 microstrip line, M37 microstrip line and C56 capacitor, said M4 microstrip line and M37 microstrip line are connected in series, drain of Q1 transistor is connected between M4 microstrip line and M37 microstrip line, another end of M4 microstrip line is connected with VD1 end of power supply, there is C7 capacitor on the line between M4 microstrip line and VD1 end of power supply, another end of C7 capacitor is grounded, another end of M4 microstrip line and VD1 end are connected with R5 resistor and C8 capacitor in series, another end of C8 capacitor is grounded, another end of M37 microstrip line is connected with C56 capacitor, another end of C56 capacitor is grounded, said C56 capacitor is connected with M37 of another symmetrical circuit, said second drain circuit is composed of R17 resistor and R17 resistor, The high-power-efficiency high-power-efficiency high-power-efficiency high-efficiency power-efficiency high-efficiency power-efficiency high-efficiency power-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency power-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency high-efficiency energy-efficiency, and a C53 capacitor and an R28 resistor are connected between the M35 microstrip line and the VD3 end of a power supply, the other end of the C53 capacitor is grounded, the R28 resistor is connected with the C54 capacitor in series, and the other end of the C54 capacitor is grounded.

4. The TR chip of claim 1, wherein the input stage circuit is composed of an M1 microstrip line and a C0 capacitor, the other end of the M1 microstrip line is connected to the input end of an external circuit, the other end of the M1 microstrip line is connected to an input matching network and the C0 capacitor, the other end of the C0 capacitor is grounded, the input matching network comprises an M2 microstrip line, a C1 capacitor, an M3 microstrip line and a C2 capacitor, the C1 capacitor, the M2 microstrip line and the M3 microstrip line are sequentially connected in series, a C2 capacitor is connected to a connection line between the M2 microstrip line and the M3 microstrip line, the other end of the C2 capacitor is grounded, the other end of the C1 capacitor is connected to the input stage circuit, and the other end of the M3 microstrip line is connected to the first stabilizing network.

5. A high-performance high-power low-noise TR chip as claimed in claim 1, wherein said first, second, third, fourth, fifth, sixth and seventh stabilizing networks have the same circuit structure and same component values, and are all a connecting circuit of two capacitors and one resistor, and said fourth, fifth, sixth and seventh stabilizing networks are connected with each other.

6. A high performance high power low noise TR chip as claimed in claim 1, wherein:

the first matching network comprises an M5 microstrip line, a C9 capacitor, a C10 capacitor, an M6 microstrip line, an M7 microstrip line, a C11 capacitor, an M8 microstrip line, an M9 microstrip line and a C12 capacitor, one end of the M5 microstrip line is connected with a drain of a Q1 transistor, the other end of the M5 microstrip line is connected with the C10 capacitor, a C9 capacitor is connected between the M5 microstrip line and the C10 capacitor, the other end of the C9 capacitor is grounded, the other end of the C10 capacitor is respectively connected with the M6 microstrip line and the M7 microstrip line, the M6 microstrip line is respectively connected with the M8 microstrip line and the C11 capacitor, the other end of the C11 capacitor is grounded, the other end of the M8 microstrip line is connected with a second stabilizing network, the M7 microstrip line is respectively connected with the M9 microstrip line and the C12 capacitor, the other end of the C12 capacitor is grounded, and the other end of the M9 microstrip line is connected with a third stabilizing network.

7. The TR chip of claim 2, wherein the second matching network comprises an M10 microstrip line, an M11 microstrip line, an M14 microstrip line, an M15 microstrip line, a C25 capacitor, a C26 capacitor, an M16 microstrip line, an M17 microstrip line, a C27 capacitor, a C30 capacitor, an M18 microstrip line, an M19 microstrip line, an M20 microstrip line, an M21 microstrip line, a C28 capacitor, a C29 capacitor, a C31 capacitor and a C32 capacitor, the M10 microstrip line, the M14 microstrip line, the M16 microstrip line and the C27 capacitor are sequentially connected in series, the M10 microstrip line and the M14 microstrip line are connected between the M14 microstrip line and the M14 microstrip line, a C14 capacitor is connected between the M14 microstrip line and the M14 microstrip line, the other end of the C14 capacitor is grounded, the M14 microstrip line, the M14 line and the M14 line are sequentially connected in series, the M14 line and the M14 line are connected between the M14 line and the M14 line, a C26 capacitor is connected between the M15 microstrip line and the M17 microstrip line, the other end of the C26 capacitor is grounded, the other end of the C27 capacitor is connected with the M18 microstrip line and the M19 microstrip line respectively, the other end of the M18 microstrip line is connected with the C28 capacitor and a fourth stabilizing network, the other end of the C28 capacitor is grounded, the other end of the M19 microstrip line is connected with the C29 capacitor and a fifth stabilizing network, the other end of the C29 capacitor is grounded, the other end of the C30 capacitor is connected with the M20 microstrip line and the M21 microstrip line respectively, the other end of the M20 microstrip line is connected with the C31 capacitor and a sixth stabilizing network, the other end of the C31 capacitor is grounded, the other end of the M21 capacitor is connected with the C32 microstrip line and a seventh stabilizing network, and the other end of the C32 capacitor is grounded.

8. A high-performance high-power low-noise TR chip according to claim 1, wherein the third matching network comprises an M22 microstrip line, an M23 microstrip line, an M24 microstrip line, an M25 microstrip line, an M26 microstrip line, an M27 microstrip line, an M28 microstrip line, an M29 microstrip line, a C45 capacitor, a C46 capacitor, a C47 capacitor, a C48 capacitor, a C49 capacitor, a C50 capacitor, an M30 microstrip line, an M31 microstrip line, a C51 capacitor, a C52 capacitor, an M32 microstrip line, an M33 microstrip line and an M34 microstrip line, the M22 microstrip line and the M26 microstrip line are connected in series, the other end of the M22 microstrip line is connected with a drain of a Q4 transistor, a C46 capacitor is connected between the M22 microstrip line and the M26 microstrip line, the other end of the C46 capacitor is grounded, the M46 and the M46 microstrip line are connected in series, the drain of the Q46 transistor is connected with the M46, a C46 capacitor is connected with the M46, the other end of the C47 capacitor is grounded, the M24 microstrip line and the M28 microstrip line are connected in series, the other end of the M24 microstrip line is connected with the drain of the Q24 transistor, a C24 capacitor is connected on the line between the M24 microstrip line and the M24 microstrip line, the other end of the C24 capacitor is grounded, the M24 microstrip line and the M24 microstrip line are connected in series, the other end of the M24 microstrip line is connected with the drain of the Q24 transistor, a C24 capacitor is connected on the line between the M24 microstrip line and the M24 microstrip line, the other end of the C24 capacitor is grounded, the M24 microstrip line and the M24 microstrip line are connected in series in sequence, the C24 capacitor and the M24 microstrip line are connected between the M24 and the M24 microstrip line respectively, the other end of the C24 capacitor is grounded, the M24 microstrip line and the M24 microstrip line are connected in series, a C48 microstrip line and an M28 microstrip line are respectively connected between the M29 microstrip line and the M31 microstrip line, the other end of the C48 capacitor is grounded, a C52 capacitor is connected between the M31 microstrip line and the M33 microstrip line, the other end of the C52 capacitor is grounded, the M32 microstrip line and the M33 microstrip line are both connected with the M34 microstrip line, and the M34 microstrip line is respectively connected with the third drain circuit and the output matching network.

9. The TR chip with high performance, high power and low noise as claimed in claim 1, wherein said output matching network comprises an M36 microstrip line, one end of said M36 microstrip line is connected to a third matching network, the other end of said M36 microstrip line is connected to an output stage circuit, said output stage circuit comprises a C55 capacitor and an M37 microstrip line, said C55 capacitor and said M37 microstrip line are connected in series, and said M37 microstrip line is connected to a peripheral circuit.

10. The TR chip with high performance, high power and low noise as claimed in claim 1, wherein the circuit structures of the first gate bias circuit, the second gate bias circuit, the third gate bias circuit and the fourth gate bias circuit are completely the same as the values of all components, and all comprise Rg1 resistor, Rg resistor, Cg1 capacitor, Cg2 capacitor and Lg inductor, one end of the Lg inductor of the first gate bias circuit is respectively connected with the gate of the Q8 transistor and the first impedance matching network, the Lg inductor is connected with the Rg1 resistor in series, the other end of the Rg1 resistor is connected with the power VLg end, the other ends of the Lg inductor and the Rg1 resistor are respectively connected with Rg resistor and the Rg1 capacitor indirectly, the other end of the Cg1 capacitor is grounded, the resistor is connected with the Cg2 capacitor in series, and the other end of the Cg2 capacitor is grounded.

11. The TR chip with high performance, high power and low noise as claimed in claim 1, wherein the circuit structures and the values of the components of the first drain bias circuit, the second drain bias circuit, the third drain bias circuit, the fourth drain bias circuit and the fifth drain bias circuit are completely the same, and the first drain bias circuit, the second drain bias circuit, the third drain bias circuit, the fourth drain bias circuit and the fifth drain bias circuit are all composed of a Rd resistor, a Cd1 capacitor, a Cd2 capacitor and an Ld inductor, one end of the Ld inductor of the first drain bias circuit is connected with the drain of the Q8 transistor and the second impedance matching network, the other end of the Ld inductor is connected with a Rd resistor Cd1 capacitor, the other end of the Cd1 capacitor is grounded, the Rd resistor is connected with the Cd2 capacitor in series, and the other end of the Cd2 capacitor is grounded.

12. A high performance high power low noise TR chip as claimed in claim 1,

the first impedance matching network comprises an LL1 microstrip line, a CL1 capacitor and a CL2 capacitor, the CL1 capacitor and the LL1 microstrip line are sequentially connected in series, a CL2 capacitor is connected to a connection line between the LL1 microstrip line and the CL1 capacitor, the other end of the CL2 capacitor is grounded, the other end of the CL1 capacitor is connected with peripheral signal input, and the other end of the LL1 microstrip line is connected with a Q8 transistor gate and a first gate bias circuit;