CN113658931A - 包括垂直接合焊盘的半导体器件 - Google Patents

包括垂直接合焊盘的半导体器件 Download PDF

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Publication number
CN113658931A
CN113658931A CN202110371207.XA CN202110371207A CN113658931A CN 113658931 A CN113658931 A CN 113658931A CN 202110371207 A CN202110371207 A CN 202110371207A CN 113658931 A CN113658931 A CN 113658931A
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Prior art keywords
die
semiconductor
edge
bond
pads
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K.佩里扬南
D.林嫩
J.帕卡穆图
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Publication of CN113658931A publication Critical patent/CN113658931A/zh
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Abstract

本发明题为“包括垂直接合焊盘的半导体器件”。本技术涉及半导体器件，该半导体器件包括半导体管芯，该半导体管芯在管芯的边缘上形成有垂直管芯接合焊盘。在晶片制造期间，垂直接合焊盘块形成在晶片的划线中并且电耦接到半导体管芯的管芯接合焊盘。垂直接合焊盘块在晶片切片期间被切穿，从而使较大垂直取向的焊盘暴露在每个半导体管芯的垂直边缘上。

Description

包括垂直接合焊盘的半导体器件
背景技术
便携式消费电子设备需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储器设备，诸如闪存存储卡，已广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固耐用的设计以及它们的高可靠性和大容量，使得此类存储器设备理想地用于多种电子设备中，包括例如数字相机、数字音乐播放器、视频游戏控制器、PDA、蜂窝电话和固态驱动器。
虽然已知许多不同的封装配置，但是闪存半导体器件通常可以被制造为系统级封装(SIP)或多芯片模块(MCM)，其中多个半导体管芯被安装并互连到小足迹基板的上表面。基板通常可以包括刚性的电介质基部，其具有在一侧或两侧上蚀刻的导电层。常规半导体管芯包括靠近管芯的上表面的边缘的管芯接合焊盘。管芯以阶梯式偏移配置堆叠在基板上，以便允许触及堆栈中的每个管芯的上表面上的管芯接合焊盘。
随着不断存在的在给定大小的半导体封装中增加存储容量的驱动，越来越多的管芯在基板上堆叠在一起。考虑到堆叠管芯的阶梯式偏移，管芯堆栈的总长度在可包括在半导体封装中的半导体管芯的数量和/或长度上变成限制因素。
附图说明
图1是根据本技术的实施方案的用于形成半导体管芯的流程图。
图2是半导体晶片的前视图，示出了该晶片的第一主表面。
图3是晶片的一部分的放大视图，示出了半导体管芯的一部分上的管芯接合焊盘以及形成在管芯之间的划线中的腔。
图4是晶片的一部分的放大视图，示出了半导体管芯的一部分上的管芯接合焊盘以及填充管芯之间的划线中的腔的垂直接合焊盘块。
图5是晶片的一部分的放大视图，示出了耦接到管芯之间的划线中的垂直接合焊盘块的半导体管芯的一部分上的管芯接合焊盘。
图6是示出了根据本技术的各方面的垂直接合焊盘块、管芯接合焊盘和晶片内的内部部件的横截面边缘视图。
图7至图10是示出了根据本技术的另选实施方案的垂直接合焊盘块、管芯接合焊盘和晶片内的内部部件的横截面边缘视图。
图11示出了根据本技术的实施方案的成品半导体管芯的透视图。
图12示出了根据本技术的实施方案的成品半导体管芯的横截面侧视图。
图13是根据本技术的实施方案的用于使用半导体管芯来形成半导体器件的流程图。
图14是根据本技术的实施方案的处于第一制造阶段的半导体器件的透视图，其中半导体管芯堆叠在基板上。
图15是根据本技术的实施方案的处于另一制造阶段的图14的半导体器件的透视图，其中半导体管芯彼此丝焊。
图16是根据本技术的另选实施方案的图14的半导体器件的透视图，其中半导体管芯电耦接。
图17是根据本技术的实施方案的完整的半导体器件的边缘视图。
图18至图19是根据本技术的另选实施方案的半导体器件的透视图。
图20是半导体晶片的前视图，示出了该晶片的第一主表面，其中半导体管芯根据本技术的另选实施方案布置。
图21是图20的晶片的一部分的放大视图，示出了耦接到管芯之间的划线中的垂直接合焊盘块的半导体管芯的一部分上的管芯接合焊盘。
具体实施方式
现在将参见附图描述本技术，附图在实施方案中涉及半导体器件，该半导体器件包括半导体管芯，该半导体管芯在管芯的边缘上形成有垂直接合焊盘。在晶片制造期间，在相邻半导体管芯之间的划线中形成垂直接合焊盘(VBP)块。然后，形成于半导体管芯的上表面上的管芯接合焊盘可电耦接到VBP块。在完成后，晶片可被切片以便切穿VBP块，从而使较大垂直取向的焊盘暴露在每个半导体管芯的垂直边缘上。
为了形成半导体器件，包括垂直接合焊盘的半导体管芯可无偏移地直接彼此上下堆叠，并且然后彼此垂直地丝焊并丝焊到基板。由于半导体管芯未偏移，因此半导体器件的长度不再是可在该器件中使用的半导体管芯的数量或长度的限制因素。
应当理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是周密且完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求书所限定的本发明的范围和实质内。此外，在本发明的以下具体实施方式中，给出了许多具体细节，以便提供对本发明的周密理解。然而，对于本领域的普通技术人员将显而易见的是，本发明可在没有此类具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为±2.5％。
现在将参见图1和图13的流程图以及图2至图12和图14至图21的视图解释本技术的实施方案。最初参见图1的流程图，半导体晶片100可作为可在步骤200中形成的晶片材料的铸块开始。在一个示例中，形成晶片100的铸块可以是根据柴可拉斯基法(CZ)或浮区法(FZ)生长的单晶硅。然而，在其他实施方案中，晶片100可由其他材料并通过其他工艺形成。在步骤202中，半导体晶片100可从铸块上切割下来并且在第一主表面102(图2)和与表面102相对的第二主表面104(图6)两者上抛光以提供平滑表面。
在步骤204中，腔106可以行和/或列形成在晶片100中，诸如例如图3中的晶片100的放大透视图所示。如下所解释的，晶片100可被处理以形成由划线108和110分开的半导体管芯。然而，在实施方案中，可在晶片100中限定半导体管芯或划线之前在晶片100上形成腔106。腔106形成在将成为划线108和/或划线110的部分中。在其他实施方案中，可在晶片100中限定半导体管芯和划线之后形成腔。
在实施方案中，腔106的形状可为正方形或矩形，并且可延伸到大于晶片的最终厚度的深度。例如，如下所解释的，可将晶片减薄至25微米(μm)，并且可将腔形成为30μm。然而，应当理解，在其他实施方案中，腔可形成为更大或更小的深度，包括形成为小于晶片100的最终厚度的深度。
在步骤204中，腔可填充有电导体，诸如例如铝，以形成垂直接合焊盘(VBP)块112，如图4的放大透视图所示。在其他实施方案中，VBP块112可由其他导电材料形成，包括例如铜以及铝和铜的合金。
在步骤206中，第一主表面102可经历各种处理步骤以将晶片100分成相应的半导体管芯114(图2和图5)，并且在第一主表面102上和/或中形成相应半导体管芯114的集成电路。在实施方案中，半导体管芯114可例如是存储器管芯，诸如2D NAND闪存存储器或3DBiCS(位成本缩放)、V-NAND或其他3D闪存存储器，但可使用其他类型的管芯114。这些其他类型的半导体管芯包括但不限于控制器管芯(诸如ASIC)或RAM(诸如SDRAM、DDR SDRAM、LPDDR和GDDR)。图2中晶片100上所示的半导体管芯114的数量是出于示例性目的，并且晶片100可包括比在其他实施方案中所示更多的半导体管芯114。
半导体管芯114可以行和列形成在晶片100上，这些行和列在四个侧面上通过晶片100上的半导体管芯114之间的水平划线108和垂直划线110彼此间隔开。划线108、110被保留为半导体管芯的有源区域周围的边界，其中可进行切割以将半导体管芯彼此切片以及从晶片100切片。在诸如锯切等传统切片技术中，考虑到锯的直径，因此在切割期间从晶片上移除了材料，并且切割还是不能够精确控制的。因此，划线108、110的宽度可例如在70μm和150μm之间的范围内，但它们可比其他实施方案中的宽度更宽或更窄。诸如磨削前的隐形切片等切片方法提供了更严格的公差并且可被控制在几微米内，从而允许更窄的划线108、110。
处理步骤206可包括金属化步骤，该金属化步骤为金属触点镀层，该金属触点包括暴露在第一主表面102上的管芯接合焊盘116。每个半导体管芯114可包括与接合焊盘116相邻的近侧端部114a和与近侧端部114a相对的远侧端部114b。
管芯接合焊盘116可例如由铝形成，但焊盘116在其他实施方案中可由其他材料形成，包括铜以及铝和铜的合金。在实施方案中，每个管芯接合焊盘116可具有大约50μm至70μm的长度和宽度，但在其他实施方案中焊盘116的长度和宽度可发生变化。接合焊盘116(接触层加衬垫)可具有720nm的厚度，但在其他实施方案中，该厚度可更大或更小。每个VBP块112可具有大约50μm至70μm的宽度，并且可具有大约70μm至150μm的长度(横跨划线的宽度)，但在其他实施方案中块112的长度和宽度可发生变化。
每个半导体管芯114上的VBP块112和接合焊盘116的数量是出于示例性目的而示出，并且每个管芯114可包括比其他实施方案中所示更多的VBP块112和管芯接合焊盘116。在实施方案中，对于每个管芯接合焊盘116，存在VBP块112。然而，在其他实施方案中，存在的管芯接合焊盘116比存在的VBP块更多，其中一些管芯接合焊盘116不与VBP块112连接。类似地，在其他实施方案中，存在的VBP块112比存在的管芯接合焊盘116更多，其中一些VBP块112不与管芯接合焊盘116连接。
如所指出的，管芯接合焊盘116可通过内部电互连件路由到限定在半导体管芯114内的集成电路，并且用于向集成电路和从集成电路传输信号。一行VBP块112可形成于每个半导体管芯上与一行管芯接合焊盘116相邻，至少部分地在如图5所示划线108内。如图所示，一行VBP块112可在相邻行半导体管芯114的近侧端部114a和远侧端部114b之间的划线108内形成。在其他实施方案中，VBP块112此外或另选地可形成于划线110中。
根据本技术的各方面，当半导体管芯114从晶片100切片时，VBP块112沿着切片线118(图5)被切断。如图所示，管芯114可被切割，使得划线108、110的一部分保持为每个半导体管芯周围的边界。在沿着切片线118切割之后可作为管芯114的一部分保持在近侧端部114a中的VBP块112的量可发生变化，但在实施方案中，可例如为5μm至100μm。在其他实施方案中，在切片之后VBP块112剩余的部分可大于或小于该量。在切片之后，每个VBP块112的残余部分可在半导体管芯114的远侧端部114b中保持未使用。
图6是近侧端部114a的横截面侧视图，该近侧端部包括例如图2所示的半导体管芯114的芯片区和划线。每个半导体管芯114可包括形成在半导体晶片的芯片区内的基板层122中和/或上的集成电路120。在集成电路120形成之后，可在介电膜128的层中顺序地形成多层金属互连件124和过孔126。如本领域中已知的，金属互连件124、过孔126和介电膜128可使用光刻和薄膜沉积工艺一次形成一层。光刻工艺可包括例如图案定义、等离子体、化学或干法蚀刻和抛光。薄膜沉积工艺可包括例如溅射和/或化学气相沉积。金属互连件124可由多种导电金属形成，包括例如如本领域已知的铜、铝及其合金。过孔可衬有和/或填充有多种导电金属，包括例如如本领域已知的钨、铜和铜合金。
顶部金属化层124(也称为M2层)可用作在其上形成管芯接合焊盘116的基部。根据本技术的各方面，顶部M2层124以及可能还有接合焊盘116本身可继续形成焊盘延伸部130，该焊盘延伸部在接合焊盘116与其相关联的VBP块112之间延伸以将接合焊盘电耦接到这些块。在图6所示的实施方案中，M2层124和接合焊盘116均延伸到接合焊盘和块之间的焊盘延伸部130中。在图7所示的又一实施方案中，接合焊盘116结束，并且仅M2层124继续形成焊盘延伸部130以将接合焊盘116电耦接到VBP块112。
如例如在图5和图6中所见，钝化层134可形成在上介电膜层128的顶部上。钝化层134可被蚀刻以暴露管芯接合焊盘116和VBP块112。如下所解释的，可能有利的是使VBP块112的上表面通过钝化层134暴露，如图5和图6所示。然而，在图8所示的又一实施方案中，钝化层134可不在VBP块112和/或管芯接合焊盘116上方被蚀刻，使得VBP块112和/或管芯接合焊盘116可保持掩埋在钝化层134下方。在块112和焊盘116保持被覆盖的情况下，钝化层138可形成在晶片100的整个表面上方，以在晶片100和相应半导体管芯114上提供平滑的平坦表面，如图8所指示。
在实施方案中，由M2层134组成的焊盘延伸部130以及可能还有接合焊盘116可延伸成与VBP块112的侧表面112a接触，如图6所示。然而，在又一实施方案中，VBP块112可略微凹陷，并且焊盘延伸部130可部分地或完全地在VBP块112的上表面112b上方延伸。在图9中示出了此类实施方案。图9示出了在VBP块112上方延伸的M2层124和接合焊盘116两者，但在其他实施方案中，这些层中的仅一层可在块112上方延伸。在所示和所描述的各种实施方案中的每个实施方案中，焊盘延伸部130用于将接合焊盘116电耦接到其相关联的VBP块112。
在图10所示的又一实施方案中，管芯接合焊盘116可并非通过M2层124，而是通过在钝化层134上方形成的再分布层(RDL)136电耦接到其相应的VBP块112。一旦钝化层134已被蚀刻以暴露接合焊盘116和VBP块112，RDL迹线136就可在钝化层134上方、在接合焊盘116和VBP块112之间形成，以电连接接合焊盘116和VBP块112。在实施方案中，RDL迹线136可由铜、铝或其合金形成。在实施方案中，可在RDL迹线136上方形成又一钝化层138。钝化层138可形成在晶片100的整个表面上方，以在晶片100和相应半导体管芯114上提供平滑的平坦表面，如图10所指示。在其他实施方案中，钝化层138可在VBP块112上方和/或在管芯接合焊盘116上方被蚀刻。
再次参见图6，金属互连件124和过孔126可用于在芯片区内形成导电节点140，以用于在管芯接合焊盘116与集成电路120之间传输信号和电压。金属互连件124和过孔126也可用于在密封环区域内形成密封环142。密封环142可围绕集成电路120和导电节点140，并且例如在晶片100的切片期间提供机械支撑以防止对集成电路120和导电节点140的损坏。
在图3至图10的实施方案中，管芯接合焊盘116可形成在芯片区中、在晶片100上的密封环区域和划线108的内部。VBP块112可形成在晶片100上的划线108中以及可能在划线110中、在密封环区域的外部。芯片区和密封环区域在本文中可一起称为半导体管芯114的有源区域。图5至图10还示出了切片线118，其表示沿着其从晶片100切割半导体管芯114的线。如图所示，切片线118切穿VBP块112，以在从晶片100切片时在每个半导体管芯114的边缘处留下VBP块112的暴露部分，如下所述。
在步骤204和206中形成集成电路120和金属导电层之后，可在步骤210中将一层胶带层合到晶片100的主表面102上。在带胶带表面102抵靠卡盘支撑的情况下，然后可在步骤212中使用施加到第二主表面104的磨轮(未示出)来减薄晶片。磨轮可将晶片100从例如780μm减薄至其最终厚度，例如约25μm至36μm。应当理解，在其他实施方案中，晶片100在回磨削步骤之后可比该范围更薄或更厚。
然后可在步骤214中对晶片进行切片。可使用各种技术来对晶片100进行切片，包括例如使用传统的锯片。如在图6的截面图中所见，锯片可沿着线118切割，直接穿过与每个管芯相关联的VBP块112。在其他实施方案中，锯片可沿着图6的线118a切割，锯切至VBP块112的侧面而不穿过该VBP块。此后，可蚀刻管芯边缘以暴露管芯的侧边缘中的VBP块112。这可用于延长用于切片的锯片的寿命。
在其他实施方案中，可使用其他技术对晶片100进行切片，包括例如磨削前的隐形切片技术和水射流技术。在磨削前的隐形切片中，激光器可使用光学系统(例如包括一个或多个准直透镜)发射聚焦到晶片表面104下方的点的脉冲束。激光器可在划线108、110中以管芯114形状创建多个针点孔。此后，振动或其他应力导致裂纹从孔沿着垂直晶面传播，该垂直晶面延伸到第一主平坦表面102和第二主平坦表面104以对半导体管芯114进行切片。这些裂纹可穿过VBR块112以切穿块112，从而使VBP块112的表面在管芯114的侧边缘中暴露。在使用磨削前的隐形切片的实施方案中，回磨削步骤可在激光处理步骤之后进行，其中回磨削步骤导致裂纹传播以完成对晶片100的切片。
在回磨削步骤212和切片步骤214完成之后，可在步骤216中将附着到柔性切片胶带的一层管芯附接膜(DAF)施加到晶片100的第二主表面104上。然后可将晶片100翻转并支撑在卡盘或其他支撑表面上，并且可在步骤218中移除晶片100的第一主表面102上的层合胶带。一旦处于卡盘上，就可在步骤220中沿着正交轴线拉伸柔性切片胶带以分离各个半导体管芯114，从而允许通过取放机器人移除各个半导体管芯114以用于包括在半导体器件中，如下所述。
图11示出了半导体管芯114在从晶片100切片之后的透视图。管芯114包括在近侧端部114a处的VBP块112和与近侧端部114a向内间隔开的管芯接合焊盘116。如图11和图12的横截面边缘视图所示，VBP块112可有三个表面暴露在管芯114的近侧端部114a处：上表面112b(如上所述)、边缘表面112c和底表面112d。这些表面中的任一个表面或全部表面可接收金属导体125(在图12中以虚线示出)以用于将VBP块112电耦接到另一部件。该金属导体125可例如为球状凸块、丝焊或其他电连接器。
边缘表面112c(在本文中也称为边缘焊盘112c)可沿着管芯114的第一主表面和第二主表面之间的整个垂直边缘延伸，如在回磨削步骤中减薄VBP块的情况一样。如上所述，该边缘可具有例如约25μm至36μm的长度(管芯厚度)。在VBP块形成为小于晶片100的最终厚度的深度的情况下，VBP块可沿着管芯114的第一主表面和第二主表面之间的垂直边缘的一部分延伸。在任一种情况下，本技术的特征都在于VBP块112的边缘焊盘112c足够大以接收常规球状凸块和/或丝焊，如下文所解释。
各个半导体管芯114可被封装在一起以形成半导体器件150，如现在将参见图13的流程图和图14至图19的示意图所解释的。在步骤230中，可将多个半导体管芯114堆叠在基板152上，如图14的透视图中所示。管芯可通过每个管芯的底表面上的DAF层固定到彼此和基板152，固化到B级以将管芯114初步地固定在堆栈154中，并且随后固化到最终C级以将管芯114永久地固定在堆栈154中。
虽然所示实施方案包括4个半导体管芯114-0至114-3，但实施方案可在管芯堆栈154中包括不同数量的半导体管芯，包括例如1个、2个、4个、8个、16个、32个或64个管芯。在堆栈154的其他实施方案中可存在其他数量的管芯。根据本技术的各方面，在包括多个半导体管芯114的情况下，半导体管芯114可无偏移地直接彼此上下堆叠以形成管芯堆栈154。因此，管芯堆栈154在基板152上的足迹与各个管芯114的足迹的大小相同。因此，半导体器件150的长度不再是可在堆栈154中使用的管芯的累积数量的限制因素。然而，如下所解释的，在其他实施方案中，管芯114可以阶梯式偏移配置堆叠。
虽然未示出，但一个或多个无源部件此外可固定到基板152。所述一个或多个无源部件可包括例如一个或多个电容器、电阻器和/或电感器，尽管也设想了其他部件。
半导体管芯114和基板152之间的电互连件可在步骤232中形成。在图15所示的一个实施方案中，半导体管芯114可经由电连接器(诸如固定到VBP块112的垂直边缘焊盘112c的焊线156)彼此电耦接并电耦接到基板152。线156可根据多个方案接合到边缘焊盘112c。然而，在一个实施方案中，丝焊毛细管(未示出)在第一边缘焊盘112c(例如，管芯114-3的边缘焊盘112c-1)上形成球状凸块158。从那里，丝焊毛细管放出线并且在下一相邻半导体管芯(在该示例中为管芯114-2)的对应边缘焊盘112c上形成针脚接合。该过程在整个管芯堆栈上继续进行，直到焊线156将管芯114-3的边缘焊盘112c耦接到管芯114-2的边缘焊盘112c。该过程然后沿堆栈重复，以将管芯114中的每个管芯彼此接合。
一般来讲，丝焊毛细管具有与其所接合的表面正交的中心轴线，使得毛细管可向下压在该表面上以形成丝焊。因此，在形成边缘焊盘112c之间的丝焊时，丝焊毛细管可沿着水平轴线安装。另选地，丝焊毛细管可具有垂直中心轴线，并且管芯堆栈154可被垂直地支撑(其中边缘焊盘112c处于水平面中)以形成接合。
最后一组焊线156可形成于最底部管芯114-0的边缘焊盘112c与基板152的接触焊盘160之间。在实施方案中，边缘焊盘112c被取向成与基板接触焊盘160成90°。考虑到该正交取向，可以多种方式形成最后一组焊线。在一个示例中，丝焊毛细管能够在彼此正交的表面上(例如，在垂直于y轴线取向的边缘焊盘112c上(图15)，以及在垂直于z轴线取向的接触焊盘160上)形成接合。还可能的是，管芯堆栈154中的所有管芯114可在其被安装在基板152上之前彼此丝焊，使得仅需要形成堆栈154的最底部管芯与基板152的接触焊盘160之间的最终接合。
管芯堆栈154可直接安装在基板152上，如图所示。在其他实施方案中，管芯堆栈可通过间隔物(诸如间隔物166，图17)与基板间隔开。这可为丝焊毛细管提供间隙以在最底部管芯114-0与基板152之间形成接合(间隔物还可为直接安装在基板上在管芯堆栈下方的控制器管芯提供空间，如下所解释)。在其他实施方案中，管芯堆栈154与基板之间的接合不需要由最底部管芯114-0制成。其可来自堆栈154中的另一管芯。
具有导电边缘焊盘112c的VBP块112提供其他电连接器方案的可能性。在图16的透视图中示出了一种此类方案。在图16中，相应管芯114中的对应VBP块112的边缘焊盘112c通过所施加的球状凸块158彼此电耦接，以便与相邻管芯114中的边缘焊盘112c重叠。此类球状凸块也可在最底部管芯114-0的边缘焊盘112c与基板152的接触焊盘160之间的正交界面处形成，如图所示。
导电凸块(诸如凸块125，图12)可设在VBP块112的顶表面112b和/或底表面112d上，而不是跨在一对边缘焊盘112c上。例如，导电凸块可设在VBP块112的底表面112d上。管芯可如上所述彼此上下堆叠，并且此后，表面112d上的导电凸块可回流以将对应VBP块中的每个块彼此电耦接并电耦接到基板。在此类实施方案中，凸块125可例如是在晶片级或在管芯114从晶片100切片之后施加的焊料凸块、焊料柱或螺柱凸块。
在又一另选实施方案(未示出)中，可省略导电凸块125、丝焊156和球焊158，并且相应管芯114中的VBP块112可简单地通过彼此上下安装来彼此固定。即是说，当管芯在堆栈154中彼此上下安装时，每个VBP块112的底表面112d(图12)搁置在下一较低管芯的顶表面112b的顶部上。该接触可足以将相应管芯中的对应VBP块彼此电耦接，并且还电耦接到基板的接触焊盘160。
一旦管芯114彼此电耦接并电耦接到基板152，就可在步骤234中将器件150封装在模制化合物162中，如图17所示。在步骤236中，焊料球(未示出)可任选地固定到基板152的下表面，以将半导体器件150固定到主机设备(诸如印刷电路板)。在实施方案中，半导体器件150可被组装在基板152的面板上以实现规模经济。在步骤240中，半导体器件150的制造可通过从此类器件的面板中单切相应半导体器件来完成。
图17所示的半导体器件150还可包括丝焊到基板152上以用于控制半导体管芯114的控制器管芯164(诸如ASIC)。控制器管芯可通过其他方式(包括通过倒装芯片安装)耦接到基板152。控制器管芯还可被制造成包括具有垂直边缘焊盘的VBP块，如上文相对于管芯114所解释的。在所示的示例中，控制器管芯164可以管芯下配置设置，直接安装到基板152。在此类实施方案中，管芯堆栈154可安装在介电间隔物166的顶部上，以为控制器管芯164及其在管芯堆栈下方的丝焊留出空间。另选地，控制器管芯164可安装在管芯堆栈154旁边，或安装在管芯堆栈154的顶部上。
根据本技术的实施方案在管芯的近侧端部114a上形成接合表面或焊盘(112c)提供了若干优点。例如，如上所述，在没有阶梯式偏移的情况下，管芯堆栈154在基板152上的足迹可与单个管芯114的足迹的大小相同，而不管堆栈154中使用了多少管芯。在没有阶梯式偏移的情况下，半导体器件150的长度不再是可在堆栈154中使用的管芯的数量的限制因素。此外，由于管芯不以阶梯式偏移配置进行堆叠，因此每个管芯可具有最大化的长度，例如略微小于半导体封装150的总长度。
虽然将半导体管芯直接彼此上下堆叠具有上述优点，但在其他实施方案中，管芯114可以阶梯式偏移配置进行堆叠。在图18和图19中示出了此类实施方案。在图18中，管芯114彼此阶梯式偏移，并且然后如上所述与焊线156和球状凸块158丝焊。在该实施方案中，可将球状凸块158和丝焊施加到顶表面112b、垂直边缘焊盘112c或顶表面112b和边缘焊盘112c两者，如图18所示。在其他实施方案中，线156可从底表面112d开始从管芯接合到管芯。在此类实施方案中，管芯堆栈和焊线将实际上相对于图18所示的视图翻转。在阶梯式偏移管芯堆栈154的又一实施方案中，可省略焊线，并且在边缘焊盘112c和顶表面112b在堆栈中的相邻管芯上聚集在一起的地方设置球状凸块158。在图19中示出了此类实施方案。
应当理解，图14至图19所示的上述电耦接方案中的任一种方案均可以不同方式彼此组合，以使用VBP块112将半导体管芯114彼此电耦接并电耦接到基板152。
在上述实施方案中，管芯114以行进行布置，每个行面向与图2中的晶片100的前视图所示相同的方向。应当理解，在其他实施方案中，管芯114可以其他配置布置在晶片100上。例如，图20和图21示出了具有镜像行的半导体管芯114的晶片100的前视图和放大局部透视图。在此类实施方案中，第一行半导体管芯114具有近侧端部114a，该近侧端部包括面向近侧端部114a的管芯接合焊盘116，包括第二行半导体管芯114的管芯接合焊盘116。
图20和图21的晶片100可包括第一行半导体管芯(包括半导体管芯114-1)，该第一行半导体管芯通过划线108与第二行半导体管芯(包括半导体管芯114-2)分开(图21中划线108和110可能未相对于彼此按比例绘制)。第一半导体管芯114-1可包括划线108中的一组管芯接合焊盘116-1和相关联的一组VBP块112-1。第二半导体管芯114-2也可包括划线108中的一组管芯接合焊盘116-2和相关联的一行VBP块112-2。根据该实施方案，焊盘延伸部130(在钝化层下方以虚线示出)可将来自管芯114-1的每个管芯接合焊盘116-1和VBP块112-1与来自管芯114-2的管芯接合焊盘116-2和VBP块112-2电耦接。
处于晶片级的此类配置具有以下优点：每对相邻管芯可同时进行测试，从而将测试时间通常缩短一半。即是说，测试探针可降落在焊盘上并且测试通过焊盘延伸部130电耦接到该焊盘的两个管芯。尽管在测试时间方面具有优势，但图20和图21所示相邻对VBP块在其他实施方案中不需要彼此电耦接。
一旦测试完成，就可沿着切割线118对晶片100中的管芯114切片，从而在划线108中的相邻对VBP块之间穿过，因而将VBP块及其相关联的管芯彼此电隔离。这还具有上述优点，即锯片穿过硅而不是VBP块，以延长锯片的寿命。在进行切割之后，可蚀刻近侧边缘以暴露如上所述VBP块112中的每个块的垂直边缘焊盘112c。
总之，本技术的示例涉及半导体管芯，该半导体管芯包括：第一主表面和第二主表面；多个管芯接合焊盘，该多个管芯接合焊盘形成在第一主表面中；边缘，该边缘在第一主表面和第二主表面之间延伸；和在边缘处暴露的多个边缘焊盘，该多个边缘焊盘电耦接到多个管芯接合焊盘，并且多个边缘焊盘被配置为接收球状凸块和/或丝焊。
在另一示例中，本技术涉及半导体器件，该半导体器件包括：多个半导体管芯，该多个半导体管芯在管芯堆栈中安装在一起，该多个半导体管芯中的每个半导体管芯包括：第一主表面和第二主表面，多个管芯接合焊盘，该多个管芯接合焊盘形成在第一主表面中，边缘，该边缘在第一主表面和第二主表面之间延伸，和多个垂直接合焊盘块，该多个垂直接合焊盘块电耦接到多个管芯接合焊盘，多个垂直接合焊盘块中的每个垂直接合焊盘块包括在每个半导体管芯的边缘处暴露的边缘焊盘；和电连接器，该电连接器将多个半导体管芯彼此电耦接。
在又一示例中，本技术涉及半导体器件，该半导体器件包括：多个半导体管芯，该多个半导体管芯在管芯堆栈中安装在一起，该多个半导体管芯中的每个半导体管芯包括：第一主表面和第二主表面，多个管芯接合焊盘，该多个管芯接合焊盘形成在第一主表面中，边缘，该边缘在第一主表面和第二主表面之间延伸，和边缘连接器装置，该边缘连接器装置用于将多个管芯接合焊盘电耦接到半导体管芯中的每个半导体管芯的边缘；和电连接器装置，该电连接器装置用于将多个半导体管芯彼此电耦接。
已出于例证和描述的目的提出本发明的上述具体实施方式。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改和变型都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理以及其实际应用，以由此使得本领域的其他技术人员能够最佳地在各种实施方案中使用具有适合于所构想的特定用途的各种修改的本发明。本发明的范围旨在由所附权利要求书限定。

Claims (22)

1.一种半导体管芯，包括：
第一主表面和第二主表面；
多个管芯接合焊盘，所述多个管芯接合焊盘形成在所述第一主表面中；
边缘，所述边缘在所述第一主表面和所述第二主表面之间延伸；和
多个边缘焊盘，所述多个边缘焊盘在所述边缘处暴露，所述多个边缘焊盘电耦接到所述多个管芯接合焊盘，并且所述多个边缘焊盘被配置为接收球状凸块和/或丝焊。
2.根据权利要求1所述的半导体管芯，其中所述多个边缘焊盘在所述第一主表面和所述第二主表面之间延伸所述边缘的整个高度。
3.根据权利要求1所述的半导体管芯，还包括多个垂直接合焊盘块，每个垂直接合焊盘块包括所述多个边缘焊盘中的边缘焊盘。
4.根据权利要求3所述的半导体管芯，其中所述多个垂直接合焊盘块中的垂直接合焊盘块还包括在所述半导体管芯的所述第一主表面处暴露的第一表面，所述第一表面被配置为接收球状凸块和/或丝焊。
5.根据权利要求4所述的半导体管芯，其中所述垂直接合焊盘块还包括在所述半导体管芯的所述第二主表面处暴露的第二表面，所述第二表面被配置为接收球状凸块和/或丝焊。
6.根据权利要求1所述的半导体管芯，其中在从晶片切片所述半导体管芯时，所述多个边缘焊盘在所述边缘处暴露。
7.根据权利要求1所述的半导体管芯，其中所述多个管芯接合焊盘形成在所述半导体管芯的芯片区中，并且所述多个边缘焊盘形成在所述半导体管芯的划线区中。
8.根据权利要求1所述的半导体管芯，其中所述多个管芯接合焊盘通过所述半导体管芯内的一个或多个金属化层电耦接到所述多个边缘焊盘。
9.根据权利要求1所述的半导体管芯，其中所述多个管芯接合焊盘通过形成于所述第一主表面上方的再分布层电耦接到所述多个边缘焊盘。
10.一种半导体器件，包括：
多个半导体管芯，所述多个半导体管芯在管芯堆栈中安装在一起，所述多个半导体管芯中的每个半导体管芯包括：
第一主表面和第二主表面，
多个管芯接合焊盘，所述多个管芯接合焊盘形成在所述第一主表面中，
边缘，所述边缘在所述第一主表面和所述第二主表面之间延伸，和
多个垂直接合焊盘块，所述多个垂直接合焊盘块电耦接到所述多个管芯接合焊盘，所述多个垂直接合焊盘块中的每个垂直接合焊盘块包括在每个半导体管芯的所述边缘处暴露的边缘焊盘；和
电连接器，所述电连接器将所述多个半导体管芯彼此电耦接。
11.根据权利要求10所述的半导体器件，其中所述多个半导体管芯彼此直接重叠。
12.根据权利要求10所述的半导体器件，其中所述电连接器包括球焊和/或焊线，并且其中所述多个垂直接合焊盘块的所述边缘焊盘被配置为接收所述球焊和/或焊线。
13.根据权利要求10所述的半导体器件，其中所述电连接器包括焊线，所述焊线耦接到所述管芯堆栈中的所述半导体管芯中的每个半导体管芯的所述边缘焊盘。
14.根据权利要求10所述的半导体器件，其中所述电连接器包括球焊，所述球焊耦接到所述管芯堆栈中的相邻半导体管芯的边缘焊盘。
15.根据权利要求10所述的半导体器件，其中所述多个半导体管芯中的每个半导体管芯中的所述多个垂直接合焊盘块还包括暴露在所述半导体管芯中的每个半导体管芯的所述第一主表面和所述第二主表面中的至少一者上的表面。
16.根据权利要求15所述的半导体器件，其中所述电连接器耦接到所述垂直接合焊盘块的暴露在所述半导体管芯中的每个半导体管芯的所述第一主表面和所述第二主表面中的至少一者上的所述表面。
17.根据权利要求16所述的半导体器件，其中所述电连接器包括处于所述垂直接合焊盘块的暴露在所述半导体管芯中的每个半导体管芯的所述第一主表面和所述第二主表面中的一者上的所述表面上的导电凸块。
18.根据权利要求10所述的半导体晶片，还包括处于所述多个半导体管芯中的半导体管芯的所述第一主表面上的钝化层，所述半导体管芯的所述管芯接合焊盘和所述垂直接合块掩埋在所述钝化层下方。
19.一种半导体器件，包括：
多个半导体管芯，所述多个半导体管芯在管芯堆栈中安装在一起，所述多个半导体管芯中的每个半导体管芯包括：
第一主表面和第二主表面，
多个管芯接合焊盘，所述多个管芯接合焊盘形成在所述第一主表面中，
边缘，所述边缘在所述第一主表面和所述第二主表面之间延伸，和
边缘连接器装置，所述边缘连接器装置用于将所述多个管芯接合焊盘电耦接到所述半导体管芯中的每个半导体管芯的所述边缘；和
电连接器装置，所述电连接器装置用于将所述多个半导体管芯彼此电耦接。
20.根据权利要求19所述的半导体器件，其中所述多个半导体管芯彼此直接重叠，所述电连接器装置在所述半导体管芯的所述边缘处固定到所述边缘连接器装置的一部分。
21.一种由晶片制造半导体管芯的方法，所述方法包括以下步骤：
在所述半导体管芯的第一表面处限定多个管芯接合焊盘；
限定穿过所述半导体管芯的厚度形成的多个接合焊盘块；
将所述多个管芯接合焊盘电耦接到所述多个接合焊盘块；
从所述晶片切割所述半导体管芯，在所述切割步骤之后，所述接合焊盘块的垂直表面在所述半导体管芯的边缘处暴露。
22.一种制造半导体器件的方法，所述方法包括以下步骤：
形成多个半导体管芯，每个管芯通过以下步骤形成：
将多个管芯接合焊盘与多个接合焊盘块电耦接，以及
从晶片切割所述半导体每个半导体管芯，在所述切割步骤之后，所述接合焊盘块的垂直表面在每个半导体管芯的边缘处暴露；
将所述多个半导体管芯彼此堆叠；以及
通过将电连接器固定到所述垂直表面来电耦接所述多个半导体管芯。
CN202110371207.XA 2020-05-12 2021-04-07 包括垂直接合焊盘的半导体器件 Pending CN113658931A (zh)

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