CN113645770A - Method for solving OSP and gold immersion potential difference plating leakage - Google Patents
Method for solving OSP and gold immersion potential difference plating leakage Download PDFInfo
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- CN113645770A CN113645770A CN202110943207.2A CN202110943207A CN113645770A CN 113645770 A CN113645770 A CN 113645770A CN 202110943207 A CN202110943207 A CN 202110943207A CN 113645770 A CN113645770 A CN 113645770A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The embodiment of the invention discloses a method for solving the problem of potential difference plating leakage of OSP and immersion gold, which comprises the following steps: s1, preparing a substrate with a conducting circuit formed, and carrying out solder mask treatment on the substrate to form a solder mask layer which covers the surface of the outer copper layer and is provided with a first windowing area, so that the outer copper layer and the PAD at the position corresponding to the first windowing area are exposed; and S2, performing gold immersion treatment on the substrate. In the embodiment of the invention, the first windowing area plays a role in balancing potential, so that the phenomenon of poor potential difference plating leakage generated in the gold immersion process of the circuit board is obviously reduced, and the circuit board can be successfully produced in mass; on the other hand, the first windowing area only changes the appearance design of the circuit board and does not change the functional design of the product.
Description
Technical Field
The invention relates to the field of circuit board manufacturing, in particular to a method for solving the problem of potential difference plating leakage of OSP and gold immersion.
Background
At present, with the rapid development of the electronic technology industry, the corresponding PCB board circuit design integration level is higher and higher, and the precision of the dimension requirements of the PAD in the OSP and the immersion gold processes of PCB surface treatment is extremely high according to different purposes of products.
And because of the nickel immersion gold reaction characteristic: ni+Electrons released by H & lt + & gt adsorbed on the copper surface are intercepted and oxidized into metallic nickel to be deposited on the copper surface, and when a wire is connected to an inner-layer circuit large copper surface (GND), because charge-effect electrons migrate to the unreacted copper surface (GND) from the wire, the electron density on the copper surface (small pad) in a liquid medicine is reduced, namely the potential during reaction is reduced, the nickel deposition is not easy to carry out, and therefore potential-difference skip plating (skip) or a thin thickness is formed.
The existing PCB for signal transmission has the ratio of the gold immersion area to the OSP area of 0.1: 99.9; only 1PAD of gold deposition is needed in each set unit, wherein the gold deposition PAD area is 0.2 x 0.3 (namely 0.06 square millimeter), and the ratio of the sum of the surface area of the inner copper layer and the surface area of the outer copper layer which are interconnected to each other is 1: 60, potential difference skip plating appears after the gold immersion process, the appearance is blackened after the OSP process, and the result measurement shows that the potential difference skip plating PAD has the nickel thickness of 2.0 mu m, the gold thickness of 0.023 mu m and the nickel corrosion of 60 percent; the normal PAD has a Ni thickness of 3.5 μm, a Au thickness of 0.056 μm, and a Ni corrosion of 10%, i.e., the product exceeds the gold immersion process capability and can not be produced in mass production, so a method for solving the problem of potential difference plating leakage of OSP and gold immersion is urgently needed.
Disclosure of Invention
The invention aims to provide a method for solving the problem of potential difference plating leakage of OSP and gold immersion, and aims to solve the problem of poor potential difference plating leakage of a circuit board in a gold immersion process.
In order to solve the technical problems, the invention aims to realize the following technical scheme: the method for solving the problem of OSP and gold immersion potential difference plating leakage comprises the following steps:
s1, preparing a substrate with a conducting circuit formed, and carrying out solder mask treatment on the substrate to form a solder mask layer which covers the surface of the outer copper layer and is provided with a first windowing area, so that the outer copper layer and the PAD at the position corresponding to the first windowing area are exposed;
and S2, performing gold immersion treatment on the substrate.
Furthermore, the first windowing region is arranged at the screw fixing hole openings at the four top corners of the substrate.
Further, before the step S1, the method further includes the following steps:
s01, measuring and recording the surface area of the inner copper layer, the surface area of the outer copper layer and the PAD area of the PAD of the substrate, and calculating and judging whether the ratio of the PAD area of the PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer is more than or equal to 1: 150;
if the ratio of the PAD area to the sum of the inner copper layer surface area and the outer copper layer surface area is greater than or equal to 1:150, executing step S1 and the following steps:
s11, arranging a second windowing region on the solder mask layer;
if the ratio of the PAD area of the bonding PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer is less than 1:150, only step S1 is executed.
Furthermore, the second windowing areas are provided with a plurality of second windowing areas, and the second windowing areas are located on the peripheral edges of the solder mask layer.
Further, the steps S1 and S2 include the following steps:
s100, performing sand blasting treatment on the substrate;
s101, fixing the substrate by using a hanging rack, and then removing oil stains on the surface of the substrate;
s102, cleaning the substrate by using hot water, and removing oil removing liquid medicine on the substrate;
s103, carrying out micro-etching on the substrate;
s104, cleaning the substrate by using hot water, and removing the micro-etching liquid medicine on the surface of the substrate;
s105, performing presoaking pickling on the substrate;
s106, carrying out activation treatment on the substrate to form a palladium layer on the surface of the substrate;
s107, sequentially carrying out water washing, acid washing and water washing on the substrate to remove the activating liquid medicine on the surface of the substrate;
s108, catalyzing the palladium layer on the substrate to form a nickel layer;
and S109, washing the substrate with water to remove the nickel bath liquid medicine on the substrate.
Further, the control parameters of the blasting in the step S100 are: the sand blasting concentration is controlled to be 13-23 percent, and the sand blasting linear speed is controlled to be 2-3 m/min.
Further, the control parameters of the activation in step S106 are: the activation time is controlled at 200s, and the activated palladium ion concentration is controlled at 100-.
Further, the control parameters of the catalysis in the step S108 are: the catalysis time is controlled within 1300s-1500s, the catalysis temperature is controlled within 70-90 ℃, the pH value of the nickel tank is controlled within 4.3-4.0, the concentration of nickel ions in the nickel tank is controlled within 4.6-5g/L, and the concentration of a nickel tank reducing agent is controlled within 25-35 g/L.
Further, the control parameters of the immersion gold in the step S2 are: the gold immersion time is controlled within 280s-320s, the gold immersion temperature is controlled within 78-86 ℃, the pH value of the gold groove is controlled within 6-7, and the gold ion concentration of the gold groove is controlled within 0.6-0.7 g/L.
Further, the step S2 includes the following steps:
and (3) cleaning the substrate after the gold precipitation treatment by using water, removing the gold tank liquid medicine on the surface of the substrate, and recovering gold in the wastewater.
The embodiment of the invention provides a method for solving the problem of potential difference plating leakage of OSP and immersion gold, which comprises the following steps: s1, preparing a substrate with a conducting circuit formed, and carrying out solder mask treatment on the substrate to form a solder mask layer which covers the surface of the outer copper layer and is provided with a first windowing area, so that the outer copper layer and the PAD at the position corresponding to the first windowing area are exposed; and S2, performing gold immersion treatment on the substrate. In the embodiment of the invention, the first windowing area plays a role in balancing potential, so that the phenomenon of poor potential difference plating leakage generated in the gold immersion process of the circuit board is obviously reduced, and the circuit board can be successfully produced in mass; on the other hand, the first windowing area only changes the appearance design of the circuit board and does not change the functional design of the product.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of a method for solving the problem of OSP and gold immersion potential difference plating leakage according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a substrate according to an embodiment of the present invention;
FIG. 3 is a sub-flowchart of a method for solving the problem of OSP and gold immersion potential difference leakage plating according to an embodiment of the present invention.
The labels in the figures illustrate:
1. a substrate; 2. a first windowed area; 3. a second windowed area.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In the prior art, the ratio of the area of the gold immersion PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer which are interconnected is more than 1:150, the circuit board begins to have the phenomenon of poor potential difference plating leakage, and the actual situation is shown as the following data:
table one:
setting the area of the gold immersion PAD as X, the surface area of the inner copper layer as Y, the surface area of the outer copper layer as Z, and setting the area ratio in the table I as X: (Y + Z).
According to the first table, it can be seen that: the ratio of the area of the gold immersion PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer which are interconnected is more than 1:150, the circuit board begins to have the phenomenon of poor potential difference leakage plating, and the ratio of the gold PAD area to the sum of the surface areas of the inner copper layer and the outer copper layer of the interconnection is more than 1: at 200 hours, the reject ratio of the circuit board reaches more than 60%, that is, most of the produced circuit boards cannot be delivered from factories, and further, the production and the manufacture of the circuit boards are seriously influenced.
With reference to fig. 1 and fig. 2, an embodiment of the present invention provides a method for solving OSP and gold immersion potential difference skip plating, comprising the following steps:
s1, preparing a substrate 1 with a conducting circuit formed, and carrying out solder mask treatment on the substrate 1 to form a solder mask layer which covers the surface of the outer copper layer and is provided with a first windowing area 2, so as to expose the outer copper layer and the PAD at the position corresponding to the first windowing area 2;
and S2, performing gold immersion treatment on the substrate 1.
The first windowing region 2 is arranged at the screw fixing hole openings at the four vertex angles of the substrate 1, namely, the first windowing region 2 only changes the appearance design of the circuit board and does not change the functional design of the product, so that the method is excellent in practicability and extremely high in applicability.
When the substrate 1 and the inner copper layer which is interconnected with the substrate are designed into a dry film before gold immersion, the screw fixing hole connected with the inner copper layer is designed to be windowed, so that the function of balancing potential is achieved in the gold immersion process, the phenomenon of poor potential difference plating leakage of the circuit board in the gold immersion process is remarkably reduced, and the circuit board can be produced in large quantity smoothly. In one embodiment, the first windowed area 2 is used as a part of the equilibrium potential during the immersion of gold, and the outer copper layer is not covered with the dry film in the first windowed area 2 according to the design during the production of the selective dry film.
In a specific embodiment, before the step S1, the method further includes the following steps:
s01, measuring and recording the surface area of the inner copper layer, the surface area of the outer copper layer and the PAD area of the PAD of the substrate 1, and calculating and judging whether the ratio of the PAD area of the PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer is more than or equal to 1: 150;
if the ratio of the PAD area of the bonding PAD to the sum of the surface areas of the inner copper layer and the outer copper layer is greater than or equal to 1:150, performing step S1 and the following steps:
s11, arranging a second windowing region 3 on the solder mask layer;
if the ratio of the PAD area to the sum of the inner copper layer surface area and the outer copper layer surface area is less than 1:150, only step S1 is executed.
According to the data in the table I, the ratio of the area of the gold immersion PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer which are interconnected is more than 1:150, the circuit board begins to have the phenomenon of poor potential difference plating leakage, but in practical conditions, the ratio of the area of the gold immersion PAD to the sum of the surface areas of the inner copper layer and the outer copper layer of the interconnection is less than 1:150, the circuit board also has poor potential difference plating leakage phenomenon, only the reject ratio is low, and the ratio of the area of the gold-deposited PAD to the sum of the surface areas of the inner copper layer and the outer copper layer of the interconnection is smaller than 1:150 through the arrangement of the first windowing area 2, so that the poor potential difference plating leakage phenomenon of the circuit board is avoided, and the yield of the circuit board is improved.
When the ratio of the area of the gold immersion PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer which are interconnected is more than 1:150, the defective rate of the circuit board is significantly increased, so the second windowing region 3 provided in this embodiment can further balance the potential, so as to increase the yield of the circuit board.
In a specific embodiment, the second windowing regions 3 are provided in plurality, and the second windowing regions 3 are located at the peripheral edges of the solder resist layer. The second windowing area 3 is used as a part of balance potential during gold immersion, and the solder mask production does not cover the solder mask according to the design of the second windowing area 3.
In order to prove that the method of the embodiment of the invention can effectively improve the yield of the circuit board, the following tests are carried out,
a detection step:
100 circuit boards produced by the embodiment of the present invention were prepared, each circuit board was tested for performance, and the average value of the test data was recorded in the following table two:
table two:
| deposit control project | Technical requirements | Average value of detection | Determination |
| Thickness of nickel | 3-5μm | 3.89 | ACC |
| Thickness of gold | 0.04-0.06μm | 0.052 | ACC |
| P content | 7-11％ | 8.90％ | ACC |
| Corrosion of nickel | <30％ | 11％ | ACC |
| Degree of porosity | No color change | No color change | ACC |
According to the second table, the problem of potential difference plating leakage of OSP and gold immersion in the prior art process is solved according to the embodiment of the invention, so that mass production of the circuit board can be realized; on the other hand, the positions of the first windowing region 2 and the second windowing region 3 in the embodiment of the invention only change the appearance of the circuit board, and do not affect the functions of the circuit board, so that the method has better practicability and applicability.
With reference to fig. 3, in the present embodiment, the following steps are included between step S2 and step S1:
s100, performing sand blasting treatment on the substrate 1;
in an embodiment, the control parameters of the blasting in step S100 are: the sand blasting concentration is controlled to be 13-23 percent, and the sand blasting linear speed is controlled to be 2-3 m/min; and (3) carrying out sand blasting treatment on the windowed substrate 1, and cleaning the PAD copper surface oxide on the substrate 1 to form roughness on the PAD copper surface and increase the bonding force between the PAD copper surface and a nickel groove.
S101, fixing the substrate 1 by using a hanging rack, and then removing oil stains on the surface of the substrate 1;
s102, cleaning the substrate 1 with hot water to remove the degreasing agent on the substrate 1;
s103, carrying out micro-etching on the substrate 1;
in step S103, the PAD copper surface oxide is cleaned and the roughness is formed on the copper surface, so as to increase the bonding force between the copper layer and the nickel bath.
S104, cleaning the substrate 1 by using hot water, and removing the micro-etching liquid medicine on the surface of the substrate 1;
s105, performing presoaking and pickling on the substrate 1;
the step S105 is performed to ensure that the acidity of the activation slot is not reduced.
S106, carrying out activation treatment on the substrate 1 to form a palladium layer on the surface of the substrate 1;
in an embodiment, the control parameters of the activation in step S106 are: the activation time is controlled at 200s, and the activated palladium ion concentration is controlled at 100-. Wherein the formed palladium layer is used as a catalyst in the reduction of the nickel layer.
S107, sequentially carrying out water washing, acid washing and water washing on the substrate 1 to remove the activating liquid medicine on the surface of the substrate 1;
s108, catalyzing the palladium layer on the substrate 1 to form a nickel layer;
in one embodiment, the control parameters of the catalysis in step S108 are: the catalysis time is controlled within 1300s-1500s, the catalysis temperature is controlled within 70-90 ℃, the pH value of the nickel tank is controlled within 4.3-4.0, the concentration of nickel ions in the nickel tank is controlled within 4.6-5g/L, and the concentration of a nickel tank reducing agent is controlled within 25-35 g/L.
S109, washing the substrate 1 with water to remove the nickel bath solution on the substrate 1.
In an embodiment, the control parameters of the immersion gold in step S2 are: the gold immersion time is controlled within 280s-320s, the gold immersion temperature is controlled within 78-86 ℃, the pH value of the gold groove is controlled within 6-7, and the gold ion concentration of the gold groove is controlled within 0.6-0.7 g/L.
In one embodiment, the step S2 is followed by the steps of:
and cleaning the substrate 1 after the gold precipitation treatment by using water, removing the gold tank liquid medicine on the surface of the substrate 1, and recovering gold in the wastewater so as to achieve the purpose of saving resources.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for solving the problem of OSP and gold immersion potential difference plating leakage is characterized by comprising the following steps:
s1, preparing a substrate (1) with a conducting circuit formed, and carrying out solder mask treatment on the substrate (1) to form a solder mask layer which covers the surface of the outer copper layer and is provided with a first windowing area (2), so as to expose the outer copper layer and PAD at the position corresponding to the first windowing area (2);
s2, performing gold immersion treatment on the substrate (1).
2. The method of resolving OSP and sinker potential deplating as set forth in claim 1, wherein: the first windowing region (2) is arranged at screw fixing hole openings at four top corners of the substrate (1).
3. The method of resolving OSP and sinker potential deplating as set forth in claim 2, wherein: before the step S1, the method further includes the following steps:
s01, measuring and recording the surface area of the inner copper layer, the surface area of the outer copper layer and the PAD area of the PAD of the substrate (1), and calculating and judging whether the ratio of the PAD area of the PAD to the sum of the surface area of the inner copper layer and the surface area of the outer copper layer is more than or equal to 1: 150;
if the ratio of the PAD area of the bonding PAD to the sum of the surface areas of the inner copper layer and the outer copper layer is greater than or equal to 1:150, performing step S1 and the following steps:
s11, arranging a second windowing region (3) on the solder mask layer;
if the ratio of the PAD area to the sum of the inner copper layer surface area and the outer copper layer surface area is less than 1:150, only step S1 is executed.
4. The method of resolving OSP and sinker potential deplating according to claim 3, wherein: the second windowing areas (3) are arranged in a plurality of numbers, and the second windowing areas (3) are located on the periphery of the solder mask layer.
5. The method of resolving OSP and sinker potential deplating according to claim 1, wherein between said steps S1 and S2, comprising the steps of:
s100, performing sand blasting treatment on the substrate (1);
s101, fixing the substrate (1) by using a hanging rack, and then removing oil stains on the surface of the substrate (1);
s102, cleaning the substrate (1) with hot water, and removing the degreasing agent on the substrate (1);
s103, carrying out micro-etching on the substrate (1);
s104, cleaning the substrate (1) by using hot water, and removing the micro-etching liquid medicine on the surface of the substrate (1);
s105, performing presoaking pickling on the substrate (1);
s106, carrying out activation treatment on the substrate (1) to form a palladium layer on the surface of the substrate (1);
s107, sequentially carrying out water washing, acid washing and water washing on the substrate (1) to remove the activating liquid medicine on the surface of the substrate (1);
s108, catalyzing a palladium layer on the substrate (1) to form a nickel layer;
s109, washing the substrate (1) with water to remove the nickel bath liquid medicine on the substrate (1).
6. The method according to claim 5, wherein the parameters for controlling the sand blasting in step S100 are: the sand blasting concentration is controlled to be 13-23 percent, and the sand blasting linear speed is controlled to be 2-3 m/min.
7. The method of resolving OSP and sinker potential deplating according to claim 5, wherein: the control parameters of the activation in step S106 are: the activation time is controlled at 200s, and the activated palladium ion concentration is controlled at 100-.
8. The method of resolving OSP and sinker potential deplating according to claim 5, wherein: the control parameters of the catalysis in the step S108 are as follows: the catalysis time is controlled within 1300s-1500s, the catalysis temperature is controlled within 70-90 ℃, the pH value of the nickel tank is controlled within 4.3-4.0, the concentration of nickel ions in the nickel tank is controlled within 4.6-5g/L, and the concentration of a nickel tank reducing agent is controlled within 25-35 g/L.
9. The method of resolving OSP and sinker potential deplating as set forth in claim 1, wherein: the control parameters of the immersion gold in the step S2 are as follows: the gold immersion time is controlled within 280s-320s, the gold immersion temperature is controlled within 78-86 ℃, the pH value of the gold groove is controlled within 6-7, and the gold ion concentration of the gold groove is controlled within 0.6-0.7 g/L.
10. The method of resolving OSP and sinker potential deplating according to claim 1, wherein said step S2 is followed by the steps of:
and (3) cleaning the substrate (1) after the gold precipitation treatment by using water, removing the gold groove liquid medicine on the surface of the substrate (1), and recovering gold in the wastewater.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002016347A (en) * | 2000-06-27 | 2002-01-18 | Mitsui Chemicals Inc | Method for manufacturing printed circuit board |
| CN105208797A (en) * | 2015-08-11 | 2015-12-30 | 深圳崇达多层线路板有限公司 | Manufacture method of semi-plugged nickel and gold immersion |
| CN107231753A (en) * | 2017-06-23 | 2017-10-03 | 深圳崇达多层线路板有限公司 | A kind of golden method of the heavy nickel for improving plating leakage |
| US20180177057A1 (en) * | 2018-01-08 | 2018-06-21 | Kunshan TVS Electronic Technology Co.,Ltd | Gold-plating etching process for 5g communication high-frequency signal boards |
| CN210381520U (en) * | 2019-06-27 | 2020-04-21 | 江苏普诺威电子股份有限公司 | Solder-resistant windowing structure of printed circuit board before nickel-gold electroplating |
| CN113141723A (en) * | 2021-03-18 | 2021-07-20 | 深圳市景旺电子股份有限公司 | Surface treatment method of printed circuit board and printed circuit board |
-
2021
- 2021-08-17 CN CN202110943207.2A patent/CN113645770B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002016347A (en) * | 2000-06-27 | 2002-01-18 | Mitsui Chemicals Inc | Method for manufacturing printed circuit board |
| CN105208797A (en) * | 2015-08-11 | 2015-12-30 | 深圳崇达多层线路板有限公司 | Manufacture method of semi-plugged nickel and gold immersion |
| CN107231753A (en) * | 2017-06-23 | 2017-10-03 | 深圳崇达多层线路板有限公司 | A kind of golden method of the heavy nickel for improving plating leakage |
| US20180177057A1 (en) * | 2018-01-08 | 2018-06-21 | Kunshan TVS Electronic Technology Co.,Ltd | Gold-plating etching process for 5g communication high-frequency signal boards |
| CN210381520U (en) * | 2019-06-27 | 2020-04-21 | 江苏普诺威电子股份有限公司 | Solder-resistant windowing structure of printed circuit board before nickel-gold electroplating |
| CN113141723A (en) * | 2021-03-18 | 2021-07-20 | 深圳市景旺电子股份有限公司 | Surface treatment method of printed circuit board and printed circuit board |
Non-Patent Citations (2)
| Title |
|---|
| 戴晖,刘喜科，林人道: "印制电路板化学金漏镀浅析", 《印制电路信息》 * |
| 胡光辉; 潘湛昌; 魏志钢: "PCB化学镀镍漏镀现象分析", 《印制电路信息》 * |
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