CN113629165A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113629165A
CN113629165A CN202010376870.4A CN202010376870A CN113629165A CN 113629165 A CN113629165 A CN 113629165A CN 202010376870 A CN202010376870 A CN 202010376870A CN 113629165 A CN113629165 A CN 113629165A
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layer
forming
gate
semiconductor structure
wafer
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俞宏俊
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a wafer substrate; forming a light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate; and etching the non-optical path transmission region of the optical transmission layer to form a first groove, wherein the depth of the first groove is at least equal to the thickness of the optical transmission layer. According to the forming method of the semiconductor structure provided by the embodiment of the invention, the first groove in the optical transmission layer is arranged, namely the optical transmission layer is divided, so that the area of the optical transmission layer connected into a whole is reduced, the stress of the optical transmission layer can be released, the curvature of the semiconductor structure caused by the stress action is further reduced, the flatness of the semiconductor structure is improved, and the vacuum degree requirement in the processing process of the semiconductor structure is ensured.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
The silicon-based optoelectronic chip is to be deployed in a high-speed signal transmission system to replace the existing copper stranded wire transmission. The performance bottleneck of high performance computing systems has moved from processors to communication infrastructure, and optical interconnects can provide high bandwidth, low latency solutions to address the challenges of future computing system bandwidth scalability.
However, once the thickness of the multilayer film structure of the silicon-based optoelectronic chip is larger than
Figure BDA0002480446840000011
The wafer is bent, the flatness is reduced, and along with the thickening of the film structure, when the wafer bending exceeds more than 200nm, the degree of vacuum is insufficient due to the reduction of the flatness, so that the machine can give an alarm and the wafer cannot pass goods.
In view of the above, how to reduce the curvature of the semiconductor structure is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which reduce the curvature of the semiconductor structure.
In order to solve the above problem, an embodiment of the present invention further provides a method for forming a semiconductor structure, including:
providing a wafer substrate;
forming a light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate;
and etching the non-optical path transmission region of the optical transmission layer to form a first groove, wherein the depth of the first groove is at least equal to the thickness of the optical transmission layer.
Accordingly, an embodiment of the present invention provides a semiconductor structure, including:
a wafer substrate;
the light transmission layer covers the front surface of the wafer substrate;
the non-optical path transmission area of the optical transmission layer is provided with a first groove, and the depth of the first groove is at least equal to the thickness of the optical transmission layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the method for forming the semiconductor structure comprises the steps of firstly providing a wafer substrate, then forming a light transmission layer on the front surface of the wafer substrate, and etching a non-light path transmission area of the light transmission layer to form a first groove, wherein the depth of the first groove is at least equal to the thickness of the light transmission layer, so that the arrangement of the first groove in the light transmission layer is equivalent to the division of the light transmission layer, the area of the light transmission layer connected into a piece is reduced, the stress of the light transmission layer can be released, the curvature of the semiconductor structure caused by the stress action is reduced, the flatness of the semiconductor structure is improved, and the requirement of vacuum degree in the processing process of the semiconductor structure is ensured.
Drawings
Fig. 1 to 8 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of a semiconductor structure according to an embodiment of the invention.
Detailed Description
As known in the background art, the thickness of the multilayer film structure of the silicon-based optoelectronic chip>
Figure BDA0002480446840000021
The wafer can be bent, the flatness is reduced, and along with the thickening of the film structure, when the wafer bending exceeds more than 200nm, the degree of vacuum is insufficient due to the reduction of the flatness, so that the machine can give an alarm and the goods cannot be delivered.
In order to reduce the curvature of the semiconductor structure, an embodiment of the invention provides a method for forming a semiconductor structure, which includes the steps of firstly providing a wafer substrate, then forming a light transmission layer on the front surface of the wafer substrate, and etching a non-light path transmission area of the light transmission layer to form a first groove, wherein the depth of the first groove is at least equal to the thickness of the light transmission layer, so that the arrangement of the first groove in the light transmission layer is equivalent to the division of the light transmission layer, the area of the light transmission layer connected into a whole is reduced, the stress of the light transmission layer can be released, the curvature of the semiconductor structure caused by the stress action is further reduced, the flatness of the semiconductor structure is improved, and the vacuum requirement in the processing process of the semiconductor structure is ensured.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Referring to fig. 1 to 8, fig. 1 to 8 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention. The semiconductor structure provided by the embodiment of the invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1-3, a wafer substrate 10 (shown in fig. 3) is provided. The wafer substrate 10 includes a wafer 300, a first gate structure 100 and a second gate structure 200, wherein the first gate structure 100 covers a front surface of the wafer 300, and the second gate structure 200 covers a back surface of the wafer 300. In this embodiment, the wafer 300 is a silicon substrate. In other embodiments, the wafer 300 may also be a substrate made of other materials, such as a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate.
It is understood that the front side of the wafer 300 described herein refers to the top surface of the wafer 300 in fig. 1; similarly, the back side of the wafer described herein refers to the bottom side of the wafer 300 in fig. 1.
Specifically, referring to fig. 1 to 3, the forming process of the wafer substrate 10 includes:
the first gate structure 100 is formed on the front surface of the wafer 300, and the second gate structure 200 is formed on the back surface of the wafer 300.
In one embodiment, the first gate structure 100 may be formed by the following steps, including:
as shown in fig. 1, first, a first oxide layer 101 is formed, and the first oxide layer 101 covers the front surface of the wafer 300.
The material of the first oxide layer 101 is silicon oxide. In one embodiment, the forming process of the first oxide layer 101 may be a furnace growth process, and in other embodiments, the first oxide layer may also be formed by chemical deposition.
Then, a first gate layer 111 is formed, the first gate layer 111 covers the first oxide layer 101, the material of the first gate layer 111 is polysilicon, in an embodiment, the formation process of the first gate layer 111 is a furnace growth process, and in other embodiments, the first gate layer may also be formed by chemical deposition.
Forming a second oxide layer 102, wherein the second oxide layer 102 covers the first gate layer 111; the second oxide layer 102 is made of silicon oxide, in one embodiment, the forming process of the second oxide layer 102 is a furnace growth process, and in other embodiments, the second oxide layer may also be formed by chemical deposition.
A second gate layer 112 is then formed, the second gate layer 112 covering the second oxide layer 102. The material of the second gate layer 112 may be polysilicon. In one embodiment, the formation process of the second gate layer 112 is a furnace growth process, and in other embodiments, the second gate layer may be formed by chemical deposition.
The second gate layer 112, the second oxide layer 102 and the first gate layer 111 provide a basis for subsequent light reflection. In this embodiment, the first gate structure 100 includes two gate layers, namely, the first gate layer 111 and the second gate layer 112, which can improve the light reflection effect and is further beneficial to improving the light transmission effect.
Of course, in other embodiments, the first gate structure 100 may also be a gate layer including only one layer or more layers.
Further, as shown in fig. 2, after forming a second gate layer 112, patterning the second gate layer 112, the second oxide layer 102 and the first gate layer 111 to form an opening 113, wherein the opening 113 exposes the first oxide layer 101;
finally, as shown in fig. 3, a third oxide layer 103 is formed, and the third oxide layer 103 fills the opening 113 and covers the second gate layer 112. In this embodiment, the third oxide layer 103 may be formed by a chemical vapor deposition process. The material of the third oxide layer 103 may be silicon dioxide. In other embodiments, the third oxide layer 103 may also be other insulating materials.
It can be seen that the first gate structure 100 on the front surface of the wafer can be obtained through the above steps, and the first gate structure 100 meeting the performance requirements can be conveniently and simply obtained through the above steps.
Of course, in other embodiments, the first gate structure 100 may be obtained in other manners.
With reference to fig. 1 and fig. 2, in an embodiment, to obtain the second gate structure 200, the following steps may be performed, specifically including:
firstly, forming a fourth oxide layer 204, wherein the fourth oxide layer 204 covers the back surface of the wafer 300;
the material of the fourth oxide layer 204 is silicon oxide. In one embodiment, the forming process of the fourth oxide layer may be a furnace growth process, and in other embodiments, the fourth oxide layer may also be formed by chemical deposition.
Then, a third gate layer 213 is formed, and the third gate layer 213 covers the fourth oxide layer 204;
the third gate layer 213 is made of polysilicon, in one embodiment, the formation process of the third gate layer 213 is a furnace growth process, and in other embodiments, the third gate layer may also be formed by chemical deposition.
Forming a fifth oxide layer 205, wherein the fifth oxide layer 205 covers the third gate layer 213;
the fifth oxide layer 205 is made of silicon oxide, in one embodiment, the forming process of the fifth oxide layer is a furnace growth process, and in other embodiments, the fifth oxide layer may also be formed by chemical deposition.
Forming a fourth gate layer 214, wherein the fourth gate layer 214 covers the fifth oxide layer 205;
the material of the fourth gate layer 214 may be polysilicon. In one embodiment, the forming process of the fourth gate layer 214 is a furnace growth process, and in other embodiments, the fourth gate layer may be formed by chemical deposition.
Removing the fourth gate layer 214; in this embodiment, a wet etching process may be used to remove the fourth gate layer 214.
The fifth oxide layer 205 is planarized.
Thus, the second gate structure 200 on the back of the wafer can be obtained, and the wet etching process is utilized, so that the etching selection ratio is high, and the process operation is convenient.
In this embodiment, the first oxide layer 101 and the fourth oxide layer 204 may be formed simultaneously, that is, the first oxide layer 101 and the fourth oxide layer 204 are simultaneously grown on two sides (front and back sides) of the wafer 300 by using a furnace growth process; meanwhile, the first gate layer 111 and the third gate layer 213 may also be formed simultaneously by using a furnace growth process, and respectively cover the first oxide layer 101 and the fourth oxide layer 204; the second oxide layer 102 and the fifth oxide layer 205 are also formed simultaneously by using a furnace growth process, and respectively cover the first gate layer 111 and the third gate layer 213 for growth; the second gate layer 112 and the fourth gate layer 214 are also formed simultaneously by using a furnace growth process, and are grown to cover the first gate layer 111 and the third gate layer 213, respectively. Since the furnace growth process is to perform film growth on the front and back surfaces of the wafer 300 at the same time, it can be ensured that the compressive stress on the front surface of the wafer 300 is balanced with the tensile stress on the back surface, and thus the flatness of the wafer 300 can be ensured.
Of course, in other embodiments, the above-mentioned layer structures may be formed by independently performing film deposition on the front surface and the back surface of the wafer 300.
In this embodiment, the material of the first oxide layer 101 or the second oxide layer 102 is silicon dioxide. In other embodiments, the first oxide layer 101 or the second oxide layer 102 may also be other insulating materials.
Referring to fig. 4, after the wafer substrate 10 is obtained, a light transmission layer 400 is formed, wherein the light transmission layer 400 covers the front surface of the wafer substrate 10. In this embodiment, a chemical deposition method is used to form the light transmission layer.
The optical transmission layer 400 is used for optical signal transmission. The optical transmission layer 400 includes an optical path transmission region and a non-optical path transmission region, and an optical signal is transmitted in the optical path transmission region of the optical transmission layer 400.
In this embodiment, the material of the light transmission layer 400 is silicon nitride.
Referring to fig. 5, the non-optical path transmission region of the light transmission layer 400 is etched to form a first groove 401, and the depth of the first groove 401 is at least equal to the thickness of the light transmission layer 400.
The depth of the first groove 401 is at least equal to the thickness of the light transmission layer 400, so as to ensure that the first groove 401 can penetrate through the light transmission layer 400 along the thickness direction of the light transmission layer 400, so as to achieve the effect of releasing stress, and the non-light path transmission region of the light transmission layer 400 is etched, so that the formation of the first groove 401 does not affect the light transmission, and the release of stress is realized at the same time.
In order to ensure that the first groove 401 can completely penetrate the light transmission layer 400 in the thickness direction of the light transmission layer 400 during the semiconductor structure processing, in one embodiment, the depth of the first groove 401 may exceed the thickness of the light transmission layer 400, considering that a specific value less than the thickness of the light transmission layer 400 is exceeded
Figure BDA0002480446840000061
The first groove is not well controlled, and thus, in one embodiment, the specific excess thickness range may be greater than or equal to
Figure BDA0002480446840000062
Therefore, the processing precision of the first groove 401 is reduced on the basis that the first groove 401 completely penetrates through the light transmission layer. As shown in fig. 5, i.e., the size of H is equal to or greater than
Figure BDA0002480446840000063
Specifically, the shape of the first groove 401 is not limited, in one embodiment, the cross-sectional shape of the first groove 401 perpendicular to the depth direction may be an inverted trapezoid, and the side wall of the first groove 401 forms an acute angle with the vertical plane, in other embodiments, the first groove 401 may also be another shape such as a rectangle or a V shape, as long as the first groove 401 is ensured to completely penetrate through the light transmission layer 400 in the thickness direction of the light transmission layer 400.
In order to further play a role in releasing stress, the first groove 401 may extend from the first end of the light transmission layer 400 to the other end opposite to the first end, so that the first groove 401 divides the light transmission layer 400 into a plurality of pieces, thereby reducing the area of the light transmission layer connected into one piece, further releasing the stress of the light transmission layer, and further reducing the curvature of the semiconductor structure caused by the stress.
Specifically, referring to fig. 6, fig. 6 is a top view of fig. 5. It can be seen that the first groove 401 extends through the first end and the opposite end of the first end in the direction of extension. First groove 401 may be a straight extension as shown in fig. 6, and in other embodiments, first groove 401 may also be a curved extension as long as it is ensured that first groove 401 is through a first end and the other end opposite to the first end in the extending direction.
In one embodiment, in order to improve the effect of releasing the stress, the opening size of the first groove 401 is greater than or equal to 500nm, for example, the opening size may be 550nm, 600nm, or greater than or equal to 650nm, and as the opening size increases, the effect of releasing the stress of the light transmission layer is more obvious, so that the flatness of the wafer can be improved more. W of fig. 6 indicates the opening size.
It should be noted that the first grooves 401 may be opened in any region of the non-optical path transmission region of the light transmission layer 400, and therefore, the number of the first grooves 401 may be at least 2, for example, 3, 4, or 5. When the plurality of first grooves 401 are formed, the stress of the light transmission layer 400 can be further released, and the curvature of the semiconductor structure can be reduced.
Referring next to fig. 7, after forming the first recess 401, in order to ensure subsequent processing of the semiconductor structure, the method further includes:
an insulating layer 500 is formed on the light transmission layer 400, and the insulating layer 500 fills the first groove 401 and covers the light transmission layer 400.
The insulating layer 500 may insulation-protect the light transmission layer 400. According to the process requirement, the thickness of the insulating layer 500 is relatively thick, and if the first groove 401 is not formed in the light transmission layer 400, after the insulating layer 500 is deposited on the light transmission layer 400, the compressive stress is further increased, so that the curvature of the wafer 300 is too large.
In this embodiment, since the first groove 401 is formed in the light transmission layer 400, after the insulating layer 500 is deposited, the material of the insulating layer 500 is silicon dioxide, the material of the light transmission layer 400 is silicon nitride, and the stress of the silicon nitride is greater than the stress of the silicon oxide, so that the stress of the light transmission layer 400 is greater than the stress of the insulating layer 500, and the stress of the wafer 300 can be further reduced by filling the insulating layer 500 in the first groove 401.
In order to further reduce the stress of the semiconductor structure, referring to fig. 8, in another embodiment, the method for forming a semiconductor structure provided by the embodiment of the present invention may further include:
and forming a stress layer 600, wherein the stress layer 600 covers the back surface of the wafer substrate 10.
The stress layer 600 covers the back surface of the wafer substrate 10, for the wafer 300, the stress of the stress layer 600 is tensile stress, and by forming the stress layer 600 on the back surface of the wafer substrate 10, a part of compressive stress on the front surface of the wafer 300 can be offset, so that the bending degree of the wafer 300 is further reduced.
In this embodiment, the stress layer is made of silicon nitride. The silicon nitride has higher stress, not only can play a role in reducing the stress of the wafer, but also can ensure that the height of the whole semiconductor structure is not too high, thereby reducing the size of the semiconductor structure. In one embodiment, the stress value of the stress layer is less than-1500 Mpa, and the thickness of the stress layer can be reduced by selecting high-stress silicon nitride as the stress layer, so that the overall height of the semiconductor structure is further reduced.
Of course, in other embodiments, the material of the stress layer may also be silicon oxynitride or silicon dioxide.
The order of formation of the stress layer and the insulating layer is not limited. The stress layer may be formed first, and the insulating layer may be formed, or the stress layer may be formed after the insulating layer is deposited.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
As shown in fig. 9, the semiconductor structure provided by the embodiment of the invention includes:
a wafer substrate (not shown by reference numerals);
a light transmission layer 40, wherein the light transmission layer 40 covers the front surface of the wafer substrate;
the non-optical path transmission region of the optical transmission layer 40 is provided with a first groove 41, and the depth of the first groove 41 is at least equal to the thickness of the optical transmission layer 40.
In the semiconductor structure provided by the embodiment of the invention, the arrangement of the first groove in the optical transmission layer is equivalent to the division of the optical transmission layer, so that the area of the optical transmission layer connected into a piece is reduced, the stress of the optical transmission layer can be released, the curvature of the semiconductor structure caused by the stress action is further reduced, the flatness of the semiconductor structure is improved, and the requirement of vacuum degree in the processing process of the semiconductor structure is ensured.
The depth of the first groove 41 is at least equal to the thickness of the light transmission layer 40, so as to ensure that the first groove 41 can penetrate through the light transmission layer 40 along the thickness direction of the light transmission layer 40, thereby achieving the effect of releasing stress. By disposing the first groove 41 in the non-optical path transmission region of the light transmission layer 40, the formation of the first groove 41 does not affect the light transmission, and the stress is released.
In a specific embodiment, the depth of the first groove 41 exceeds the thickness of the light transmission layer 40 by at least
Figure BDA0002480446840000081
So as to reduce the processing precision of the first groove 41 on the basis of ensuring that the first groove 41 can completely penetrate through the light transmission layer 40 in the thickness direction of the light transmission layer 40.
The shape of the first groove 41 is not limited, in one embodiment, the cross-sectional shape of the first groove 41 perpendicular to the depth direction may be an inverted trapezoid, and the side wall of the first groove 41 forms an acute angle with the vertical plane, in other embodiments, the first groove 41 may also be another shape such as a rectangle or a V shape, as long as the first groove 41 can completely penetrate through the light transmission layer 40 along the thickness direction of the light transmission layer 40.
To further function as a stress relief, the first groove 41 extends from a first end of the light transmission layer 40 to another end opposite to the first end. In this way, the first groove 41 divides the light transmission layer 40 into a plurality of pieces, so that the area of the light transmission layer connected into one piece can be reduced, the stress of the light transmission layer is further released, and the bending degree of the semiconductor structure caused by the stress action is further reduced.
The first groove 41 may be a straight extension or may be a curved extension as long as the first groove 41 is ensured to penetrate the first end and the other end opposite to the first end in the extending direction.
In an embodiment, in order to improve the effect of releasing the stress, the size of the opening of the first groove 41 is greater than or equal to 500nm, for example, the size of the opening may be 550nm, 600nm, or greater than or equal to 650nm, and as the size of the opening increases, the effect of releasing the stress of the light transmission layer is more obvious, so that the flatness of the wafer can be improved more.
It should be noted that the first groove 41 may be opened in any region of the non-optical path transmission region of the light transmission layer 40, and therefore, the number of the first grooves 41 may be at least 2, for example, 3, 4 or 5. When the plurality of first grooves 41 are formed, the stress of the light transmission layer 400 can be further released, and the curvature of the semiconductor structure can be reduced.
The wafer substrate 10 includes a wafer 300, a first gate structure 100 and a second gate structure 200, wherein the first gate structure 100 covers a front surface of the wafer 300, and the second gate structure 200 covers a back surface of the wafer 300. In this embodiment, the wafer 300 is a silicon substrate. In other embodiments, the wafer 300 may also be a substrate made of other materials, such as a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate.
The first gate structure 70 includes:
a first oxide layer 701, wherein the first oxide layer 701 covers the front surface of the wafer 30;
a first gate layer 711, wherein the first gate layer 711 covers a portion of the first oxide layer 701;
a second oxide layer 702, the second oxide layer 702 covering the first gate layer 711 and the first oxide layer 701;
a second gate layer 712, the second gate layer 712 covering a portion of the second oxide layer 702;
a third oxide layer 703, wherein the third oxide layer 703 covers the second gate layer 712 and the second oxide layer 702.
The first gate structure 70 provides a basis for the subsequent growth of the light transport layer. The second gate layer 712, the second oxide layer 702 and the first gate layer 711 provide a basis for subsequent light reflection. In this embodiment, the first gate structure 70 includes two gate layers, namely, the first gate layer 711 and the ground-second gate layer, which can improve the light reflection effect and is further beneficial to improving the light transmission effect. Of course, in other embodiments, the first gate structure 70 may also be a gate layer including only one layer or more layers.
In this embodiment, the first oxide layer 701, the second oxide layer 702, or the third oxide layer 703 is made of silicon dioxide. In other embodiments, the first oxide layer 701, the second oxide layer 702, or the third oxide layer 703 may also be other insulating materials. The material of the first gate layer and the second gate layer is polysilicon.
The wafer substrate further comprises:
and the second gate structure 80, wherein the second gate structure 80 covers the backside of the wafer 30, and the stress layer 60 covers the second gate structure 80.
The second gate structure 80 includes:
a fourth oxide layer 804, wherein the fourth oxide layer 804 covers the back surface of the wafer 30;
a third gate layer 813, the third gate layer 813 covering the fourth oxide layer 804;
a fifth oxide layer 805, wherein the fifth oxide layer 805 covers the third gate layer 813.
In this embodiment, the material of the fourth oxide layer 804 or the fifth oxide layer 805 is silicon dioxide. In other embodiments, the material of the fourth oxide layer 804 or the fifth oxide layer 805 may also be other insulating materials. The material of the third gate layer 813 is polysilicon.
In this embodiment, the first gate structure 70 is located on the front surface of the wafer 300, the second gate structure 80 is located on the back surface of the wafer, the thicknesses and materials of the first oxide layer 701 and the fourth oxide layer 804 are the same, and the thicknesses and materials of the first gate layer 711 and the third gate layer 813 are the same, so that the compressive stress on the front surface of the wafer 300 and the tensile stress on the back surface are partially offset, and the flatness of the wafer 300 can be ensured.
As shown in fig. 9, the semiconductor structure provided in the embodiment of the present invention further includes an insulating layer 50, wherein the insulating layer 50 fills the first groove 41 and covers the light transmission layer 40.
The insulating layer 50 serves to insulation-protect the light transmission layer 40. According to the process requirement, the thickness of the insulating layer 50 is relatively thick, and if the first groove 41 is not formed in the light transmission layer 40, after the insulating layer 50 is deposited on the light transmission layer 40, the compressive stress is further increased, so that the curvature of the wafer 30 is too large. In this embodiment, since the first groove 41 is formed in the light transmission layer 40, after the insulating layer 50 is deposited, the material of the insulating layer 50 is silicon dioxide, the material of the light transmission layer 40 is silicon nitride, and the stress of the silicon nitride is greater than the stress of the silicon oxide, so that the stress of the light transmission layer 40 is greater than the stress of the insulating layer 50, and the stress of the wafer 30 can be further reduced by filling the insulating layer 50 in the first groove 41.
With continued reference to fig. 9, the semiconductor structure further includes:
and the stress layer 60 covers the back surface of the wafer substrate, wherein the stress layer 60 covers the back surface of the wafer substrate.
The stress layer 60 covers the back surface of the wafer substrate, for the wafer 30, the stress of the stress layer 60 is tensile stress, and by forming the stress layer 60 on the back surface of the wafer substrate, a part of the compressive stress on the front surface of the wafer 30 can be offset, so that the bending degree of the wafer 30 is further reduced.
In this embodiment, the stress layer 60 is made of silicon nitride. The silicon nitride has higher stress, which not only can reduce the stress of the wafer 30, but also can ensure that the height of the whole semiconductor structure is not too high, thereby reducing the size of the semiconductor structure. In one embodiment, the stress value of the stress layer 60 is less than-1500 Mpa, and the thickness of the stress layer can be reduced by selecting high-stress silicon nitride as the stress layer, so that the overall height of the semiconductor structure can be further reduced.
Of course, in other embodiments, the material of the stress layer may also be silicon oxynitride or silicon dioxide.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a wafer substrate;
forming a light transmission layer, wherein the light transmission layer covers the front surface of the wafer substrate;
and etching the non-optical path transmission region of the optical transmission layer to form a first groove, wherein the depth of the first groove is at least equal to the thickness of the optical transmission layer.
2. The method of forming a semiconductor structure of claim 1, wherein the first recess extends from a first end of the light transmission layer to another end opposite the first end.
3. The method for forming a semiconductor structure according to claim 1, wherein an opening size of the first recess is 500nm or more.
4. The method of forming a semiconductor structure of claim 1, wherein the first recess is formedA depth exceeding the thickness of the light transmission layer by at least
Figure FDA0002480446830000011
5. The method of forming a semiconductor structure of claim 1, wherein the number of first recesses is at least 2.
6. The method of forming a semiconductor structure of any of claims 1-5, further comprising:
and forming a stress layer, wherein the stress layer covers the back surface of the wafer substrate.
7. The method of forming a semiconductor structure of any of claims 1-5, further comprising, after forming the first recess:
and forming an insulating layer on the light transmission layer, wherein the insulating layer fills the first groove and covers the light transmission layer.
8. The method of forming a semiconductor structure of any of claims 1-5, wherein the wafer substrate comprises a wafer and a first gate structure, the first gate structure overlying a front side of the wafer.
9. The method of forming a semiconductor structure of claim 8, wherein forming the first gate structure comprises:
forming a first oxidation layer, wherein the first oxidation layer covers the front side of the wafer;
forming a first gate layer overlying the first oxide layer;
forming a second oxide layer covering the first gate layer;
forming a second gate layer overlying the second oxide layer;
patterning the second gate layer, the second oxide layer and the first gate layer to form an opening, wherein the opening exposes the first oxide layer;
and forming a third oxide layer which fills the opening and covers the second grid layer.
10. The method of forming a semiconductor structure of claim 8, wherein the wafer substrate further comprises a second gate structure, the second gate structure overlying the back side of the wafer.
11. The method of forming a semiconductor structure of claim 10, wherein forming the second gate structure comprises:
forming a fourth oxide layer, wherein the fourth oxide layer covers the back of the wafer;
forming a third gate layer overlying the fourth oxide layer;
forming a fifth oxide layer covering the third gate layer;
forming a fourth gate layer overlying the fifth oxide layer;
removing the fourth gate layer;
and flattening the fifth oxide layer.
12. The method for forming the semiconductor structure according to claim 11, wherein the process for removing the fourth gate layer is a wet etching process.
13. The method of claim 11, wherein the forming the first gate layer and the forming the third gate layer are furnace growth processes.
14. A semiconductor structure, comprising:
a wafer substrate;
the light transmission layer covers the front surface of the wafer substrate;
the non-optical path transmission area of the optical transmission layer is provided with a first groove, and the depth of the first groove is at least equal to the thickness of the optical transmission layer.
15. The semiconductor structure of claim 14, further comprising:
and the stress layer covers the back surface of the wafer substrate.
16. The semiconductor structure of claim 15, wherein the stress layer material is silicon nitride.
17. The semiconductor structure of claim 16, wherein the stress layer has a stress value of less than-1500 Mpa.
18. The semiconductor structure of any one of claims 14-17, further comprising:
an insulating layer filling the first groove and covering the light transmission layer.
19. The semiconductor structure of any one of claims 14-17, wherein the wafer substrate comprises a wafer and a first gate structure, the first gate structure overlying a front side of the wafer, the light transmissive layer overlying the first gate structure.
20. The semiconductor structure of any one of claims 15-17, wherein the wafer substrate further comprises:
and the second gate structure covers the back surface of the wafer, and the stress layer covers the second gate structure.
CN202010376870.4A 2020-05-07 2020-05-07 Semiconductor structure and forming method thereof Pending CN113629165A (en)

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