CN113594259B - Field effect transistor, preparation method and logic gate operation implementation method - Google Patents

Field effect transistor, preparation method and logic gate operation implementation method Download PDF

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CN113594259B
CN113594259B CN202110678712.9A CN202110678712A CN113594259B CN 113594259 B CN113594259 B CN 113594259B CN 202110678712 A CN202110678712 A CN 202110678712A CN 113594259 B CN113594259 B CN 113594259B
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field effect
effect transistor
channel region
gate
alpha
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CN113594259A (en
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王振兴
王俊俊
王峰
何军
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National Center for Nanosccience and Technology China
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National Center for Nanosccience and Technology China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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Abstract

The invention provides a field effect transistor, a preparation method and a logic gate operation realization method, which are characterized In that an alpha-In 2Se3 nano sheet is used for forming a channel region, the ferroelectric polarization characteristics In and out of the plane can be changed by utilizing the voltage control of alpha-In 2Se3, the input voltage of at least one end of a grid electrode and a drain electrode can be controlled, the resistance state of the channel region can be changed to regulate the output current of a source electrode, and the logic gate operation is realized according to the output current. Therefore, the single field effect transistor provided by the invention can realize various logic gate operations, and compared with the traditional field effect transistor, the field effect transistor device provided by the invention has simple structure and smaller size.

Description

Field effect transistor, preparation method and logic gate operation implementation method
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a field effect transistor, a method for manufacturing the field effect transistor, and a method for implementing logic gate operation.
Background
The continued scaling of the size of Complementary Metal Oxide Semiconductor (CMOS) field effect Transistor FETs (FIELD EFFECT transistors) has been the cornerstone of rapid increase in microprocessor computing performance. Although new technologies like strained silicon gates, high-k dielectrics, fin-FETs (Fin Field-Effect Transistor), fully-surrounding gate structures, etc. have driven a continual reduction in device size, conventional CMOS will always inevitably reach the scaling limit.
In order to allow for continued improvement of device performance, some readily realizable solutions have been proposed. For example, a reconfigurable field effect transistor with programmable conduction polarity on a single device can increase the functionality of the device, thereby increasing material area utilization without disrupting recognized designs and building modern electronic circuitry. However, the above solution has a serious disadvantage in that it requires the addition of an additional electrode tip, which in turn greatly increases the complexity of the system. Therefore, a device design having a simpler structure while enabling a multi-function logic operation is highly desired.
Disclosure of Invention
The invention provides a field effect transistor, a preparation method and a logic gate operation realization method, which are used for solving the problem that a semiconductor device for realizing logic gate operation in the prior art is complex in structure.
The present invention provides a field effect transistor comprising:
A gate;
A dielectric layer covering the gate;
A channel region formed with alpha-In 2Se3 nanoplatelets on the dielectric layer;
source and drain electrodes distributed at both ends with respect to the channel region.
According to the field effect transistor provided by the invention, the grid electrode is formed by the substrate.
The field effect transistor provided by the invention further comprises:
And the passivation layer covers the channel region, the source electrode and the drain electrode.
According to the field effect transistor provided by the invention, the passivation layer is made of a light-transmitting material.
The invention also provides a preparation method of the field effect transistor, which comprises the following steps:
Forming a gate and a dielectric layer covering the gate;
transferring the alpha-In 2Se3 nano-sheet obtained by micro-mechanical stripping onto the dielectric layer to form a channel region;
source and drain electrodes are formed distributed at both ends with respect to the channel region.
According to the preparation method of the field effect transistor provided by the invention, the alpha-In 2Se3 nano sheet obtained by micro mechanical stripping is transferred onto the dielectric layer to form a channel region, and the preparation method comprises the following steps:
Spin-coating PPC solution on the alpha-In 2Se3 nano-sheet obtained by micro-mechanical stripping;
baking the PPC solution to form a PPC film;
stripping the PPC film adhered with the alpha-In 2Se3 nano sheet by using deionized water;
Transferring the PPC film onto the dielectric layer such that the PPC film covers the dielectric layer to support the alpha-In 2Se3 nanoplatelets;
transferring the PPC film with the alpha-In 2Se3 nanoplatelets adhered thereto onto the dielectric layer such that the alpha-In 2Se3 nanoplatelets cover the dielectric layer;
Dissolving the PPC film, leaving the alpha-In 2Se3 nanoplatelets to form the channel region.
According to the preparation method of the field effect transistor provided by the invention, a source electrode and a drain electrode which are distributed at two ends relative to the channel region are formed, and the preparation method comprises the following steps:
forming a metal material layer on the channel region using a metal deposition process;
And carrying out patterning treatment on the metal material layer to obtain the source electrode and the drain electrode.
The preparation method of the field effect transistor provided by the invention further comprises the following steps:
A passivation layer is formed on the channel region, the source electrode, and the drain electrode using an atomic layer deposition method.
The invention also provides a logic gate operation realization method, which comprises the following steps:
providing a field effect transistor as described in any one of the above;
and controlling the input voltage of at least one end of the grid electrode and the drain electrode to regulate the output current of the source electrode so as to realize logic gate operation according to the output current.
The logic gate operation implementation method provided by the embodiment of the invention further comprises the following steps:
An alpha-In 2Se3 nano-sheet In the channel region is irradiated with a light signal to adjust the ferroelectric polarization state of the alpha-In 2Se3 nano-sheet, thereby adjusting the resistance state thereof.
According to the field effect transistor, the preparation method and the logic gate operation implementation method, the alpha-In 2Se3 nano-sheet is used for forming the channel region, the alpha-In 2Se3 is utilized to be controlled by voltage so as to change ferroelectric polarization characteristics In and out of the plane, the input voltage of at least one end of the grid electrode and the drain electrode is controlled, the resistance state of the channel region can be changed to adjust the output current of the source electrode, and the logic gate operation is realized according to the output current. Therefore, by using the single field effect transistor provided by the embodiment of the invention, various logic gate operations can be realized, and compared with the conventional field effect transistor for realizing the logic gate operations, the field effect transistor device provided by the invention has the advantages of simple structure and smaller size.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic perspective view of a field effect transistor according to an embodiment of the present invention;
FIGS. 2-14 are schematic diagrams illustrating a test procedure for implementing logic gate operation using the FET of FIG. 1 according to an embodiment of the present invention;
fig. 15 is a schematic flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present invention;
Fig. 16 to fig. 20 are schematic cross-sectional structures of various stages of a method for manufacturing a field effect transistor according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Currently, the performance of modern CMOS systems has entered a plateau for many years. The main reason for this is that the physical separation between the processing units and the memory units of the von neumann architecture results in energy and time consumption when data is shuttled between the two. However, as society enters a big data age, many scenes such as internet of things, machine learning, artificial neural network, bionic intelligence and the like need to be applied to a large amount of data, so that huge energy consumption and a large amount of time are wasted, and therefore, breaking of von neumann architecture is imperative.
In order to construct an efficient and high-speed data-centric electronic circuit, a solution with a very promising application prospect, namely a memory algorithm, is proposed. Up to now, schemes based on nonvolatile memory including resistance change memory, phase change memory, and floating gate memory have been reported to confirm that a memory integrated function can be achieved. However, there are still many obstacles to the practical production and life of these schemes, such as switching electrode variability, high operating voltages, complex processes (extra gates or logic inputs), etc.
It has been found that ferroelectric materials having the property that the ferroelectric polarization state can be reversed by an external electric field have been demonstrated to have the ability to build functional devices such as ferroelectric random access memory RAM (Random Access Memory) for non-volatile storage, negative capacitance field effect transistors for high efficiency switches, etc., particularly for memory integrated ferroelectric field effect transistor devices. Scaling of devices with good endurance/reliability, large memory window, and fast write/erase speeds has been a big challenge. Moreover, conventional ferroelectric materials are either insulators or wide bandgap semiconductors, which severely limit the functionality of ferroelectric-based devices.
The present invention turns to another van der waals ferroelectric semiconductor material α -In 2Se3. On the one hand, the layered structure of α -In 2Se3 is inherently immune to the problems caused by scaling of the device described above. The above advantages have therefore made α -In 2Se3 a promising candidate for constructing unexplored functional devices, wherein the concept of integrating logic and memory functions into one simple structure device has not been proposed and implemented.
The field effect transistor provided in the embodiment of the present invention is described below with reference to fig. 1.
Referring to fig. 1, a field effect transistor provided in an embodiment of the present invention includes:
A gate electrode 11;
A dielectric layer 12 covering the gate electrode 11;
A channel region 13 formed using alpha-In 2Se3 nano-sheets on the dielectric layer 12;
a source 14 and a drain 25 are distributed at both ends with respect to the channel 13 region.
The material adopted for the channel region 13 In the embodiment of the present invention is α -In 2Se3, and the field effect transistor In the embodiment of the present invention can be used to implement logic gate operation. Specifically, the input voltages to at least one of the gate 11 and the drain 15 may change the resistance state of the channel region 13 to adjust the output current of the source 14 to achieve a logic gate operation according to the output current.
Therefore, by using the single field effect transistor provided by the embodiment of the invention, various logic gate operations can be realized, and compared with the conventional field effect transistor for realizing the logic gate operations, the field effect transistor device provided by the invention has the advantages of simple structure and smaller size.
The scheme of implementing logic gates by field effect transistors according to the embodiments of the present invention is described in detail below with reference to specific test data.
The field effect transistor is first set to an initial ferroelectric polarization state (high-resistance state or low-resistance state) using a pulse programming signal with a larger amplitude, and then logic calculation is performed by inputting a gate voltage at the gate 11 and/or inputting an input voltage pulse signal such as a bias signal at the drain 15. After the input voltage is finished, a nonvolatile memory integrated function can be realized.
Referring to fig. 2, if the field effect transistor is set to a High Resistance State (HRS), during a voltage input, an output current of the field effect transistor implements and gate logic operation. Wherein 0 denotes an input low level pulse signal, 1 denotes an input high level pulse signal, so that the gate voltage-bias voltage= '11' denotes that the input voltage includes both the gate voltage and the bias voltage are high level pulse signals, the gate voltage-bias voltage= '00' denotes that the input voltage includes both the gate voltage and the bias voltage are low level pulse signals, the gate voltage-bias voltage= '01' denotes that the gate voltage in the input voltage is a low level pulse signal, the bias voltage is a high level pulse signal, and the gate voltage-bias voltage= '10' denotes that the gate voltage in the input voltage is a high level pulse signal, and the bias voltage is a low level pulse signal.
Specifically, only when the gate voltage and the bias voltage simultaneously input a high-level pulse signal, the output current is a high current. When one of the input gate voltage or the bias voltage is a low-level pulse signal, the output current is low. In this way, and gate logic can be implemented based on the output current.
With reference to fig. 3, the field effect transistor is very robust in implementing and gate logic operations over multiple cycles.
Referring to fig. 4, if the field effect transistor is set to a High Resistance State (HRS) after the end of the voltage pulse signal input, the storage current of the field effect transistor implements a non-volatile nor gate logic operation, and the storage current is the output current of the field effect transistor after the end of the voltage pulse signal input.
Specifically, when the low level pulse signal is simultaneously input to the input gate voltage and the bias voltage, the storage current maintains a high current, and when only one voltage signal input is the high level pulse signal in the input gate voltage and the bias voltage, the storage current is low after the input voltage is ended. Thus, non-volatile nor gate logic operations may be implemented in accordance with the memory current.
Referring to fig. 5, the field effect transistor is very robust in implementing non-volatile nor gate logic operation after being set to a High Resistance State (HRS).
Referring to fig. 6, after the field effect transistor is set to a High Resistance State (HRS), implementing non-volatile nor gate logic operation has an ultra-fast operating speed, which may be approximately 10 μs.
Referring to fig. 7, after the field effect transistor is set to a Low Resistance State (LRS), an output current of the field effect transistor implements an or gate logic operation during a voltage input.
Specifically, the output current is low only when the gate voltage and the bias voltage are simultaneously inputted with a low level pulse signal, and is high when one of the gate voltage and the bias voltage is inputted with a high level pulse signal. Thus, an or gate logic operation can be realized according to the output current.
Referring to fig. 8, after the field effect transistor is set to a Low Resistance State (LRS), the implemented or gate logic operation is very robust.
Referring to fig. 9, after the field effect transistor is set to a Low Resistance State (LRS), the memory current of the device implements a non-volatile nand gate logic operation after the voltage input is completed.
Specifically, the storage current maintains a low current after the gate voltage and the bias voltage are simultaneously inputted with the high level pulse signal, and maintains a high current after the input signal is ended as long as one of the input gate voltage and the bias voltage is inputted with the low level pulse signal. Thus, a nonvolatile NAND gate logic operation can be implemented according to the memory current.
Referring to fig. 10, after the field effect transistor is set to a Low Resistance State (LRS), the implemented non-volatile nand gate logic operation is very robust.
Referring to fig. 11, after the field effect transistor is set to a high resistance state (LRS), the nand gate logic operation is implemented with an ultra-fast operation speed, which may be approximately 10 μs.
In alternative embodiments of the present invention, the strong photoresponsive properties of alpha-In 2Se3 may also be used to change the resistance state of the channel region. Specifically, an α -In 2Se3 nano-sheet In the channel region is irradiated with an optical signal to adjust the ferroelectric polarization state of the α -In 2Se3 nano-sheet, thereby adjusting the resistance state thereof.
Referring to fig. 12, a laser signal in a visible light band is taken as another input terminal, and a logic operation and a nonvolatile memory integrated function of photoelectric synergy are realized by combining the drain bias signal, wherein ON indicates that there is an optical signal input, OFF indicates that there is no optical signal input, and the visible light band includes 473 nm, 532 nm and 639 nm.
When the bias signal is input alone, the output current reaches a high current. When the bias signal ends, the memory current becomes low, so that the nonvolatile NOT logic can be implemented. When the bias signal and the laser signal are used as two input signals, the output current is kept to be low current only when the two input signals are low-level pulse signals; when the bias voltage and the laser signal are finished, the storage current is kept in a low current state only when the bias voltage signal is a high-level pulse signal and the laser signal is in an off state, so that the field effect transistor realizes the OR gate logic and the nonvolatile inclusion logic of photoelectric synergy.
Referring to fig. 13, a laser signal in a visible light band is used as another input terminal, and a logic operation and a nonvolatile memory integrated function of photoelectric synergy are realized by combining the grid voltage signal.
When the gate voltage signal is input alone, the output current reaches a high current. When the gate voltage signal ends, the memory current becomes low, so that non-volatile NOT logic can be implemented. When the grid voltage signal and the laser signal are used as two input signals, the output current is kept to be low current only when the grid voltage signal is a low-level pulse signal and the laser signal is in a closed state; when the grid voltage and the laser signal are finished, the storage current is kept in a low current state only when the grid voltage signal is a high-level pulse signal and the laser signal is in an off state, so that the field effect transistor realizes the OR gate logic and the nonvolatile inclusion logic of photoelectric synergy.
Referring to fig. 14, three ends of a laser signal, a gate voltage signal, and a bias voltage signal are taken as input ends. The light bar is used for representing the height of the output current, the darker the color is, the higher the output current is, and the lighter the color is, the lower the output current is.
When the input is photo-gate voltage-bias voltage= '000', the output current is low, and in other states, such as photo-gate voltage-bias voltage= '001', photo-gate voltage-bias voltage= '010', photo-gate voltage-bias voltage= '011', photo-gate voltage-bias voltage= '100', photo-gate voltage-bias voltage= '101', photo-gate voltage-bias voltage= '110', photo-gate voltage-bias voltage= '111', the output current is high, so that three-input or gate logic operation can be realized.
When the photo-gate voltage-bias voltage= '000' and the photo-gate voltage-bias voltage= '100', that is, no matter whether the laser signal is input or not, the memory current of the field effect transistor maintains high current when the input gate voltage and the bias voltage are both low level pulse signals, and the memory current maintains low current under other conditions, so as to realize the nonvolatile NOR gate logic operation.
From the above, the field effect transistor according to the embodiment of the invention can realize the following functions:
S1, when only one grid voltage or bias voltage signal is used as an input signal, non-volatile NOT gate logic operation can be realized;
S2, when the grid voltage and the bias voltage pulse are used as input signals at the same time, two-input AND gate and OR gate logic operation and nonvolatile NAND gate and NOR gate logic operation can be realized;
S3, when only one voltage signal (gate voltage or bias voltage) and the laser signal are used as input signals, two-input OR gate logic operation and nonvolatile implication logic operation can be realized;
S4, when two voltage (grid voltage and bias voltage) pulses and a laser signal are used as input signals, three-input OR gate and NOR gate logic operation can be realized.
As can be seen from the above test results, the field effect transistor device provided by the embodiment of the invention has a simple three-terminal structure, can realize various logic operations including OR gate, AND gate logic operation, nonvolatile NOT gate, NAND gate, NOR gate, implication and other logic operations only by setting different initial states and different input conditions, and has excellent robustness and ultra-fast operation speed.
The structure of the field effect transistor according to the embodiment of the present invention is specifically described below with reference to fig. 1.
In the embodiment of the present invention, the gate electrode 11 is formed of a substrate. Specifically, a silicon wafer substrate is heavily doped, and the substrate directly serves as the gate electrode 11.
In an alternative embodiment of the present invention, the protruding gate may be formed on the substrate or the substrate may be patterned to form the protruding gate, which is not limited herein.
In embodiments of the present invention, the dielectric layer 12 may be selected from aluminum oxide or other dielectric materials for insulating isolation.
In an embodiment of the present invention, the field effect transistor may further include a passivation layer 16, and the passivation layer 16 covers the channel region 13, the source electrode 14, and the drain electrode 15. The passivation layer 16 serves to protect the channel region 13, the source electrode 14, and the drain electrode 15.
Wherein the passivation layer 16 covers the sidewalls of the source electrode 14 and the drain electrode 15, i.e., partially and incompletely covers the source electrode 14 and the drain electrode 15. In alternative embodiments, the passivation layer may also completely cover the source and drain electrodes.
The passivation layer 16 may be made of a light transmissive material such as aluminum oxide or hafnium oxide, which may be transmissive using laser signals to achieve logic gate operation, and is not particularly limited herein.
The source electrode 14 and the drain electrode 15 may be metal electrodes, or graphene electrodes.
The following describes a method for manufacturing a field effect transistor according to an embodiment of the present invention with reference to fig. 15 to 20.
Referring to fig. 15, the method for manufacturing a field effect transistor according to the embodiment of the present invention may include the following steps:
step 151: forming a gate and a dielectric layer covering the gate;
Step 152: transferring the two-dimensional lamellar ferroelectric semiconductor alpha-In 2Se3 nanometer sheet obtained by micro-mechanical stripping onto a dielectric layer to form a channel region;
step 153: source and drain electrodes are formed distributed at both ends with respect to the channel region.
In particular, referring to fig. 16, a substrate 160 is provided, the substrate 160 forming a gate.
The substrate 160 may be a heavily doped silicon substrate and may act directly as a gate. The type or proportion of ions doped in the substrate 160 is not particularly limited herein.
Referring to fig. 17, a dielectric layer 170 is deposited on a substrate 160 using an atomic deposition process, the dielectric layer 170 covering the substrate 160, serving as an insulating barrier to the substrate 160 and the device layers thereon.
The material of the dielectric layer 170 is aluminum oxide or silicon dioxide or other materials capable of playing an insulating role. The thickness of the aluminum oxide dielectric layer 170 is 15 to 50nm, preferably 50nm, and the thickness of other materials can be selected according to need, and is not limited herein.
Referring to fig. 18, the α -In 2Se3 material is In the form of nanoplatelets so that the exfoliated α -In 2Se3 nanoplatelets can be transferred onto the dielectric layer 170, with the α -In 2Se3 nanoplatelets over the dielectric layer 170 to form the channel region 180.
The alpha-In 2Se3 nano sheet can be prepared by mechanically stripping the corresponding bulk material by using a transparent adhesive tape, and the laminar alpha-In 2Se3 bulk material is adhered to the adhesive tape by multiple stripping to realize stripping.
In an embodiment of the present invention, the α -In 2Se3 nanoplatelets are peeled directly onto the substrate 160 with the aluminum oxide dielectric layer 170 evaporated.
In an embodiment of the present invention, the α -In 2Se3 nano-sheet obtained by the lift-off is transferred onto the dielectric layer 170 to form the channel region 180, which includes the following steps:
Spin-coating PPC solution on the alpha-In 2Se3 nano-sheet obtained by micro-mechanical stripping;
baking the PPC solution to form a PPC film;
stripping the PPC film adhered with the alpha-In 2Se3 nano sheet by using deionized water;
transferring the PPC film with the alpha-In 2Se3 nanoplatelets adhered thereto onto the dielectric layer such that the alpha-In 2Se3 nanoplatelets cover the dielectric layer;
Dissolving the PPC film, leaving the alpha-In 2Se3 nanoplatelets to form the channel region.
The English name of PPC is (poly (propylene carbonate), which refers to polypropylene carbonate) and PPC In a solution state is uniformly spin-coated on an alpha-In 2Se3 nanometer sheet, and is cured by baking, wherein the baking time is about 10-30 seconds, and the method is not particularly limited.
In an alternative embodiment of the present invention, heat may be applied to enhance adhesion between the α -In 2Se3 nanoplatelets and the dielectric layer 170 prior to dissolution of the PPC film, allowing the α -In 2Se3 nanoplatelets to bond more tightly at the interface with the dielectric layer 170;
in addition, acetone may be used to dissolve the PPC membrane.
Referring to fig. 19, a source 191 and a drain 192 are formed on the channel region 180, wherein the source 191 and the drain 192 are disposed at both ends.
In an embodiment of the present invention, both the source 191 and the drain 192 are located on the channel region 180.
In an embodiment of the present invention, forming a source and a drain distributed at both ends with respect to a channel region includes:
forming a metal material layer on the channel region using a metal deposition process;
And carrying out patterning treatment on the metal material layer to obtain the source electrode and the drain electrode.
In the embodiment of the invention, the metal deposition sequence can be titanium with the thickness of 10-30 nm and gold with the thickness of 50-60 nm; or 50-60 nm thick gold. Preferably a titanium-gold composite layer, wherein the lower layer is titanium, and the upper layer is gold; more preferably, the titanium layer of the electrode has a thickness of 15nm and the gold layer has a thickness of 60nm.
The patterning process may use a standard electron beam exposure process, and is not particularly limited herein.
In an alternative embodiment of the invention, a patterned masking layer is formed over the channel region prior to forming a layer of metal material over the channel region using a metal deposition process, the patterned masking layer defining the locations of the source and drain electrodes. Thus, a metal material layer is formed over the channel region covering the patterned mask layer and the exposed channel region portions.
Further, the metal material layer is subjected to patterning treatment to obtain the source electrode and the drain electrode, specifically, the metal material layer part and the patterned mask layer on the patterned mask layer are removed,
In alternative embodiments, graphene materials may also be used for the source and drain electrodes.
Referring to fig. 20, a passivation layer 200 is formed on the channel region 180, the source electrode 191, and the drain electrode 192 using an atomic layer deposition method. The passivation layer 200 covers the channel region 180 and also covers portions of the sidewalls of the source and drain electrodes 191 and 192.
The passivation layer 200 is made of aluminum oxide or hafnium oxide, and has a thickness of 10 to 50nm, preferably aluminum oxide as the passivation layer, and more preferably 10nm.
In alternative embodiments of the present invention, the passivation layer may completely cover the source and drain electrodes.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A field effect transistor, comprising:
A gate;
A dielectric layer covering the gate;
A channel region formed with alpha-In 2Se3 nanoplatelets on the dielectric layer;
Source and drain electrodes distributed at both ends with respect to the channel region; the ferroelectric polarization characteristics In and out of the plane are changed by utilizing the alpha-In 2Se3 under the control of voltage, the input voltage of at least one end of the grid electrode and the drain electrode is controlled, and the resistance state of the channel region is changed to adjust the output current of the source electrode so as to realize the logic gate operation according to the output current.
2. The field effect transistor of claim 1, wherein the gate is formed from a substrate.
3. The field effect transistor of claim 1, further comprising:
And the passivation layer covers the channel region, the source electrode and the drain electrode.
4. A field effect transistor according to claim 3, wherein the passivation layer is made of a light transmissive material.
5. A method of manufacturing a field effect transistor, suitable for use in a field effect transistor according to any one of claims 1 to 4, comprising:
Forming a gate and a dielectric layer covering the gate;
transferring the alpha-In 2Se3 nano-sheet obtained by micro-mechanical stripping onto the dielectric layer to form a channel region;
source and drain electrodes are formed distributed at both ends with respect to the channel region.
6. The method of manufacturing a field effect transistor according to claim 5, wherein transferring the micro-mechanically exfoliated α -In 2Se3 nano-sheet onto the dielectric layer to form a channel region comprises:
Spin-coating PPC solution on the alpha-In 2Se3 nano-sheet obtained by micro-mechanical stripping;
baking the PPC solution to form a PPC film;
stripping the PPC film adhered with the alpha-In 2Se3 nano sheet by using deionized water;
transferring the PPC film with the alpha-In 2Se3 nanoplatelets adhered thereto onto the dielectric layer such that the alpha-In 2Se3 nanoplatelets cover the dielectric layer;
Dissolving the PPC film, leaving the alpha-In 2Se3 nanoplatelets to form the channel region.
7. The method of manufacturing a field effect transistor according to claim 5, wherein forming a source and a drain distributed at both ends with respect to the channel region, comprises:
forming a metal material layer on the channel region using a metal deposition process;
And carrying out patterning treatment on the metal material layer to obtain the source electrode and the drain electrode.
8. The method of manufacturing a field effect transistor according to claim 5, further comprising:
A passivation layer is formed on the channel region, the source electrode, and the drain electrode using an atomic layer deposition method.
9. A method for implementing logic gate operations, comprising:
providing a field effect transistor as claimed in any one of claims 1 to 4;
Illuminating an alpha-In 2Se3 nano-sheet In the channel region with an optical signal to adjust the ferroelectric polarization state of the alpha-In 2Se3 nano-sheet, thereby adjusting the resistance state thereof;
and controlling the input voltage of at least one end of the grid electrode and the drain electrode to regulate the output current of the source electrode so as to realize logic gate operation according to the output current.
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Publication number Priority date Publication date Assignee Title
CN110061056A (en) * 2019-06-06 2019-07-26 湘潭大学 A kind of novel ferroelectric FET unit and its write-in and read method
CN110246891A (en) * 2019-06-28 2019-09-17 北京大学 A kind of synapse transistor, device and its manufacturing method, operation array
CN111969035A (en) * 2020-07-09 2020-11-20 山西师范大学 Transistor device and application and preparation thereof

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