KR20120068598A - Memristor apparatus using flexible substrate and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A memristor apparatus and a manufacturing method thereof using an oxide semiconductor thin film layer and an organic ferroelectric thin film layer are provided to dynamically control a device property by providing a memristor transistor with an adaptive studying function on a flexible plastic substrate. CONSTITUTION: A substrate barrier dielectric layer(102) reduces the mechanical stress of a substrate. An oxide semiconductor thin film layer is formed on the upper side of a substrate barrier insulation layer between a source electrode layer and a drain electrode layer. A protection insulation layer(108) is formed on the upper side of the oxide semiconductor thin film layer and protects an oxide semiconductor thin film layer. An organic ferroelectric thin film layer(110) is formed on the upper sides of the source electrode layer, the drain electrode layer, and the protection insulation layer and is used as a gate insulation layer. A top gate electrode layer(114) is formed on the upper side of the organic ferroelectric thin film layer in a channel region.

Description

Memristor Apparatus and Manufacturing Method Thereof {Memristor Apparatus Using Flexible Substrate and Manufacturing Method Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a memristor device using a oxide semiconductor thin film layer and an organic ferroelectric thin film layer as a channel layer and a gate insulating film layer of a thin film transistor.

The existing electronics industry has been developed through technological advances in silicon and materials and device technologies, namely silicon electronics. However, silicon electronics have the disadvantage of being hard and brittle, due to the nature of the material, and opaque in the visible range, making them unsuitable for certain applications. As a solution for overcoming the limitations of the silicon electronics, a concept of flexible electronics for manufacturing electronic devices and electronic systems on a flexible substrate has been newly proposed. In addition, modern electronic devices are classified into advanced device and component areas focusing on high performance, and next-generation parts that target low cost, light weight, and convergence functions even at the expense of performance. The technology that actively supports is the flexible electronics technology. Currently, research and development is underway to realize various applications such as sensors, displays, electronic circuits and batteries.

On the other hand, electronic circuits that make up all the electronic components currently used are represented by three types of passive components: capacitors, resistors, and inductors. These passive components are responsible for distributing or storing energy, and cannot actively generate energy. The three passive elements can also be described as a simple linear connection between two of the four fundamental variables, current, voltage, charge and magnetic flux, which describe the circuit operation. In the early 1970's, Leon Chua predicted that a fourth passive element must exist along with the three passive elements in order to construct a complete circuit. The element was named Memristor. Memristor is a passive element that connects magnetic flux and charge, and claims that four passive elements, including memristors, can complete a total of six circuit formulas. In 2008, about 40 years later, researchers at HP in the United States built a new class of electronics that embodied the predicted memristor function, and claimed that the fourth component of the circuit was finally discovered.

When voltage is applied to the memristor, the current flowing through the memristor appears in the form of a sinusoidal curve with time. From these characteristics, the memristor reversibly moves between the strong on state and the weak off state. Therefore, the memristor acts as a nonlinear resistor, and because the resistance changes nonlinearly with the time reduction of the voltage, it can act as a register for storing information. In other words, the memristor element can remember how much current has passed through the memristor. Various resistance-variable memory devices reported so far can be classified functionally as memristor devices, and in a narrow sense, memristors have functions that satisfy the relationship between magnetic flux and charge.

An example of a previously proposed memristor device is as follows.

First, a device having a two-terminal structure is formed by forming a predetermined electrode on both ends of a binary oxide represented by a metal oxide. At this time, examples of the type of binary oxide material include titanium oxide, nickel oxide, copper oxide and the like. In the device, the resistance state of both ends of the device can be changed into a high resistance state and a low resistance state by changing the polarity and magnitude of the voltage applied across the device.

Second, an active region composed of two elements, an element that is easy to diffuse and an electrolyte required for element diffusion, and a predetermined electrode are formed at both ends of the region to form an element having a two-terminal structure. In the device, by changing the polarity and magnitude of the voltage applied to both ends of the device, a low resistance state made by forming a conductive filament of a conductive diffusion species element in an electrolyte and a high resistance state made by dismantling the conductive filament can be realized.

Third, it is a device group of various structures manufactured in a form in which the resistance state of the material is greatly changed by the redox reaction of the core material constituting the device or the introduction of special gas species included in the outside air. For example, the specific organic thin film may change the resistance state greatly according to the structural change of the organic material by the redox reaction. In addition, certain oxide thin films can experience reversible changes to two materials whose conductivity varies greatly with the supply of hydrogen.

If the good performance of the memristor device having the various structures and operating principles described above is implemented, it is expected to replace the existing devices to provide improved performance or to create device applications with new functions not currently implemented. .

The first application is in the field of ultra high density nonvolatile memory devices. Currently, silicon-based flash memory occupies most of the market, but due to the physical limitations of flash memory itself, there is an urgent need for a device to replace it in the near future. Some are actively researching under the name of resistive-change random access memory (ReRAM). In the field, the purpose of the technology is to dramatically increase the level of existing nonvolatile memory technology on the extension of existing silicon electronics.

The second application field is a technical field in which non-volatile logic is provided to the logic circuit itself by integrating a device having a memory function in the existing logic circuit. Such attempts have been actively made in recent years as a way to reduce power consumption of existing silicon-based integrated circuits. By temporarily storing information of infrequently used circuit parts in a memory device and cutting off the power of the parts, Reducing power consumption in circuit systems is key to the technology. In order to use memristor devices in this field, process compatibility with existing silicon-based devices should be no problem.

The characteristics of the first and second application areas are closely related to the existing silicon-based electronic circuits and components, and the data storage provided by the memristor device is digital information. On the other hand, by utilizing the state accumulation characteristic based on the flux accumulation of the memristor, the form of data storage provided by the memristor device can be changed analogously, and various additional functions can be expected.

The third field of application is the application of electronic devices with adaptive learning. In this field, studies are being conducted to provide devices expressing predetermined characteristics through fast time learning using a simple device structure, and many research examples for implementing the above functions using silicon-based CMOS devices have been reported. It is becoming. However, in order to implement the adaptive learning function using a conventional transistor device, the number of devices is increased so that the circuit size becomes too large, and it is known that enormous learning time is required to give a learning function. It is becoming. On the other hand, by using the characteristics of the memristor, it is possible to impart various intermediate states other than the on and off states to the device in a very simple manner, and to change the characteristics of the device continuously. If such a device is implemented, it is expected to greatly contribute to the development of new device technology for user-friendly flexible electronics as well as the rapid development of existing silicon electronic computing technology.

In the fourth application field, the adaptive learning function of the memristor mentioned in the third application field is further advanced. The memristor element is used as a synapse of a neural network, and an electrical signal is applied to a neuron of blocking when a predetermined threshold is exceeded. It is a neural network application field that implements intelligent information processing function that occurs in the human brain by combining with neural network neuron circuit that delivers. In this application, the memristor element plays a role of synapse, a connection linking neurons and neurons, and through the adaptive learning function described above, synapses having different weights can be realized. This field is also a key source technology that can accelerate the development of artificial intelligence device technology for flexible electronics, as well as the rapid development of existing silicon electronics computing technology.

Until now, several device structures and operating principles have been proposed for realizing the adaptive learning function that can be implemented in memristors.However, the following problems are required to realize memristor devices with adaptive learning functions by fabricating them on a flexible substrate. Have.

First, in the case of a two-terminal memristor device using a binary oxide, the operation principle is not clear yet, and there is a problem in that the operation characteristics of the device vary irregularly depending on the production conditions of the oxide thin film layer and the type of electrode used. In addition, in the case of a memristor device using an organic thin film layer having a predetermined composition, it is difficult to accurately design an amount of change in device characteristics because a chemical reaction mechanism that changes through a redox reaction of organic matter or a reaction with outside air is used as an operation principle. However, in order to recognize various intermediate states other than the on state and the off state as the stages of adaptive learning with their respective importances, and to design them, it is necessary to accurately define the index of variation of device characteristics according to the change of applied voltage, and to design the relationship. It is desirable to employ the principle of operation.

Second, some organic-based memristor devices fabricated on flexible substrates that report memory functions have the problem that the margins of the on and off states are too small. In order to realize the adaptive learning function of the memristor device stably, it is desirable to define various intermediate states that are stably implemented between the on state and the off state.

Third, we report similar performances to the adaptive learning function of memristors in atomic switch or field effect transistor devices using some silicon substrates, but these devices are basically fabricated on silicon substrates and integrated with silicon-based devices. This has a problem that the manufacturing process is complicated or that a particularly high process temperature is required. In particular, the conventional flexible plastic substrate used in flexible electronics has the highest heat resistance of about 300 ℃ as the highest temperature, it is preferable to perform the temperature of the process applied for manufacturing the device at a low temperature.

As such, there is no method for fabricating the memristor device on a flexible substrate and applying it as a core device of next-generation flexible electronics by using the adaptive learning function of the memristor device.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a memristor device using an oxide semiconductor thin film layer and an organic ferroelectric thin film layer as a channel layer and a gate insulation layer of a thin film transistor, respectively.

Another object of the present invention is to provide a method of manufacturing a memristor apparatus, which is manufactured on a flexible substrate using a low temperature process.

According to a first embodiment of the present invention for achieving the above object, a memristor apparatus according to the present invention comprises a substrate; A substrate barrier insulating layer formed on the substrate to reduce mechanical stress of the substrate generated in the bending operation of the substrate; A source electrode layer formed on one side of the substrate barrier insulating layer; A drain electrode layer formed on the other side of the substrate barrier insulating layer; An oxide semiconductor thin film layer formed on the substrate barrier insulating layer between the source electrode layer and the drain electrode layer to form a channel region; A protective insulating layer formed on the oxide semiconductor thin film layer to protect the oxide semiconductor thin film layer; An organic ferroelectric thin film layer formed on the source electrode layer, the drain electrode layer, and the protective insulating layer, and used as a gate insulating layer; And an upper gate electrode layer formed on the organic ferroelectric thin film layer on the upper side of the channel region.

As described above, according to the present invention, by providing a memristor transistor having an adaptive learning function on a flexible plastic substrate, the channel resistance value of various states can be arbitrarily set by changing a voltage signal application method, or the characteristics of the device can be changed. A memristor transistor having an adaptive learning function that can be dynamically controlled can be provided.

In addition, by providing an adaptive learning-type flexible memristor device, the present invention can greatly contribute to the realization of an electronic device having improved functionality and new applicability in the field of flexible electronics to be developed in the future.

1 is a cross-sectional view of a memristor transistor according to a first embodiment of the present invention;
2 is a cross-sectional view of a memristor transistor according to a second embodiment of the present invention;
3 is a cross-sectional view of a memristor transistor according to a third embodiment of the present invention;
4 is a cross-sectional view of a memristor transistor according to a fourth embodiment of the present invention;
5A to 5C are schematic diagrams illustrating an operation principle of a memristor transistor expressing a memory function and an adaptive learning function according to the present invention;
6A to 6D are diagrams schematically illustrating a correlation between ferroelectric spontaneous polarization and transistor drain current according to voltage application conditions and voltage application for implementing an adaptive learning function of a memristor transistor according to the present invention;
FIG. 7 shows that the drain current value and the memory on / off ratio of the thin film transistor device fabricated using the oxide semiconductor thin film layer and the organic ferroelectric thin film layer as the semiconductor channel layer and the gate insulating film layer, respectively, according to the change of the voltage pulse width applied for the program operation. Graph showing tendency to
8 is a graph illustrating gate voltage and drain current characteristics of a memristor transistor according to a first embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a cross-sectional view of a memristor transistor according to a first embodiment of the present invention.

As shown in FIG. 1, the memristor transistor according to the present invention includes a substrate barrier insulating layer 102, a source and drain electrode layer 104a and 104b, an oxide semiconductor thin film layer 106, and a protective insulating layer formed on the substrate 100. A layer 108, an organic ferroelectric thin film layer 110, and an upper gate electrode layer 114 are included. In addition, the plurality of contact via holes 112 and the plurality of contact via holes 112 respectively connected to the source and drain electrode layers 104a and 104b and the upper gate electrode layer 114 formed at predetermined intervals on the barrier insulating layer 102 are formed. Source and drain electrode pads 116a and 116b and gate electrode pads (not shown) respectively connected to the source and drain electrode layers 104a and 104b and the upper gate electrode layer 114 are further included.

Hereinafter, each component will be described in detail.

The substrate 100 is preferably made of a plastic material in order to secure the flexibility of the memristor transistor according to the present invention. Specifically, polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate ( PET), polyvinyl chloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), Polyacetal (POM), polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), Polyvinyl acetal, polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP) ), Epoxy resin (EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures thereof and It may consist of one of the compounds.

The substrate barrier insulating layer 102 may be formed of an inorganic or organic insulating layer having electrical insulation properties, and may have a predetermined structure to reduce mechanical stress caused by bending of the substrate 100. It can be formed in the form of a laminated film. For example, the substrate barrier insulating film layer 102 is formed of a silicon-based insulating film such as a silicon oxide film (SiO ₂ ), a silicon nitride film (SiNx), a silicon oxynitride film (SiON) as an inorganic insulating film, or an aluminum oxide film as an organic insulating film. (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), or the like, and may be formed of an oxide film in which two or more metal elements are mixed.

At this time, the role of the substrate barrier insulating layer 102 in the memristor transistor proposed in the present invention is as follows.

The first role is to improve the flatness of the surface of the plastic material substrate 100.

The second role is to prevent the gas component contained in the plastic material is discharged to the upper portion of the substrate 100 to adversely affect the device characteristics.

The third role is to prevent the moisture contained in the outside air penetrates through the plastic material to adversely affect the device characteristics.

The fourth role is to reduce the mechanical stress generated in the substrate 100 through a predetermined heat treatment process performed in the manufacturing process of the memristor transistor according to the present invention manufactured using the plastic substrate. However, in order to achieve this purpose, the material and the laminated structure of the substrate barrier insulating layer 102 should be appropriately designed to minimize the stress generated on the substrate 100.

On the other hand, the substrate barrier insulating film layer 102 needs to strictly control the process temperature in consideration of the heat resistance of the substrate 100. In the case of the inorganic layer barrier insulating layer, a deposition method that can be introduced in a general inorganic thin film forming process such as atomic layer deposition, sputtering, spin-coating, or the like can be used. In addition, in the case of the organic layer barrier insulating layer, a deposition method that can be introduced in a general organic thin film forming process, such as spin coating, thermal evaporation, and langmere blowjet (LB), may be used. The substrate barrier insulating layer 102 may be formed under conditions of optimum deposition conditions to ensure excellent flatness and electrical insulation even at low temperatures.

The source and drain electrode layers 104a and 104b are preferably formed of a metal electrode layer or a conductive oxide thin film layer. In some cases, the source and drain electrode layers 104a and 104b may be formed of a metal stacked electrode layer having a predetermined structure or a stacked electrode layer including both a conductive oxide thin film layer and a metal thin film layer. It may be formed in the form. One of the most important factors to consider in selecting the material constituting the source and drain electrode layers 104a and 104b is that the oxide semiconductor thin film layer 106, which is to serve as the semiconductor channel of the memristor transistor according to the present invention, is good. It is necessary to realize the electrical contact characteristics. For example, titanium (Ti) as the metal electrode layer material, indium tin oxide (In-Sn-O, ITO), indium zinc oxide (In-Zn-O), aluminum-zinc oxide as the conductive oxide thin film material It is preferable to employ (Al-Zn-O) or the like, and other metals such as molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), silver (Ag), and copper (Cu) An electrode layer can be used. In addition, the material may be stacked and used in a two-layer or three-layer structure to satisfy the requirements of the application system.

Here, the source and drain electrode layers 104a and 104b are composed of a source electrode layer 104a and a drain electrode layer 104b formed at predetermined intervals in two regions electrically separated on the substrate barrier insulating film layer 102. . The region between the source electrode layer 104a and the drain electrode layer 104b is defined as a channel region of the memristor transistor. Therefore, the channel width and length of the memristor transistor are determined by the pattern width and the distance between the patterns of the source and drain electrode layers 104a and 104b. At this time, it is desirable to properly design the channel width and length in consideration of the operation characteristics of the memristor transistor.

The oxide semiconductor thin film layer 106 is formed on the substrate 100 between the source electrode layer 104a and the drain electrode layer 104b, specifically, on the substrate barrier insulating layer 102. That is, it is formed in the channel region of the memristor transistor according to the present invention, and may be formed to cover sidewalls and upper portions of the source and drain electrode layers 104a and 104b. The oxide semiconductor thin film layer 106 serves as a semiconductor of the memristor transistor, and in particular, is formed of an oxide semiconductor. In this case, the oxide semiconductor thin film layer 108 is preferably formed of a transparent oxide semiconductor thin film which is an oxide having a broad energy bandgap and a transparent property in the visible light region and electrically having semiconductor properties. For example, zinc oxide (ZnO), indium-gallium-zinc oxide (In-Ga-Zn-O), zinc-tin oxide (Zn-Sn-O), or zinc, indium, gallium, tin, aluminum It may be formed of an oxide containing at least two elements. Alternatively, the above-mentioned oxide may be formed by doping various elements.

The oxide semiconductor thin film layer 106 is an oxide such as a sputtering method, a chemical vapor deposition method, an atomic layer deposition method, a pulsed-laser deposition, a spin coating method using a sol-gel solution, a printing method using a precursor ink, and the like. Any deposition method commonly used to form thin films can be used. Of course, these methods can also be used in combination or in combination. In addition, the temperature of the deposition process of the oxide semiconductor thin film layer 106 needs to strictly control the process temperature in consideration of the heat resistance of the substrate 100. Preferably, it is necessary to optimize the material composition and process conditions of the oxide semiconductor thin film layer 106 so that a good operating performance of the memristor transistor can be expressed even at a lower temperature.

Since the thickness of the oxide semiconductor thin film layer 106 is one of important device variables for determining the operating conditions of the memristor transistor, it is preferable to determine the thickness in consideration of the following matters.

First, the thickness of the oxide semiconductor thin film layer 106 is determined within a range capable of securing operating characteristics of the transistor element using the oxide semiconductor thin film layer 106 as a channel layer. In general, in order to function as a semiconductor thin film in the channel region of the thin film transistor, it is preferable to form the oxide semiconductor thin film layer 106 with a thickness of 5 to 50 nm. If the film thickness is thinner than 5 nm, the film thickness may become thinner than the average moving distance of the carrier moving on the surface of the semiconductor thin film, which may cause the carrier mobility to be greatly reduced. On the other hand, if the film thickness is greater than 50 nm, the carrier concentration inside the semiconductor thin film is excessive, resulting in an increase in the off current and a decrease in the on / off operation margin of the transistor in the electrical operating characteristics of the thin film transistor. When is high, the operation of the driving transistor itself cannot be ensured. Therefore, in consideration of the first matter, the thickness of the oxide semiconductor thin film layer 106 is preferably 5 to 50 nm.

Second, it is preferable to determine the thickness of the semiconductor thin film layer 106 so that the memory operation of the memristor transistor can be performed at a lower voltage. In the present specification, the description of the quantitative calculation for determining the operating voltage of the memristor transistor is omitted, but the operating voltage of the memristor transistor according to the present invention is programmed to perform the anti-stimulation period operation rather than performing the stimulation period operation of the synapse. Higher operating voltages are required. The reason is that in the case of the oxide semiconductor thin film, unlike the conventional silicon semiconductor which operates in the inversion layer and the accumulation layer according to the change of the applied voltage, the oxide semiconductor thin film operates in the depletion layer and the accumulation layer according to the change of the applied voltage. This is because the oxide semiconductor thin film under certain voltage conditions is completely depleted and behaves like an insulator. Under these conditions, the loss of programming voltage is caused by a series capacitor formed due to the presence of a fully depleted layer of the oxide semiconductor thin film on the gate stack structure of the transistor, resulting in an increase in the programming operating voltage of the anti-stimulation period operation. It causes. Therefore, in order to suppress such effects to the possible level and reduce the programming voltage of the anti-stimulation cycle operation, it is necessary to reduce the thickness of the fully depleted layer of the oxide semiconductor thin film as much as possible, which is to reduce the thickness of the oxide semiconductor thin film layer 106 as much as possible. That means you need to reduce it. Therefore, in consideration of the second point, the deposition thickness of the oxide semiconductor thin film layer 106 is preferably 20 nm or less.

As a result, considering the first and second points at the same time, the thickness of the oxide semiconductor thin film layer 108 is more preferably determined in the range of 5 to 20nm.

The protective insulating layer 108 is preferably formed of an oxide insulator thin film. For example, the protective insulating layer 108 is formed of a silicon-based insulating film such as a silicon oxide film (SiO ₂ ), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), or the like. It may be formed of an aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), or the like, and may be formed of an oxide film in which two or more metal elements are mixed. . It may also be formed of a silicate insulating film in which the metal elements and silicon constituting the aforementioned oxides are mixed. In addition, it may be formed of oxide insulating materials that can be used as a gate insulating material in the manufacture of a conventional oxide thin film transistor.

The protective insulating layer 108 is formed for the purpose of preventing damage to the oxide semiconductor thin film layer 106 in a subsequent process and improving the characteristics of the memristor transistor of the present invention. The protective insulating layer 108 is formed on the oxide semiconductor thin film layer 106, and is formed in the channel region between the source electrode layer 104a and the drain electrode layer 104b together with the oxide semiconductor thin film layer 106. It may be formed to cover portions of the sidewalls and the upper portions of the electrode layers 104a and 104b.

At this time, the role of the protective insulating layer 108 in the memristor transistor proposed in the present invention will be described in detail.

First, the process degradation of the oxide semiconductor thin film layer 106 is suppressed during the etching process and the etching mask removal process of the oxide semiconductor thin film layer 106. When the protective insulating film layer 108 is not provided in the above process, chemicals such as photoresist, photoresist developer, and photoresist stripper directly act on the oxide semiconductor thin film layer 106 to prevent the material of the oxide semiconductor thin film layer 106. Properties may deteriorate. Accordingly, by forming the protective insulating layer 108 on the oxide semiconductor thin film layer 106, it is possible to prevent the oxide semiconductor thin film layer 108 from being chemically deteriorated.

Second, by preventing the oxide semiconductor thin film layer 106 from being damaged and deteriorated during the subsequent process, the oxide semiconductor thin film layer 106 faithfully plays a role as a semiconductor, and thus the memristor transistor has good operating characteristics. In detail, the protective insulating layer 108 suppresses chemical degradation of the oxide semiconductor thin film layer 106 when the organic ferroelectric thin film layer 110 to be formed in a subsequent process is formed. The organic ferroelectric thin film layer 110 is formed by a coating process using an organic solution. In this case, material characteristics of the oxide semiconductor thin film layer 106 may be degraded according to the type of organic solution used. Therefore, by forming the protective insulating film layer 108 on the oxide semiconductor thin film layer 106, it is possible to prevent the oxide semiconductor thin film layer 106 from chemically deteriorating.

Third, the electrical characteristics of the oxide semiconductor thin film layer 106 may be changed by changing the material type and process conditions of the protective insulating layer 108. In particular, when the protective insulating layer 108 is formed, the operating conditions of the memristor transistor may be improved by changing the carrier concentration and the chemical state of the surface of the oxide semiconductor thin film layer 106 by changing the process conditions.

Fourth, the protective insulating layer 108 serves as an electrical protective film to suppress the leakage current of the organic ferroelectric thin film layer 106 to be formed in a subsequent process. In the organic ferroelectric thin film layer 110 constituting the memristor transistor of the present invention, the leakage current increases greatly as the thickness of the organic ferroelectric thin film layer 110 proceeds, which may act as a cause of decisively reducing the operation characteristics of the memristor transistor. Accordingly, the protective insulating layer 108 may be provided between the organic ferroelectric thin film layer 110 and the oxide semiconductor thin film layer 106 to prevent deterioration of characteristics of the memristor transistor due to leakage current.

Considering the role of the protective insulating layer 108 as described above, the protective insulating layer 108 is, first, can sufficiently suppress the process degradation of the oxide semiconductor thin film layer 106, and second, the protective insulating layer 108 It is preferable that the adaptive learning function of the memristor transistor can be improved by the introduction thereof, and third, it is formed to have an electrical property capable of sufficiently suppressing the leakage current of the organic ferroelectric thin film layer 110.

In this case, the thickness of the auxiliary insulating layer 108 is a very important device parameter that determines the operation characteristics of the memristor transistor, and it is preferable to determine the thickness of the auxiliary insulating layer 108 in consideration of the following matters.

First, the operating voltage of the memristor transistor must be determined in such a range that it does not increase too much. That is, when the thickness of the auxiliary insulating layer 108 is too thick, a part of the driving voltage of the memristor transistor is consumed in the series capacitor generated by the auxiliary insulating layer 108 forming part of the gate stack of the transistor, and thus the operating voltage as a whole. This may cause the to rise. Therefore, in consideration of the first matter, the thickness of the auxiliary insulating layer 108 is preferably determined in the range of 10 nm or less.

Second, in the etching process of the oxide semiconductor thin film layer 106, it should be determined in a range that can sufficiently suppress the process degradation caused by various chemicals.

Third, it should be determined in a range capable of sufficiently suppressing the leakage current of the organic ferroelectric thin film layer 108 to be formed in a subsequent process.

Therefore, in consideration of the second and third considerations, the thickness of the auxiliary insulating layer 108 is preferably 4 nm or more. As a result, when considering the first to third points at the same time, the thickness of the auxiliary insulating film layer 108 is preferably determined in the range of 4 to 10nm.

The organic ferroelectric thin film layer 110 is used as a gate insulating film of the transistor for implementing the memory operation and adaptive learning function of the memristor transistor of the present invention, and the residual polarization according to the application of voltage to an organic material, that is, a low-molecular or high-molecular organic material It is formed of an organic material having ferroelectric properties.

For example, the organic ferroelectric thin film layer 110 may be formed of P (VDF-TrFE), a copolymer in which poly (Vinylidene Fluoride) (P (VDF)) and trifluorotethylene (TrFE) in an appropriate ratio are mixed with P (VDF). The mixed composition range of P (VDF) and TrFE can be adjusted within a range in which P (VDF-TrFE) exhibits ferroelectric properties, for example, preferably 55% or more of P (VDF). , The mixed composition range is more preferably adjusted at an appropriate ratio to optimize the leakage current characteristics and ferroelectric properties of the organic ferroelectric thin film layer (110).

The organic ferroelectric thin film layer 110 is preferably formed by a spin coating method. For example, when the P (VDF-TrFE) is selected to form the organic ferroelectric thin film layer 110, a raw material solution is typically prepared by dissolving P (VDF-TrFE) raw material in a solid grain form in an appropriate organic solvent. can do. A general procedure for forming the organic ferroelectric thin film layer 110 by the spin coating method is as follows. First, the raw material solution is added dropwise onto a predetermined substrate and coated under appropriate spin coating conditions, and then heat treatment is performed at a predetermined temperature to volatilize the organic solvent included in the raw material solution. Subsequently, heat treatment is performed at a predetermined temperature for crystallization of the organic ferroelectric film. Typically, the temperature of the heat treatment process for volatilizing the organic solvent may vary depending on the organic solvent used, but is preferably performed at 50 to 120 ° C. In addition, the temperature of the heat treatment process for crystallization may vary depending on the type of organic ferroelectric material used, but when P (VDF-TrFE) is used as the organic ferroelectric material, it is preferably carried out at a temperature of 120 to 160 ℃ Do. In this case, in order for the organic ferroelectric thin film layer 110 to have a good ferroelectric property, it is very important to select a crystallization temperature because the crystallization process of the thin film is essential. If the temperature of the crystallization process is too low, the crystallinity of the thin film is insufficient to obtain the desired electrical properties. On the contrary, if the temperature of the crystallization process is too high, the formed thin film may be completely melted and lose ferroelectric properties. As illustrated, since the crystallization temperature of P (VDF-TrFE), which is an organic ferroelectric material, is within the heat resistance range of the plastic substrate material that is commonly used, it is easy to manufacture the memristor transistor of the present invention.

On the other hand, when the organic ferroelectric thin film layer 110 is formed by the spin coating method, the thickness of the organic ferroelectric thin film layer 110 may be adjusted by controlling the rotation speed of the spin coating process and the concentration of the organic ferroelectric raw material solution. Here, in order to select an appropriate thickness of the organic ferroelectric thin film layer 110, two things should be considered.

First, it is desirable to select the operation voltage of the memristor transistor in a direction that can lower as much as possible. To this end, it is desirable to reduce the thickness of the organic ferroelectric thin film layer 110 so that polarization can be easily reversed even at a relatively low applied voltage. However, according to the existing research results, when the thickness of the organic ferroelectric thin film is thinned below a certain thickness, the ferroelectricity of the thin film itself is greatly deteriorated, so that the electric field value at which polarization reversal occurs increases, and the time required for polarization reversal even in the same electric field. It is known that this very long phenomenon occurs. Although the value of the critical film thickness at which such deterioration occurs may vary depending on which electrode is used above and below the organic ferroelectric, it is generally known to be remarkably observed at a film thickness of 50 nm or less.

Second, it is preferable to select in a direction that can improve the data retention characteristics of the memory transistor, that is, the memory transistor. Since the data retention time of the memory transistor is closely related to the leakage current characteristics of the organic ferroelectric thin film layer 110, it is necessary to optimize the deposition thickness of the organic ferroelectric thin film layer 110 so that excessive leakage current does not occur during operation of the device. There is. According to the research results, it is known that a remarkable leakage current does not occur depending on the applied voltage when the thickness of the organic ferroelectric film is about 200 nm.

Therefore, the deposition thickness of the organic ferroelectric thin film layer 110 is preferably selected in the range of 50 to 200nm in consideration of both the first point and the second point. However, if a method for obtaining excellent ferroelectric properties is developed even if the organic ferroelectric film is further thinned according to future technology development, the lower deposition thickness lower limit of the organic ferroelectric thin film layer 110 may be further reduced.

The upper gate electrode layer 114 is positioned on a portion of the upper portion of the organic ferroelectric thin film layer 110, and in particular, is positioned on the channel region of the memristor transistor. The upper gate electrode layer 114 may be formed of a metal electrode layer or a conductive oxide thin film layer. For example, various metal electrode layers such as titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), silver (Ag) and copper (Cu) may be used as the metal electrode layer material. The conductive oxide thin film layer material may be an indium tin oxide (In-Sn-O, ITO), or an indium zinc oxide (In-Zn-O) thin film layer. In addition, the material may be stacked and used in a two-layer or three-layer structure to satisfy the requirements of the application system.

Here, it should be noted that the formation process and the patterning process of the upper gate electrode layer 114 should be designed so as not to damage the organic ferroelectric thin film layer 110 below. The reason for this is as follows.

First, the deposition process of a conventional conductive thin film using plasma is an electrical component of the organic ferroelectric thin film layer 110 which is a very important component to realize the memory operation and adaptive learning function of the device in the construction of the memristor transistor of the present invention. This is because the mechanical thin film properties may be greatly deteriorated.

Second, for example, when a conductive oxide thin film layer such as ITO is used as the material of the upper gate electrode layer 114, a subsequent heat treatment process is often performed at a predetermined temperature after the deposition process in order to improve conductivity of the electrode. As described above, when P (VDF-TrFE) is used as the material of the organic ferroelectric thin film layer 110, the process temperature for the subsequent process cannot be set to a temperature higher than the melting point of P (VDF-TrFE).

Third, when P (VDF-TrFE) is used as the material of the organic ferroelectric thin film layer 110, the roughness of the surface of P (VDF-TrFE) is very high, and thus the adhesion to the commonly used conductive oxide thin film layer is not good. This is because the patterning of the healthy shape becomes very difficult during the etching process.

Accordingly, the upper gate electrode layer 114 may be optimized to optimize the type of electrode material, deposition process method, subsequent heat treatment process temperature, and etching process conditions so as not to damage the organic ferroelectric thin film layer 110. As an example of the deposition process method, it is preferable to use a vacuum thermal deposition method, an electron beam deposition method, or the like, which does not use plasma during the process, and in the case of forming the upper gate electrode layer 114 by a sputtering method using plasma. There is a need to optimize the structure and deposition conditions of the equipment.

The source and drain electrode pads 116a and 116b are electrically connected to the source and drain electrode layers 104a and 104b through a contact via hole 112 formed through a portion of the organic ferroelectric thin film layer 110. As an example, the contact via hole 112 of the memristor transistor is formed to penetrate the organic ferroelectric thin film layer 110. In this process, the organic ferroelectric thin film layer 110 in the region where the source and drain electrode pads 116a and 116b are to be selectively removed is selectively removed. For example, after forming a photoresist pattern on the organic ferroelectric thin film layer 110, the organic ferroelectric thin film layer 110 is etched using the photoresist pattern as an etching mask. Next, the photoresist pattern which is an etching mask is removed. Here, the etching process of the organic ferroelectric thin film layer 110 should consider the following two points.

First, when etching the organic ferroelectric thin film layer 110 using an oxygen plasma, it is necessary to optimize the conditions of the oxygen plasma so that the characteristics of the oxide semiconductor thin film layer 106 is not degraded. In general, the oxide semiconductor thin film layer 106 has a possibility that the characteristics of the surface and the inside of the thin film are significantly changed by the plasma treatment. Of course, although the auxiliary insulating layer 108 serves as a protective film of the oxide semiconductor thin film layer 106 during the etching process of the organic ferroelectric thin film layer 110, the oxygen plasma condition so that the characteristics of the oxide semiconductor thin film layer 106 do not deteriorate. Needs to be optimized.

Second, a stripping solution that does not affect the characteristics of the organic ferroelectric thin film layer 110 should be selected during the stripping process of the photoresist pattern used as an etching mask. Since chemicals for stripping of the photoresist pattern generally used may have a fatal effect on the characteristics of the organic ferroelectric thin film layer 110, sufficient care should be taken in selecting the stripping solution. In addition, the photoresist pattern removal process uses a kind of dry etching process using plasma in vacuum, unlike general wet etching, so that the photoresist pattern is more hardened and the photoresist pattern is removed in an unfavorable condition. Some of the organic ferroelectric thin film layer 110 may remain.

The characteristics which the peeling solution applicable in this process should have are as follows. The first property is that the constituents of the stripper should not have a chemical effect on the organic ferroelectric thin film layer 110. For example, in the case of an organic ferroelectric thin film formed of P (VDF-TrFE), the constituents of the stripping solution should not chemically disassemble P (VDF-TrFE) to cause the removal of the thin film, and P (VDF-TrFE) Although not removed, the crystal state or chemical bonding state of P (VDF-TrFE) should not be changed significantly, resulting in serious changes in the electrical properties of P (VDF-TrFE). For example, in the case of acetone, which is one of the organic chemicals generally applied for peeling a photoresist pattern, it has a function of completely dissolving and removing P (VDF-TrFE). It is not possible to use acetone as a stripping solution in the method. The second property is that the stripper must be able to completely remove the residual components of the photoresist pattern. If the stripper cannot remove the remaining components of the photoresist pattern sufficiently effectively, the remaining components of the photoresist pattern remain on a part of the substrate on which the device of the present invention is formed, so that the device of the present invention is normally There is a possibility of acting as a factor to prevent operation. For example, although organic chemicals based on methanol may be used for peeling the photoresist pattern, residues of the photoresist may be used with methanol depending on the type of photoresist pattern used and the effects of the preceding process. Cannot be removed completely.

The source and drain electrode pads 116a and 116b may be formed of a metal electrode layer or a conductive oxide thin film layer. The source and drain electrode pads 116a and 116b may be formed by the same batch process on the same plane as the upper gate electrode layer 114 on the organic ferroelectric thin film layer 110. Therefore, the source and drain electrode pads 116a and 116b may be formed of the same material as the upper gate electrode layer 114.

2 is a cross-sectional view of a memristor transistor according to a second embodiment of the present invention.

As shown in FIG. 2, the memristor transistor according to the present invention includes a substrate barrier insulating layer 202, an oxide semiconductor thin film layer 204, a protective insulating layer 206, a source and a drain electrode layer formed on the substrate 200. 208a and 208b, an organic ferroelectric thin film layer 210 and an upper gate electrode layer 214. In addition, the plurality of contact via holes 212 and the plurality of contact via holes 212 connected to the source and drain electrode layers 208a and 208b and the upper gate electrode layer 214 formed at predetermined intervals on the substrate barrier insulating layer layer 202 may be formed. Source and drain electrode pads 216a and 216b and gate electrode pads (not shown) respectively connected to the source and drain electrode layers 208a and 208b and the upper gate electrode layer 214 are further included.

The structure of the memristor transistor according to the second embodiment shown in FIG. 2 is different from that of the memristor transistor according to the first embodiment shown in FIG. 1 as follows.

The oxide semiconductor thin film layer 204 is formed on the substrate barrier insulating film layer 202, and the source and drain electrode layers 208a and 208b are formed to cover the sidewalls and a part of the upper portion of the oxide semiconductor thin film layer 204. The semiconductor device further includes a protective insulating layer 206 formed on the oxide semiconductor thin film layer 204. As a result, the oxide semiconductor thin film layer 204 and the protective insulating film layer 206 are formed in the channel region of the memory thin film transistor in the same manner as the device structure provided in the first embodiment, but the oxide semiconductor thin film layer 204 and The positional relationship between the source and drain electrode layers 208a and 208b is different. The structure in which the gate electrode layer is formed on the gate insulating film is generally referred to as a top gate structure. In the thin film transistor having the top gate structure, the structure according to the first embodiment is referred to as a top gate-bottom contact. The structure according to this is called a top gate-top contact structure.

As shown in FIG. 2, in the structure of the memristor transistor according to the second embodiment, the protective insulating layer 206 serves as the protective insulating layer 108 described with reference to the first embodiment of FIG. 1. Together, we can expect the following roles:

Since the source and drain electrode layers 208a and 208b are formed after the oxide semiconductor thin film layer 204, the oxide semiconductor thin film layer 204 when performing the patterning process of the source and drain electrode layers 208a and 208b using a wet or dry etching process. It is possible to effectively prevent the process degradation phenomenon that can act on the), and to prevent the material properties of the oxide semiconductor thin film layer 204 from deteriorating. Accordingly, the protective insulating layer 206 may simultaneously serve as an etching control layer for etching the source and drain electrode layers 208a and 208b in the device structure according to the second embodiment. In consideration of the role of the protective insulating layer 206, the protective insulating layer 206 may firstly be sufficiently capable of deteriorating the process of the oxide semiconductor thin film layer 204 in the etching process of the source and drain electrode layers 208a and 208b. Secondly, it is preferable to form the material which can suppress and sufficiently secure the etching selectivity between the upper and lower constituent layers.

The components and manufacturing method of the memristor transistor according to the second embodiment of the present invention shown in FIG. 2 are the same as the components and manufacturing method of the memristor transistor according to the first embodiment of the present invention shown in FIG. Therefore, duplicate description is omitted.

3 is a cross-sectional view of a memristor transistor according to a third embodiment of the present invention.

As shown in FIG. 3, the memristor transistor according to the present invention includes a substrate barrier insulating layer 302, a lower gate electrode layer 304, an organic ferroelectric thin film layer 306, and an oxide semiconductor thin film layer 310 formed on the substrate 300. ) And a protective insulating film layer 312. And source and drain electrode layers 308a and 308b formed on the organic ferroelectric thin film layer 306 at predetermined intervals. And a plurality of contact via holes (not shown) connecting the source and drain electrode pads (not shown), the lower gate electrode layer 304, and the gate electrode pads (not shown). Although not shown in the drawings, a second protective insulating layer (not shown) may be further included on the protective insulating layer 312 to protect the entire surface of the device.

The structure of the memristor transistor according to the third embodiment shown in FIG. 3 is different from that of the memristor transistor according to the first embodiment shown in FIG. 1. The bottom of the gate electrode is first formed on the substrate 300. It has the structure of a gate. On the other hand, since the oxide semiconductor thin film layer 310 forms the channel layer in the form of bottom contact after the source and drain electrode layers 308a and 308b are formed, the structure of the transistor according to the first embodiment shown in FIG. 1 is the same. .

In the structure of the memristor transistor of the present invention having the bottom gate-bottom contact structure shown in FIG. 3, the organic ferroelectric thin film layer 306 is formed earlier than the oxide semiconductor thin film layer 310. Therefore, the following points should be considered in the manufacturing process of the device.

First, the deposition method and process temperature of the oxide semiconductor thin film layer 310 and the protective insulating layer 312 should be determined so as not to damage the organic ferroelectric thin film layer 306 below. More specifically, in the deposition process of the oxide semiconductor thin film layer 310 and the protective insulating layer 312, it is preferable to employ a deposition method that does not use plasma, and the reason is as described above. In addition, the process temperatures of the oxide semiconductor thin film layer 310 and the protective insulating film layer 312 should be controlled to 150 ° C or less. This is because P (VDF-TrFE), a typical organic ferroelectric material that is commonly used, may fail to secure certain electrical characteristics when the material has a higher melting point around 155 ° C. to be. Although the limitation of the process temperature is limited by the heat resistance of the plastic substrate to be used, even if a plastic substrate having higher heat resistance is used as the substrate material, in the case of a memistor transistor having a bottom gate structure shown in FIG. It should be noted that is limited to 150 ° C.

Second, after the oxide semiconductor thin film layer 310 is formed, the process temperature of the subsequent heat treatment process that can be performed to improve the operation of the memristor transistor device of the present invention should also be suppressed to 150 ° C or less. At this time, since the temperature conditions required in the subsequent heat treatment process are largely dependent on the material composition of the oxide semiconductor thin film layer 310 to be used, the oxide semiconductor thin film layer 310 of the oxide semiconductor thin film layer 310 can be secured even through a low temperature subsequent heat treatment process. It is desirable to determine the material composition.

Third, since the oxide semiconductor thin film layer 310 is most finally formed except for the protective insulating film layer 312 and is exposed in a state close to the outside air, the protective insulating film layer 312 has an oxide semiconductor from outside air in addition to the above-described effects. Consideration should be given to the additional role of protecting the thin film layer.

Except as described above, the components and the manufacturing method of the memristor transistor according to the third embodiment of the present invention shown in FIG. 3, the memristor according to the first embodiment of the present invention shown in FIG. Since the components are the same as the components of the transistor and the manufacturing method thereof, redundant description thereof will be omitted.

4 is a cross-sectional view of a memristor transistor according to a fourth embodiment of the present invention.

As shown in FIG. 4, the memristor transistor according to the present invention includes a substrate barrier insulating layer 402, a lower gate electrode layer 404, an organic ferroelectric thin film layer 406, and an oxide semiconductor thin film layer 410 formed on the substrate 400. ) And a protective insulating film layer 412. And source and drain electrode layers 408a and 408b formed on the organic ferroelectric thin film layer 406 at predetermined intervals. And a plurality of contact via holes (not shown) connecting the source and drain electrode pads (not shown), the lower gate electrode layer 404, and the gate electrode pads (not shown). Although not shown in the drawings, a second protective insulating layer (not shown) may be further included on the protective insulating layer 412 to protect the entire surface of the device.

The structure of the memristor transistor according to the fourth embodiment shown in FIG. 4 differs from that of the memristor transistor according to the third embodiment shown in FIG. 3 in that the source and drain electrode layers 408a and 408b are divided into oxide semiconductor thin film layers. 410 and the protective insulating layer 412 are formed after the formation. That is, it has a structure of bottom gate-top contact.

The memristor transistor of the present invention having the bottom gate-top contact structure has both the device structure of the bottom gate-bottom contact of the third embodiment and the device structure of the top gate-top contact of the second embodiment. Therefore, redundant description of technical matters to be considered through provision of each structure is omitted. In addition, except for matters to be considered due to the difference in structure, the same description as the components and manufacturing method of the memristor transistor according to the first embodiment of the present invention described with reference to FIG. 1 will not be repeated.

The method of manufacturing the memristor transistors according to the first to fourth embodiments described herein is presented as an example, and the present invention is not limited thereto. In addition, according to the structure of the entire system to be applied and the required process, the specific device structure and process conditions may be selected in the most appropriate form.

5A to 5C are schematic diagrams illustrating an operation principle of a memristor transistor expressing a memory function and an adaptive learning function. For convenience, the description of FIG. 5 illustrates the operation principle of the memristor transistor of the present invention using the top gate transistor device structure shown schematically. However, the operation principle of the present invention described with reference to FIGS. Commonly applied to memristor transistors according to the first to fourth embodiments.

Referring to FIG. 5A, the ferroelectric spontaneous polarization of the organic ferroelectric thin film layer 506 serving as a gate insulating layer in the memristor transistor according to the present invention is fully aligned toward the channel direction of the memristor transistor. Polarization). In order to make this state, in the case of the top gate transistor, it is necessary to apply a positive voltage to the upper gate electrode layer 510.

After the positive voltage is applied to the upper gate electrode layer 510, the ferroelectric spontaneous polarization completely aligned in the channel direction inside the organic ferroelectric thin film layer 506 is maintained in a nonvolatile state even when the application of the voltage is blocked. On the other hand, assuming that the oxide semiconductor thin film layer used in the manufacture of the thin film transistor is n-type, a large amount of carrier electrons are generated on the channel surface of the oxide semiconductor thin film layer 504 in the above state, so that the source electrode layer of the memristor transistor ( A large amount of current flows between the 502a and the drain electrode layer 502b, and the memristor transistor is turned on.

Referring to FIG. 5B, the ferroelectric spontaneous polarization of the organic ferroelectric thin film layer 506 is completely aligned toward the channel opposite direction of the memristor transistor. In order to make this state, in the case of the top gate transistor, it is necessary to apply a negative voltage to the upper gate electrode layer 510. After the positive voltage is applied to the upper gate electrode layer 510, the ferroelectric spontaneous polarization completely aligned in the opposite direction of the channel inside the organic ferroelectric thin film layer 506 is preserved in a non-volatile state even if the application of the voltage is blocked. In this state, carrier electrons are hardly generated on the channel surface of the oxide semiconductor thin film layer 504, so that almost no current flows between the source electrode layer 502a and the drain electrode layer 502b of the memristor transistor. OFF) status.

By using the two states described with reference to FIGS. 5A through 5B, a low resistance on state and a high resistance off state can be realized. If the data corresponds to data 0 and data 1, the flexible memristor element stores digital information. May be provided on the plastic substrate.

Referring to FIG. 5C, a state in which the ferroelectric spontaneous polarization of the organic ferroelectric thin film layer 506 is partially aligned (partial polarization) is schematically illustrated. In reality, the polarizations are arranged in a disordered direction inside the thin film, and effectively calculated and converted into the number of polarizations facing downwards and the number of polarizations facing upwards, as shown in FIG. 5C. Can be. In order to make this state, it is necessary to design some planned voltage application conditions, and a detailed method will be described in detail with reference to FIG. 6. On the other hand, in the above state, the amount of carrier electrons generated on the channel surface of the oxide semiconductor thin film layer 504 has a predetermined function relationship with the number of polarizations effectively directed in the channel direction in the organic ferroelectric thin film layer 506. As a result, one can expect different amounts of carrier electrons to occur depending on the state of polarization. Therefore, an intermediate current flows between the source electrode layer 502a and the drain electrode layer 502b of the memristor transistor in the on state of the memristor transistor of FIG. 5A and the off state of the memristor transistor of FIG. 5B. Therefore, if the current value of the intermediate state can be set in the memristor transistor, and it can be accumulated and amplified or reduced, the adaptive learning function can be implemented using the memristor transistor of the present invention.

6A to 6D are diagrams schematically showing a correlation between ferroelectric spontaneous polarization and transistor drain current according to voltage application conditions and voltage application for implementing an adaptive learning function of a memristor transistor according to the present invention.

Referring to FIG. 6A, a voltage pulse for applying a voltage to an organic ferroelectric thin film layer of a memristor transistor according to the present invention to partially arrange the ferroelectric spontaneous polarization of the organic ferroelectric thin film layer as shown in FIG. 5C. An example is shown. In this example, by adjusting the frequency of the voltage pulses having the same size and width, it is possible to adjust the number of voltage pulses applied for a predetermined time. This application method is called a pulse frequency modulation (PFM). In this method, the magnitude of the applied voltage is set to a value large enough to invert the polarization of the organic ferroelectric thin film layer to align in a predetermined direction, and the width of the applied voltage is set to a value sufficiently shorter than the time taken for the polarization of the organic ferroelectric thin film layer to invert. It is important to do.

Referring to FIG. 6B, the ferroelectric polarization amount of the organic ferroelectric thin film layer or the drain current of the memristor transistor increases in accordance with a predetermined function as the number of applied voltage pulses increases, and then saturates as the ferroelectric spontaneous polarization is completely aligned. Tend to Accordingly, in order to implement a transistor device having an arbitrary channel resistance through partially aligned ferroelectric spontaneous polarization in the memristor transistor according to the present invention, an applied voltage pulse having a predetermined frequency is applied for a predetermined time by varying the time, or When voltage pulses having different frequencies are applied for a time, memristor transistors having different channel resistance values can be obtained. For example, when a relatively low frequency voltage pulse indicated as PFM1 in FIG. 6A is applied to the organic ferroelectric thin film for a predetermined time, the memristor transistor exhibits a drain current value indicated as PFM1 in FIG. 6B, and induces a relatively high frequency voltage pulse denoted as PFM2. When a certain time is applied to the ferroelectric thin film layer, the drain current value represented by PFM2 is displayed. In addition, if voltage pulses of a constant frequency are continuously applied to the same memristor transistor, it is possible to continuously change the channel resistance of the transistor in real time according to the number of applied voltage pulses. In addition, although not shown in FIG. 6A, by applying the voltage pulses having the opposite polarity in the same manner, the ferroelectric spontaneous polarization amount or the increase / decrease direction of the drain current of the memristor transistor according to the number of voltage pulses applied may be reversed.

By using this function, the resistance value of a frequently accessed device can be lowered and the resistance value of a rarely accessed device can be increased. In addition, the resistance value of the device can be reduced by repetition of the stimulus signal, and the resistance value of the device can be increased by repetition of the suppression signal. This function is an adaptive learning function of the memristor transistor according to the present invention.

Referring to FIG. 6C, a voltage pulse is applied to the organic ferroelectric thin film layer of the memristor transistor according to the present invention to partially arrange the ferroelectric spontaneous polarization of the organic ferroelectric thin film layer as shown in FIG. 5C. Another example of is shown. In this example, by adjusting the pulse width of the voltage pulse having the same magnitude and frequency, it is possible to adjust the application time of the voltage pulse applied by a predetermined number of times. This application method is called pulse width modulation (PWM). In this method, the magnitude of the applied voltage is also large enough to invert the polarization of the organic ferroelectric thin film layer to align in a predetermined direction, and the width of the applied voltage is set to a value short enough to the time required for the polarization of the organic ferroelectric thin film layer to invert. It is important to do.

Referring to FIG. 6D, the ferroelectric polarization amount of the organic ferroelectric thin film layer or the drain current of the memristor transistor increases as the total application time increases with increasing width of the applied voltage by a predetermined function relationship, and the ferroelectric spontaneous polarization is completely aligned. As the state approaches, it tends to saturate. Accordingly, when an applied voltage pulse having a predetermined frequency is applied to the memristor transistor according to the present invention for a predetermined time with different pulse widths, memristor transistors having different channel resistance values can be obtained. For example, when a relatively short voltage pulse indicated by PWM1 in FIG. 6C is applied for a predetermined time, the memristor transistor shows a drain current value indicated by PWM1 in FIG. 6D, and a relatively long voltage pulse denoted by PWM2 is applied for a predetermined time. In one case, the drain current is indicated by PWM2. In addition, although not shown in FIG. 6C, by applying a voltage pulse having the opposite polarity in the same manner, the direction of increase or decrease of the ferroelectric spontaneous polarization according to the voltage pulse width or the drain current of the memristor transistor may be reversed.

The PFM method described with reference to FIGS. 6A through 6B and the PWM method described with reference to FIGS. 6C through 6D are as follows.

First, in the case of configuring an integrated circuit, it is advantageous to apply the PFM method to simplify the circuit configuration of the entire system, assuming that a voltage signal having a constant width is used as an input signal.

Second, in order to continuously change the channel resistance characteristics of the memristor transistors through the continuous application of voltage pulses for a predetermined signal application time, it is advantageous to apply the PFM method that can change the frequency of the applied signal by changing only the frequency.

Third, in the case of the memristor transistor implemented from the operating principle of the present invention, considering that the width of the voltage pulse should be shorter than the polarization time of the ferroelectric spontaneous polarization of the organic ferroelectric thin film layer, the channel resistance value is adjusted in a more detailed range. In order to achieve this, it is more advantageous to apply a PFM method that can apply a voltage pulse having a short width in a possible range than a PWM method in which the pulse width of the voltage pulse should be changed.

Although not shown in Figs. 6A and 6C, the partial polarization inversion can be realized by changing the amplitude of the applied voltage without changing the number of pulses or the pulse width of the applied voltage. However, in order to change the amplitude of the voltage pulse inside the circuit system that is already configured, not only the circuit configuration becomes very complicated, but also it is expected to solve a very complicated design problem in constructing an actual neural circuit system. Therefore, in the present invention, an example of implementing the adaptive learning function in the memristor transistor according to the present invention by changing the amplitude of the applied voltage will not be described in detail.

The advantages of the memristor transistor using the oxide semiconductor thin film layer and the organic ferroelectric thin film layer according to the present invention as the semiconductor channel layer and the gate insulating film layer, respectively, are compared with the memristor transistor which implements the adaptive learning function using the other operating principle proposed so far. The explanation is as follows.

First, since the memristor transistor of the present invention has a transistor structure using an oxide semiconductor thin film layer as a channel, very excellent on-off characteristics can be secured. The on-off ratio of the oxide semiconductor-based thin film transistor which is generally manufactured well is 10 ⁷ to 10 ⁸ , and the on-off ratio may be applied even when used as a memory transistor through a combination with an organic ferroelectric thin film layer. Moreover, since the memristor transistor according to the present invention is characterized by using an intermediate state between on and off analogously, it is absolutely desirable to secure a large range of on-off margins as much as possible. On the other hand, in the case of organic-based general memory devices fabricated on the flexible substrate, the on-off margin is only about several hundreds, so it is very difficult to secure a stable intermediate state.

Second, since the memristor transistor of the present invention utilizes the accurate operation resulting from the ferroelectric spontaneous polarization amount of the ferroelectric thin film layer, it provides an advantageous condition for designing the entire circuit or system by predicting the operation of the device. On the other hand, in the case of conventional memristor transistors using chemical reactions such as redox and diffusion of elements, it is difficult to accurately predict changes in device characteristics due to accumulation of applied signals. In addition, even in the case of the binary oxide-based material used in the most common memristor transistor, even the operation principle is not yet fully identified, which is a critical problem in ensuring the operation stability of the device.

Third, since all of the manufacturing methods provided for the production of memristor transistors according to the present invention can be carried out at a low temperature of 150 ° C. or lower, a process for applying a device on a flexible plastic substrate having poor heat resistance characteristics is usually performed. Offers advantages. The memristor transistor using the field effect of the ferroelectric thin film layer has been proposed before, but generally has a problem involving high temperature heat treatment in the deposition process and the crystallization process of the thin film because the material of the oxide type.

FIG. 7 shows that the drain current value and the memory on / off ratio of the thin film transistor device fabricated using the oxide semiconductor thin film layer and the organic ferroelectric thin film layer as the semiconductor channel layer and the gate insulating film layer, respectively, according to the change of the voltage pulse width applied for the program operation. It is a graph showing the tendency to do.

The results shown in FIG. 7 are provided to show the feasibility of the adaptive learning function of the memristor transistor according to the present invention, and are not the results obtained in the device manufactured on the actual plastic substrate. The device was fabricated on a glass substrate, and an oxide semiconductor thin film layer was formed of 10 nm of In—Ga—Zn—O and an organic ferroelectric thin film layer of 150 nm of P (VDF-TrFE) thin film. A 4 nm Al ₂ O ₃ was used as the protective insulating layer, and the device structure is a device having a top gate-bottom contact structure shown in FIG. 1. Except that it is fabricated on a glass substrate, the material and manufacturing method of the device is almost the same as proposed in the present invention, and it is sufficiently effective to verify the possibility of the adaptive learning function of the memristor transistor of the present invention using this device. You can judge.

Referring to FIG. 7, the program drain current of the thin film transistor tends to increase as the program voltage pulse width applied to implement the on state increases, and as the program voltage pulse width applied to implement the off state increases. It shows a tendency to decrease. That is, as shown in FIGS. 6A to 6D, it is possible to arbitrarily determine or continuously change the channel resistance values of the on state and the off state according to the change of the PFM or PWM voltage pulse application method. The result is. As a result, when the applied program voltage pulse width is changed from 100 milliseconds to 1 second, it can be seen that the ratio of the memory on / off margin varies from about 3 to 400. It should be noted that the program voltage pulse width required to obtain the maximum memory on-off margin is very long at 1 second. Therefore, if a short voltage pulse of about 10 milliseconds is applied continuously, It is expected that various intermediate state channel resistance values can be realized in the operation of the Lister transistor.

8 is a graph illustrating gate voltage and drain current characteristics of a memristor transistor according to a first embodiment of the present invention.

The memristor transistor device showing the measurement result shown in FIG. 8 is manufactured according to the first embodiment described with reference to FIG. 1 and has a structure of a top gate-bottom contact. A detailed manufacturing method provided in the embodiment of the device will be described below with reference to FIG. 1.

The substrate 100 was a polyethylene naphthalate (PEN) substrate, and the substrate barrier insulating layer 102 was an aluminum oxide film (Al ₂ O ₃ ) having a thickness of about 20 nm formed by atomic layer deposition. As the source and drain electrode layers 104a and 104b, a stacked Ti / Au / Ti thin film was used. The oxide semiconductor thin film layer 106 was formed of a zinc oxide (ZnO) thin film at a temperature of 150 ° C. by a sputtering method, and has a film thickness of 10 nm. As the protective insulating layer 108, an aluminum oxide film (Al ₂ O ₃ ) having a thickness of 6 nm was formed at a temperature of 150 ° C. by atomic layer deposition. As the organic ferroelectric thin film layer 110, a P (VDF-TrFE) thin film having a thickness of 100 nm was used. The thin film was formed by applying a spin coating method, the crystallization heat treatment temperature is 140 ℃. The etching process of etching the organic ferroelectric thin film layer 110 to form a plurality of contact via holes 112 was performed by an oxygen plasma etching method using a photoresist as an etching mask. As the source and drain electrode pads 116a and 116b, the gate electrode pad (not shown), and the upper gate electrode layer 114, an Au thin film was used.

Referring to FIG. 8, the memristor transistor fabricated on a flexible PEN plastic substrate has a counterclockwise direction due to the electric field effect of the ferroelectric gate insulating film as the gate voltage V _G is applied in the transfer characteristic of the drain current I _D. It can be seen that hysteresis of is observed. From this result, it can be seen that the memristor transistor according to the present invention can be manufactured on a flexible plastic substrate, and can function as a memristor element exhibiting the function of the nonvolatile memory.

The embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

100 substrate 102 substrate barrier insulating layer
104a: source electrode layer 104b: drain electrode layer
106: oxide semiconductor thin film layer 108: protective insulating film layer
110: organic ferroelectric thin film layer 112: a plurality of contact via holes
114: upper gate electrode layer 116a: source electrode pad
116b: drain electrode pad

Claims (1)

Board;
A substrate barrier insulating layer formed on the substrate to reduce mechanical stress of the substrate generated in the bending operation of the substrate;
A source electrode layer formed on one side of the substrate barrier insulating layer;
A drain electrode layer formed on the other side of the substrate barrier insulating layer;
An oxide semiconductor thin film layer formed on the substrate barrier insulating layer between the source electrode layer and the drain electrode layer to form a channel region;
A protective insulating layer formed on the oxide semiconductor thin film layer to protect the oxide semiconductor thin film layer;
An organic ferroelectric thin film layer formed on the source electrode layer, the drain electrode layer, and the protective insulating layer, and used as a gate insulating layer; And
An upper gate electrode layer formed on the organic ferroelectric thin film layer on the upper side of the channel region;
Memristor device comprising a.

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