KR20130021716A - Resistance random access memory including quantum dots and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A resistance change memory device including a quantum dot and a manufacturing method thereof are provided to improve a data retention property by including the quantum dot on the lower side of an insulation layer formed in a resistance change layer. CONSTITUTION: A bottom electrode(200) is formed on a substrate(100). A resistance change layer(300) is formed on the bottom electrode. An insulation layer(400) is formed on the resistance change layer. A quantum dot(500) is formed in the insulation layer. A top electrode(600) is formed on the quantum dot insulation layer.

Description

Resistance random memory device including quantum dots and a method of manufacturing the same {Resistance random access memory including quantum dots and Method of manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance change memory device including a quantum dot and a method of manufacturing the same, and more particularly, to an asymmetric shape in a specific voltage range including a quantum dot in a lower region in an insulating layer formed on a resistance change layer. The present invention relates to a resistance change memory device including a quantum dot that exhibits resistance switching characteristics of and a method of manufacturing the same.

Since the late 1990s, memory applications have been extended to various electronic devices, not limited to computers, and various types of memories are being developed to achieve high integration and fast response speed.

Among them, the resistance change memory device, which is one of the nonvolatile memory devices, is a device that uses a material capable of switching at least two different resistance states by rapidly changing the resistance according to an applied voltage. Recently, it has been spotlighted as the next generation nonvolatile memory device because of its simplicity, stability, low power consumption, fast response speed and high integration.

In general, the resistive change memory device has a metal / insulator / metal MIM structure (Metal / Insulator / Metal), and uses a 'resistive switching' phenomenon indicating non-volatileness.

That is, the resistance change memory device has two different resistance states under one voltage, and is 'On' using a low resistance state (LRS) and a high state (HRS). Alternatively, it switches to 'Off', and it operates on the principle of storing 2 bits of information. In addition, once the state changes, it has a nonvolatile characteristic that the state is continuously maintained even when no external power is supplied until the next switching occurs.

According to the characteristics of the 'on' or 'off' switching operation, a unipolar that can switch both resistance states at one polarity and a bipolar that can switch both resistance states by changing the polarity of the voltage It can be classified as a resistance change memory device.

Meanwhile, a resistance change memory device having a complementary resistance switching characteristic different from the general resistance switching characteristic has been disclosed [Nature materials, vol 9, May 2010, p403-406].

The resistance change memory device has a structure in which a resistance change layer made of a metal oxide is interposed between upper and lower metal electrodes, and a metal electrode such as Cu is formed in the middle of the resistance change layer. Blocking or energizing the flow of resistance change results in complementary resistance switching characteristics.

However, since the resistance switching characteristics of the bipolar type change depending on the type of electrode disposed in the middle of the resistance change layer, the resistance change memory device needs to secure an optimized structure of the material of the resistance change layer and the electrode material. There is a problem, and an additional process for forming an electrode in the middle of the resistance change layer is required, resulting in a complicated manufacturing process.

Accordingly, a first object of the present invention is to include a quantum dot in a lower region of an insulating layer formed on a resistive change layer, and thereby exhibit a resistance switching memory device having an asymmetric resistance switching characteristic using a quantum confinement effect and a coulombic shielding effect. To provide.

In addition, a second object of the present invention is to provide a method of manufacturing a resistance change memory device capable of realizing a multi-bit by expressing an asymmetric resistance switching characteristic in a specific voltage range by adjusting the magnitude of the applied voltage.

The present invention for achieving the above first object is a lower electrode, a resistance change layer formed on the lower electrode, an insulating layer formed on the resistance change layer, a quantum dot formed in the insulating layer and an upper electrode formed on the insulating layer It includes, characterized in that the bipolar or asymmetric resistance switching characteristics according to the voltage applied to the upper electrode and the lower electrode.

In addition, the present invention for achieving the above second object is a step of forming a lower electrode on the substrate, forming a resistance change layer on the lower electrode, forming a metal layer on the resistance change layer, the metal layer Forming an insulator precursor layer on the substrate, heat treating the metal layer and the insulator precursor layer to form quantum dots in the insulating layer through a chemical reaction between the metal layer and the insulator precursor layer, and forming an upper electrode on the insulating layer And a resistance switching characteristic of a bipolar type or an asymmetric type according to the voltage applied to the upper electrode and the lower electrode.

The resistance change memory device including a quantum dot according to the present invention has a large on / off resistance ratio and excellent data retention characteristics due to the quantum dots included in the lower region of the insulating layer formed on the resistance change layer.

In addition, in the method of manufacturing a resistance change memory device including a quantum dot according to the present invention, each layer constituting the device may be made of a transparent material to produce a transparent device having excellent transmittance, and the distribution density and size or application of the quantum dots By controlling the magnitude of the voltage, the asymmetric resistance switching characteristics are expressed in a specific voltage range, thereby realizing a multi-bit resistance change memory device.

1 is a cross-sectional view illustrating a resistance change memory device according to an exemplary embodiment of the present invention.
2A to 2J are manufacturing process diagrams of a resistance change memory device according to an exemplary embodiment of the present invention.
3A and 3B are TEM photographs of a resistance change memory device manufactured by an embodiment of the present invention.
4A and 4B are hysteresis graphs showing current-voltage (IV) characteristics according to voltage ranges of a resistance change memory device according to an exemplary embodiment of the present invention.
5 is a log plot graph of an asymmetric resistance switching characteristic of a resistance change memory device according to an exemplary embodiment of the present invention.
FIG. 6 is a graph illustrating a change in resistance state with time of a resistance change memory device according to an exemplary embodiment of the present invention. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. In describing the drawings, like reference numerals refer to like elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a resistance change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a resistance change memory device according to an embodiment of the present invention includes an insulating layer 500 including a lower electrode 200, a resistance change layer 300, and a quantum dot 400 on a substrate 100. The upper electrode 600 is sequentially stacked.

The substrate 100 is used to support the device and may be removed as necessary. For example, the substrate 100 may be a transparent inorganic substrate selected from glass, quartz, and Al ₂ O ₃ or polyethylene terephthlate (PET), polyethersulfone (PES), polystyrene (PS), polycarbonate (PC), and polyimide (PI). ), A transparent organic substrate selected from polyethylene naphthalate (PEN) and polyarylate (PAR). In addition, according to the embodiment, a specific film quality may be interposed between the substrate 100 and the lower electrode 200.

The lower electrode 200 formed on the substrate 100 has conductivity and may include a metal-based or transparent conducting oxide. In particular, when the transparent conductive oxide is used, a transparent resistance change memory device having high transmittance may be implemented. The metal may be Pt, Ru, Al, Ir, W, or Cu, wherein the transparent conductive oxide is ITO, doped ZnO (AZO: Al doped, GZO: Ga doped, IZO: In doped, IGZO: In and Ga doped , MZO: Mg doped), MgO doped with Al or Ga, In ₂ O ₃ doped with Sn, SnO ₂ doped with F, or TiO ₂ doped with Nb.

The resistance change layer 300 formed on the lower electrode 200 is a layer in which a conductive filament, which is a path through which current flows, is generated or disappeared as a voltage is applied, and various materials that may exhibit resistance switching characteristics. It can select and form from.

For example, the resistance change layer 300 may include a binary metal oxide series or a perovskite oxide series. The binary metal oxide series may include TiO ₂ , NiO, ZnO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , and perovskite Sky agent film _{SrTiO 3, BiFeO 3, BaTiO 3} , LaMnO 3, may include a SrMnO _3, PrTiO _3. It may also include Pr _{1- x} Ca _x MnO ₃ (0 ≦ _x ≦ 1) and La _{1 - x} Ca _x MnO ₃ (0 ≦ _x ≦ 1).

The insulating layer 500 formed on the resistance change layer 300 serves as a kind of tunneling barrier when a voltage is applied. The insulating layer 500 may include an organic material having insulating properties.

For example, the insulating layer 500 may be a polymer insulator including polyethersulfone (PES), polyethylene terephthlate (PET), polystyrene (PS), polyimide (PI), or poly (methyl methacrylate) (PMMA).

The quantum dot 400 formed in the lower region of the insulating layer 500 traps charge at the quantum level in the deep quantum well and serves to block or energize the movement of charge according to the applied voltage. The quantum dot 400 includes a metal, a metal silicide, a metal oxide, or a metal oxide semiconductor, and may be formed in a single layer or multiple layers.

For example, the metal quantum dot may be at least one selected from Au, Pt, Zn, Al, Co, W, Ni, Ag, Cd, Au, Ti, Sn, Te, Ge, Ga, Se, and Fe. Silicide quantum dots include CoSi, NiSi, WSi, TiSi, V₃Si₂, MnSi. Cu₅Si, CaSi, SrSi, YSi, Mg₂Si, Ge₂Si, Sn₂Si, Pb₂Si, SrSi₂, ThSi₂ And PtSi may be at least one selected from, and the metal oxide or metal oxide semiconductor quantum dot is In₂O₃, CuO, Cu₂O₃, PbO, Bi₁₂SiO₂₀, ZnO₂, SnO₂, GaO, MgO, GeO, V₂O₅, BaO, SrO, Bi₁₂GeO₂₀, Bi₁₂SiO₂₀, Cd₂SnO₄, CdSnO₃, GaO and Li₃CuO₃ At least one selected from among.

The upper electrode 600 formed on the insulating layer 500 has the same conductivity as the lower electrode 200 described above, and may be selected from a metal series including Pt, Ru, Al, Ir, W, or Cu. have.

2A to 2J are manufacturing process diagrams of a resistance change memory device according to an exemplary embodiment of the present invention.

2A and 2B, the lower electrode 200 is formed on the substrate 100. It may be formed through thermo-phase deposition, electron beam deposition, RF sputtering or magnetron sputtering.

The substrate 100 may be an inorganic substrate having transparent and solid characteristics, and may be an organic substrate having transparent and flexible characteristics. In addition, the lower electrode 200 formed on the substrate 100 may include a conductive metal or a transparent conductive oxide. The lower electrode 200 may be spaced apart at regular intervals to have a cross-point shape. At this time, the width of the electrode is preferably selected within the range of 1nm to 500μm in order to facilitate the flow of current and improve the degree of integration of the device. In addition, the separation distance is preferably formed at a minimum interval without interference of the electric and magnetic fields in accordance with the flow of current in order to minimize the dispersion of the threshold voltage by the magnetic field between the adjacent elements.

2C and 2D, the resistance change layer 300 is formed on the lower electrode 200. The resistance variable layer 300 may be formed by a physical vapor deposition (PVD) method such as a sputtering method, a pulsed laser deposition method (PLD), a thermal evaporation method, an electron beam evaporation method, or a chemical vapor deposition method (CVD), chemical vapor deposition (CVD), or the like. In this case, the resistive change layer 300 preferably has a thickness of 1 nm to 500 nm to facilitate the device fabrication process, and lithography and etching to form a cross-point type memory device as shown in FIG. 2D. Through the process may be formed in the form of a column spaced apart a certain distance. The resistance change layer 300 may include a binary metal oxide series or a perovskite oxide series.

Referring to FIG. 2E, a metal layer 400a is formed on the resistance change layer 300 to form a quantum dot. The metal layer 400a may be formed using a physical vapor deposition method or a chemical vapor deposition method. The metal layer 400a is preferably formed to a thickness of 1nm to 5nm. At this time, the thinner the thickness of the metal layer 400a, the smaller the size of the quantum dot 400, and the thicker the thickness of the metal layer 400a, the larger the size of the quantum dot, the thickness of the metal layer 400a in a subsequent process When the metal layer 400a is changed to form a quantum dot, the metal layer 400a is preferably formed to a thickness capable of controlling the size of the quantum dot.

The metal layer 400a may be formed of Au, Pt, Zn, Al, Co, W, Ni, Ag, Cd, Au, Ti, Sn, Te, or Ge, which may react with the insulator precursor layer 500a to be described later. At least one of Ga, Se, Fe, V, Mn, Cu, Ca, Sr, Y, Mg, Pb, Ba, and Li. In addition, in order to form a cross-point type memory device, the metal layer 400a may be formed on the resistance change layer 300 formed in a pillar shape spaced at a predetermined distance.

Referring to FIG. 2F, an insulator precursor layer 500a is formed on the metal layer 400a to form quantum dots. The insulator precursor layer 500a may be formed by spin coating, and the thickness of the insulator precursor layer 500a may be 10 nm to 50 nm. If the thickness of the insulator precursor layer 500a is 10 nm or less, a direct tunneling phenomenon occurs and electrons confined to the quantum dots are more likely to leak and become back tunneled, resulting in an asymmetrical resistance due to the coulomb shielding effect. Switching characteristics cannot be expected. In addition, when the thickness of the insulator precursor layer 500a is 50 nm or more, electrons are not tunneled even by FN tunneling, so a high electric field must be applied to limit charges to quantum dots. The 500 is destroyed and loses its function as a resistance change memory element. Therefore, the thickness may be controlled by adjusting the wt% ratio of the insulator precursor to the solvent. The insulator precursor layer 500a may be a polyimide precursor layer.

The polyimide precursor layer is BPDA-PDA (poly (p-phenylene biphenylene carboximide)), PMDA-PDA (poly (p-phenylene pyromellitimide)), ODPA-PDA (poly (p-phenylene 3,3 ', 4,4 '-oxydiphthalimide)), 6FDA-PDA (poly (p-phenylene 4,4'-hexafluoro isopropylidene diphthalimide)), BTDA-ODA (3,3', 4,4'-Benzophenonetetracarboxylic dianhydride-4,4'-oxydianiline) , DMAc (Dimethylacetamide), BDSDA-ODA (4,4'-bis (3,4-dicarboxyphenoxy) diphenylsulfide-oxydianhydride), DSDA (3,3 ', 4,4'-diphenylsulfone tetracarboxylic acid dianhydride), BPDA-Bz ( poly (4,4'-biphenylene biphenyltetracarboximide), trimethylellitic anhydride-p-phenylene diamine (TMA-PPD) or ODA-PI (4,4'-oxydianiline-polyimide).

Referring to FIG. 2G, when the substrate 100 on which the insulator precursor layer 500a is formed is heat-treated, the metal layer 400a reacts with the insulator precursor layer 500a to form a quantum dot 400 and the insulator precursor layer. 500a reacts with the metal layer 400a to form an insulating layer 500. The heat treatment process may be performed in two steps, a first heat treatment and a second heat treatment.

The first heat treatment may be a process of removing a solvent in the insulator precursor layer 500a. The first heat treatment may be performed for 10 to 60 minutes at a temperature of 125 ℃ to 135 ℃.

In addition, the second heat treatment may be a curing process for forming a quantum dot by reacting the insulator precursor layer 500a from which the solvent is removed through the first heat treatment with the metal layer 400a. The second heat treatment temperature and time is preferably selected in a range sufficient to completely cure the surface of the insulating layer 500 to be chemically stable. Therefore, the second heat treatment may be performed for 30 to 120 minutes at a temperature of 300 ℃ to 500 ℃. Through the curing process, the quantum dot 400 and the insulating layer 500 are formed in the lower region of the insulating layer 500 to contact the upper portion of the resistance change layer 300.

2H and 2I, the upper electrode 600 is formed on the insulating layer 500. The upper electrode 600 may be formed of a conductive material by thermo-phase deposition, electron beam deposition, RF sputtering or magnetron sputtering. In this case, the upper electrode 600 may be formed to vertically cross the lower electrode 200 described above in order to manufacture a cross-point type memory device.

Referring to FIG. 2J, the inner space of the device is filled with the passivation layer 700 to support and protect the device and maintain structural stability of the device. The passivation layer 700 may be a polymer insulator including PI (polyimide) or PMMA (poly (methyl methacrylate)).

Hereinafter, preferred examples are provided to aid the understanding of the present invention. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited to the following experimental examples.

Example

An ITO transparent electrode was formed on the glass substrate. Subsequently, a 160 nm thick ZnO layer was deposited on the ITO transparent electrode using an ultra-high vacuum sputtering method. And a Sn metal layer was formed on the ZnO layer to a thickness of 5nm. Subsequently, the polyimide precursor layer was spin-coated to a thickness of 50 nm with a mixed solution of NMP (N-Methyl pyrrolidone), which is a non-volatile solvent, in a ratio of 1: 3 wt%, on the Sn metal layer, BPDA-PDA, which is a polyimide precursor. Formed. Then, the solvent is removed by soft baking at 125 ° C. for 30 minutes on a hot plate and cured at 400 ° C. for 1 hour in a nitrogen atmosphere to form the Sn metal layer as a quantum dot containing SnO ₂ . The polyimide precursor layer was formed of a polyimide (PI) layer. Subsequently, an Al electrode was formed on the polyimide layer.

3A and 3B are TEM photographs of a resistance change memory device manufactured by an embodiment of the present invention.

Referring to FIGS. 3A and 3B, the resistance change memory device manufactured by an embodiment of the present invention may include a lower electrode, ITO, a resistance change layer, ZnO, a quantum dot, SnO ₂ nanoparticles, and an insulating layer. It can be seen that Al, which is the mid layer and the upper electrode, is sequentially formed. Furthermore, SnO ₂ nanoparticles are located in the lower region of the polyimide layer, which is formed to contact the upper portion of the ZnO layer, it can be seen that the SnO ₂ nanoparticles are interposed between the ZnO layer and the polyimide layer.

In addition, it can be seen that the crystal lattice of the SnO ₂ nanoparticles shows that the interplanar distance of the crystal lattice is 3.345 Å and has a tetragonal structure in the (110) plane direction.

4A and 4B are hysteresis graphs showing current-voltage (I-V) characteristics according to voltage ranges of a resistance change memory device according to an exemplary embodiment of the present invention.

Referring to Figure 4a, the current was measured while changing the applied voltage in the range of -4V to 4V. At this time, the threshold voltage and the current value are threshold voltage 1.3 V at V _th1 , threshold voltage at 1.1x10 ^-5 A and V _th2 , respectively. 3.3 V at current 2.8x10 ^-5 A, V _th3 Threshold voltage -2.2 V, current 3.8x10 ^-5 A), threshold voltage at V _th4 We can see that it has -4 V, current 9.0x10 ^-5 A. When the voltage is applied from -4V to 4V, the device maintains a low resistance state (LRS) as in path 1, but changes from a threshold voltage of -2.2V to a high resistance state (HRS). 2) the state is maintained (path 3), and when the voltage is increased to 1.3V or more, the state is changed back to the low resistance state (path 4) to maintain the state (path 5), which is the Coulomb shielding effect of the quantum dot. This is because the transfer of charge is blocked. The device then transitions back to a high resistance state (path 7) at a threshold voltage of 3.3 V, and continues to remain high while the voltage decreases from path 8 to path 9, which insulates the flow of electrons. In addition, it is understood that a conductive filament capable of transferring charge is not formed inside the resistance change layer.

That is, when a voltage of 3V or less is applied, no resistance change is observed, which is due to the limited movement of charges by the insulating layer under the above voltage, and that the conductive filament by oxygen ions is not formed in the resistance change layer. do.

However, when a voltage of 4V or more is applied, electrons tunneled in the insulating layer start to be confined to the quantum dots, thereby forming a conductive filament through which current can flow in the resistance change layer. At this time, the transfer of charge is blocked by the quantum confinement effect and the coulomb shielding effect in which electrons are confined to the quantum well structure formed by the quantum dot.

That is, when the charge tunneled in the quantum dot is trapped in the quantum well with respect to the quantum dot, the charge transfer is stopped by the Coulomb shielding effect, the conductive filament by the movement of oxygen ions and oxygen vacancies in the resistance change layer Is formed so that the charge passes through the insulating layer, the quantum dot, and the resistance change layer so that the resistance decreases and the current increases. This results in an asymmetrical resistive switching characteristic.

Referring to Figure 4b, the current was measured while changing the applied voltage in the range of -5V to 5V. In this case, the device maintains a low resistance state (LRS) like path 1, but changes from a threshold voltage of -2.2V to a high resistance state (HRS) (path 2), and the current Increase along path 3 by increasing. Subsequently, when the voltage increases above the threshold voltage of 3.3V, the voltage is changed to the low resistance state again (path 4), and the current decreases or increases as the voltage decreases or increases (paths 5 and 6).

In this case, when the applied voltage is changed from -5V to 5V, the device exhibits bipolar resistance switching characteristics, which is because the coulomb shielding effect of the charges constrained to the quantum dots decreases as the voltage increases. do.

5 is a log plot graph of an asymmetric resistance switching characteristic of a resistance change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the current flow through the linear slope change of the Log (I) -Log (V) characteristic curve can be confirmed using a log plot. The resistance change memory device according to the exemplary embodiment of the present invention may have a slope of 1.3 in the case of a low resistance state (LRS) with respect to an applied electric field, and a high resistance state (HRS) In this case we can see the slopes of 1.7 and 2.1.

The reason why the slope increases as described above is that the conduction mechanism is different for each region. For a slope of 2.1 in the high resistance state (HRS), the current density is proportional to the square of the voltage (V ² ). As seen It can be seen that the current follows a space-charge limited current (SCLC) mechanism, which is limited by voltage and space charge, with a slope of 1.7 and a low resistance state in the high resistance state (HRS). The slope of 1.3 at (LRS) shows that the current density is proportional to the voltage (V), which follows the ohmic conduction mechanism.

FIG. 6 is a graph illustrating a change in resistance state with time of a resistance change memory device according to an exemplary embodiment of the present invention. FIG. Pulses were applied at 1V to induce asymmetrical switching.

Referring to FIG. 6, the difference between the high resistance state HRS and the low resistance state LRS is about 4.4 × 10 ⁴ , and the difference is maintained for 10 ³ seconds or more. Through this, it can be seen that the resistance change memory device according to the exemplary embodiment has excellent data retention characteristics.

100 substrate 200 lower electrode
300: resistance change layer 400: insulating layer
500: quantum dot 600: upper electrode
700: shield

Claims (12)

Lower electrode;
A resistance change layer formed on the lower electrode;
An insulation layer formed on the resistance change layer;
A quantum dot formed in the insulating layer; And
An upper electrode formed on the quantum dot insulating layer,
And a resistance change memory device having bipolar or asymmetric resistance switching characteristics depending on voltages applied to the upper and lower electrodes. The method of claim 1,
The resistance change memory device, characterized in that the asymmetrical resistance switching characteristics in the range of -4V to 4V applied to the upper electrode and the lower electrode. The method of claim 1,
The resistance change layer is a resistance change memory device, characterized in that it comprises a binary metal oxide or perovskite oxide. The method of claim 1,
The insulating layer is a resistance change memory device, characterized in that it comprises a polymer insulator. The method of claim 1,
The quantum dot is a resistance change memory device, characterized in that any one selected from metal, metal silicide and metal oxide. Forming a lower electrode on the substrate;
Forming a resistance change layer on the lower electrode;
Forming a metal layer on the resistance change layer;
Forming an insulator precursor layer on the metal layer;
Heat treating the metal layer and the insulator precursor layer to form quantum dots in the insulating layer through a chemical reaction between the metal layer and the insulator precursor layer; And
Forming an upper electrode on the insulating layer;
And a bipolar or asymmetrical resistance switching characteristic depending on the voltage applied to the upper electrode and the lower electrode. The method according to claim 6,
The voltage applied to the upper electrode and the lower electrode is a manufacturing method of a resistance change memory device, characterized in that the asymmetrical resistance switching characteristics in the range of -4V to 4V. The method according to claim 6,
The quantum dot is a method of manufacturing a resistance change memory device, characterized in that formed in a single layer or multiple layers. The method according to claim 6,
The heat treatment is performed for 30 minutes to 120 minutes at a temperature of 300 ℃ to 500 ℃ to form an insulating layer, the surface is completely cured to form a resistance change memory device. The method according to claim 6,
After the forming of the upper electrode on the insulating layer, forming a protective film filling the internal space of the device further comprising the step of manufacturing a resistance change memory device. Providing a resistance change memory device in which a lower electrode, a resistance change layer, an insulating layer including a quantum dot, and an upper electrode are sequentially stacked;
Programming the resistance change memory device to repeat a low resistance state and a high resistance state by applying a voltage to the resistance change memory device in order to sequentially increase from a negative voltage to a positive voltage; And
Programming the resistance change memory device to a high resistance state by applying a voltage to the resistance change memory device in order to sequentially decrease from a positive voltage to a negative voltage. The method of claim 11,
The applied voltage is a method of operating a resistance change memory device, characterized in that in the range of -4V to 4V.

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