KR101537433B1 - Memristor Device including Resistance random access memory and Method of manufacturing the same - Google Patents

Abstract

Memristor elements and a method for manufacturing the same are disclosed. The MEMS device according to the present invention may include two or more resistance change memories and schottky diodes having various resistance switching characteristics to implement characteristics of resistors, memories, and diodes as required in one cell. The method of manufacturing a MEMS device according to the present invention uses a resistance change memory formed through a spontaneous oxidation reaction occurring at an interface between an upper electrode and an insulating layer, By forming the key diodes, a memristor device including a plurality of resistance change memories and diodes in one cell can be manufactured easily and easily.

Description

[0001] MEMBRSTER DEVICE AND METHOD OF MANUFACTURING THE SAME [0002]

The present invention relates to a memristor device and a method of manufacturing the same, and more particularly, to a memristor device including two or more resistance change memories and schottky diodes having various resistance switching characteristics and a method of manufacturing the same.

Memristor is a nano-scale passive device that connects a charge and a magnetic flux. The memristor memorizes the amount of charge and has a characteristic in which the resistance changes according to the stored amount of charge.

Memistors, together with resistors, capacitors and inductors, are one of the basic components of electrical circuits. The memristor is generally similar to the resistor in that it plays various roles that the register plays, but it can change the resistance according to the direction and magnitude of the applied voltage differently from the resistor, There is an ability to. Therefore, the memristor is a new concept device that can construct a new logic circuit such as a terabit memory, a defect recognition device by a neural network circuit configuration, and belongs to the next generation memory related field based on nanotechnology.

On the other hand, since individual memristors can serve as multifunctional transistors, they can replace 7 to 12 transistors and can greatly improve device functions such as energy consumption and boot time. There is an advantage. In addition, the transistor always needs power, so the power loss through leakage current is large, while the memristor has the advantage that memory can be maintained without power.

The conventional memristor is composed of a titanium dioxide double layer which is a pigment of white paint, and can be added to a commonly used silicon semiconductor chip to manufacture an improved device. The memristor arrangement is formed at a crossing point of a cross shape of 100 x 100 conductors. In other words, at each intersection between the two conductors, titanium dioxide is formed in a sandwich structure, which acts as a memorizer. In addition, a series of copper connectors are responsible for connecting the internal devices of the chip to the memristor.

However, when 10,000 patterns of the memristor having the above structure are formed on a conventional complementary metal oxide semiconductor (CMOS) chip, the surface of the CMOS chip is very irregular, There has been a problem in that technical difficulties are involved in complicated physicochemical polishing for planarization.

On the other hand, studies on the characteristics of memristor using nanoparticles showing reversible switching effect in a specific current and temperature range were carried out. Korean Patent Laid-Open No. 10-2010-0061405 discloses that even when a very small amount of current is applied inside a chemically synthesized nanoparticle assembly, a very large resistance change is realized at room temperature, Hysteresis was observed in which the resistance value was changed. This showed the possibility of simply developing the memristor by making the nanoparticles into a pellet (pellet). However, since the memristor using nanoparticles is difficult to control the size and surface characteristics of nanoparticles, it is still necessary to develop a technology having high performance.

In addition, a technique for manufacturing a thin film memory device using a resistive random access memory (RRAM), which is a next generation non-volatile memory, has been disclosed [Nature materials vol 10, August 2011 p625-630]. However, this lacks the differences that distinguish it from the function of the resistance change memory itself, posing a problem with the inherent function of the memristor.

SUMMARY OF THE INVENTION Accordingly, it is a first object of the present invention to provide a memristor device including two or more resistance change memories and schottky diodes having various resistance switching characteristics.

A second object of the present invention is to provide a resistance change memory formed by a spontaneous oxidation reaction occurring at an interface between an upper electrode and an insulating layer, a memory including a Schottky diode formed by disposing a metal layer on a part of the resistance- And to provide a method of manufacturing a raster element.

According to an aspect of the present invention, there is provided a semiconductor device including: a substrate; a lower electrode formed on the substrate; a resistance-variable semiconductor layer formed on the lower electrode and having a resistance change memory region and a diode region; An upper electrode formed on the insulating layer and reacting with the insulating layer to form a metal oxide layer, and an upper electrode formed on the diode region on the resistance-variable semiconductor layer, And a metal electrode formed on the substrate.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: forming a lower electrode on a substrate; forming a resistance-variable semiconductor layer having a resistance change memory region and a diode region on the lower electrode; Forming an insulating layer including quantum dots in a resistance change memory region on a semiconductor layer, forming an upper electrode on the insulating layer, and arranging a metal electrode in a diode region on the resistance variable semiconductor layer to form a Schottky junction The method comprising the steps of:

The MEMS device according to the present invention can simultaneously realize characteristics of a resistor, a memory and a diode in one cell by using two or more resistance change memories and schottky diodes having various resistance switching characteristics.

A method of manufacturing a MEMS device according to the present invention includes forming a resistance change memory element through a spontaneous oxidation reaction occurring between an insulating layer including a polymer insulator and an upper electrode including a metal, It is possible to manufacture a MEMSistor device in which a resistance change memory and a diode are integrated simply and easily by forming a diode by disposing a metal layer in a part of a region of the resistance-variable semiconductor layer.

1 is a perspective view of a MEMSistor device according to an embodiment of the present invention.
2A to 2G are process diagrams illustrating a method of manufacturing a MEMSistor device according to an embodiment of the present invention.
3 is a circuit diagram for analyzing an energy band diagram and device characteristics of a memristor device according to an embodiment of the present invention.
4 is a hysteresis graph showing current-voltage (IV) characteristics of a first resistance-change memory constituting a MEMS device according to an embodiment of the present invention.
5 is a hysteresis graph showing a current-voltage (IV) characteristic of a second resistance-change memory constituting a MEMSistor according to an embodiment of the present invention.
6 is a perspective view illustrating a MEMSistor device according to another embodiment of the present invention.
7 is a circuit diagram for analyzing an energy band diagram and device characteristics of a MEMSistor device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view of a MEMSistor device according to an embodiment of the present invention.

1, a MEMS device according to an embodiment of the present invention includes a substrate 100, a lower electrode 200, a resistance change semiconductor layer 300 having a resistance change memory region A and a diode region B, An insulating layer 500 including a quantum dot 400 and an upper electrode 600 are sequentially stacked on the resistance change memory region A and a metal electrode 700) are formed and a resistance change memory and a Schottky diode are integrated.

The substrate 100 is used to support the device. For example, the substrate 100 may be an inorganic substrate selected from glass, quartz, and Al ₂ O ₃ having a transparent and solid nature, and may be made of PET (polyethylene), which is transparent and flexible terephthlate, polyethersulfone (PES), polystyrene (PS), polycarbonate (PC), polyimide (PI), polyethylene naphthalate (PEN) and polyarylate.

The lower electrode 200 formed on the substrate 100 is used as a lower electrode of the resistance-variable memory device constituting the MEMS device. The lower electrode 200 has conductivity and includes a metal-based or transparent conducting oxide . The transparent conductive oxide may be at least one selected from the group consisting of ITO, doped ZnO (AZO: Al doped, GZO: Ga doped, IZO: In doped, IGZO: In and Ga doped , MZO: Mg doped), Al or Ga is doped MgO, Sn-doped In ₂ O _3, SnO ₂ doped with F Or the Nb-doped TiO ₂ Lt; / RTI >

The resistance variable semiconductor layer 300 formed on the lower electrode 200 has a resistance change memory region A and a diode region B. That is, the resistance-variable semiconductor layer 300 functions as a layer in which a conducting filament, which is a path through which a current flows in a resistance-variable memory device constituting a resistive element, is generated or destroyed, And serves as a semiconductor layer for forming a metal-semiconductor junction in the constituent Schottky diode.

Thus, the resistance-variable semiconductor layer 300 may exhibit resistance-switching characteristics and may be selected from a variety of materials capable of exhibiting the properties of a semiconductor forming a Schottky junction in relation to a metal electrode 700 have.

For example, the resistance-variable semiconductor layer 300 may include a binary metal oxide series or a perovskite oxide series. The binary metal oxide series may include TiO ₂ , NiO, ZnO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ and Nb ₂ O ₅ , The skid film may include SrTiO ₃ , BiFeO ₃ , BaTiO ₃ , LaMnO ₃ , SrMnO ₃ , and PrTiO ₃ . And may include Pr _{1 - x} Ca _x MnO ₃ (0? _X? 1) and La _{1 - x} Ca _x MnO ₃ (0? _X? 1).

The insulating layer 500 formed in the resistance-variable memory region A on the resistance-variable semiconductor layer 300 serves as a kind of tunneling barrier for passing charges when a voltage is applied in the resistance-variable memory element constituting the memristor element .

The insulating layer 500 forms a metal oxide layer (not shown) through a spontaneous oxidation reaction occurring at an interface with the upper electrode 600 formed on the insulating layer 500. The metal oxide layer causes the resistance switching characteristic at the interface between the insulating layer 500 and the upper electrode 600 to function as a resistance change memory.

The insulating layer 500 is preferably cured at a relatively low temperature for a short time so as to have a soft characteristic for an interface reaction with the upper electrode 600, You can cure within 1 hour.

For example, the insulating layer 500 may include an organic material having an insulating property, and may be formed of a material such as polyethersulfone (PES), polyethylene terephthalate (PET), polystyrene (PS), polyimide (PI), or poly (methyl methacrylate) Polymeric insulator.

The quantum dot 400 formed in the lower region of the insulating layer 500 captures a charge at a quantum level in a deep quantum well and functions to block or energize the movement of charges according to the applied voltage. Therefore, the resistance change memory constituting the memristor element exhibits an asymmetrical resistance switching characteristic in a specific voltage region. The quantum dot 400 includes a metal, a metal silicide, a metal oxide, or a metal oxide semiconductor, and may be formed as a single layer or a multilayer.

For example, the metal quantum dots may be at least one selected from Au, Pt, Zn, Al, Co, W, Ni, Ag, Cd, Au, Ti, Sn, Te, Ge, silicide quantum dots CoSi, NiSi, WSi, TiSi, V 3 Si 2, MnSi. Cu ₅ Si, CaSi, SrSi, YSi, Mg ₂ Si, Ge ₂ Si, Sn ₂ Si, Pb ₂ Si, SrSi ₂ , ThSi ₂ And PtSi. The metal oxide or metal oxide semiconductor quantum dots may be at least one selected from the group consisting of In ₂ O ₃ , CuO, Cu ₂ O ₃ , PbO, Bi ₁₂ SiO ₂₀ , ZnO ₂ , SnO ₂ , GaO, MgO, GeO , V ₂ O ₅ , BaO, SrO, Bi ₁₂ GeO ₂₀ , Bi ₁₂ SiO ₂₀ , Cd ₂ SnO ₄ , CdSnO ₃ , GaO and Li ₃ CuO ₃ And the like.

The upper electrode 600 formed on the insulating layer 500 functions as an upper electrode of the resistance change memory constituting the memristor element. In addition, it plays a role of forming a metal oxide layer (not shown) by spontaneous oxidation reaction occurring at the interface with the insulating layer 500 described above. The metal oxide layer causes the resistance switching characteristic at the interface between the insulating layer 500 and the upper electrode 600 to function as a resistance change memory.

The upper electrode 600 preferably includes a metal that reacts with the insulating layer 500 to form an oxide for an interface reaction with the insulating layer 500. For example, the upper electrode 600 may be any metal selected from the group consisting of Al, In, Sn, Zn, Cu, Mn, Ni, Co,

The metal electrode 700 formed in the diode region B on the resistance-variable semiconductor layer 300 may be formed by forming a metal-semiconductor junction in the relationship with the resistance-variable semiconductor layer 300, It is preferable that the function is formed of a large metal. For example, the metal electrode 700 may be any one selected from the group consisting of In, Au, and Pt.

The MEMS device according to an embodiment of the present invention includes a lower electrode 200, a resistance-variable semiconductor layer 300, a quantum dot 400, an insulating layer 500, a metal oxide layer (not shown), and an upper electrode 600 And a second resistance change memory including a metal oxide layer (not shown) / an upper electrode 600 formed at the interface between the insulating layer 500 and the upper electrode 600, (B) having a schottky diode having a semiconductor-metal junction as the metal electrode (700) and the resistance-variable semiconductor region (300) in a region of the resistance-variable semiconductor layer ). ≪ / RTI >

As described above, the MEMS device according to one embodiment of the present invention has a structure in which a first resistance-change memory, a second resistance-change memory, and a Schottky diode are integrated on one substrate, and the Schottky diode The characteristics can be controlled. In addition, since the memristor device has a plurality of terminal terminals, it can be used as a resistor, a memory, or a diode according to various applications by variously contacting the terminals.

2A to 2G are process diagrams illustrating a method of manufacturing a MEMSistor device according to an embodiment of the present invention.

Referring to FIG. 2A, a lower electrode 200 is formed on a substrate 100. This is used as a lower electrode of the resistance change memory and can be formed through thermal vapor deposition, electron beam deposition, RF sputtering, magnetron sputtering, or the like.

The substrate 100 may be an inorganic substrate having a transparent and solid characteristic, and may be an organic substrate having a transparent and flexible characteristic. In addition, the lower electrode 200 formed on the substrate 100 may include a conductive metal or a transparent conductive oxide. The lower electrodes 200 may be spaced apart at regular intervals to have a cross-point shape.

Referring to FIG. 2B, the resistance-variable semiconductor layer 300 is formed on the lower electrode 200. The resistance variable semiconductor layer 300 may be formed by a physical vapor deposition (PVD) method such as a sputtering method, a pulsed laser deposition method (PLD), a thermal evaporation method, an electron beam evaporation method, And may be formed using CVD (Chemical Vapor Deposition) or the like.

In order to facilitate the device manufacturing process, the resistance-variable semiconductor layer 300 preferably has a thickness of 1 nm to 500 nm. In order to form the memory device of the cross-point type, the resistance- Or may be formed in a columnar arrangement. The resistance-variable semiconductor layer 300 may include a binary metal oxide series or a perovskite oxide series.

Referring to FIG. 2C, a metal layer 400a is formed on the resistance-variable semiconductor layer 300 to form quantum dots. In this case, the metal layer 400a may be formed in a part of the resistance-variable semiconductor layer 300 to form a diode, which will be described later. That is, the metal layer 400a is formed such that a part of the resistance variable semiconductor layer 300 is exposed.

The metal layer 400a may be formed using a physical vapor deposition method or a chemical vapor deposition method. The metal layer 400a is preferably formed to a thickness of 1 nm to 5 nm. As the thickness of the metal layer 400a decreases, the size of the quantum dot 400 becomes smaller. When the thickness of the metal layer 400a increases, the size of the quantum dot becomes larger. When the metal layer 400a is changed to form quantum dots, it is preferable that the thickness of the metal layer 400a can be controlled to control the size of the quantum dots.

The metal layer 400a may be formed of Au, Pt, Zn, Al, Co, W, Ni, Ag, Cd, Au, Ti, Sn, Te, and Ge which can react with the insulator precursor layer 500a described later to form quantum dots. , Ga, Se, Fe, V, Mn, Cu, Ca, Sr, Y, Mg, Pb, Ba and Li. In addition, the metal layer 400a may be formed on the resistance-variable semiconductor layer 300, which is formed in a columnar shape and spaced apart by a predetermined distance, to form a memory element of a cross-point type.

Referring to FIG. 2D, an insulator precursor layer 500a is formed on the metal layer 400a to form quantum dots. The insulator precursor layer 500a may be formed by a spin coating method, and is preferably formed to a thickness of 10 nm to 50 nm. At this time, the thickness can be controlled by adjusting the wt% ratio of the insulator precursor to the solvent. The insulator precursor layer 500a may be a polyimide precursor layer.

The polyimide precursor layer may be formed of at least one selected from the group consisting of BPDA-PDA (poly (p-phenylene biphenylene carboximide)), PMDA-PDA (poly (p-phenylene pyromellitimide), ODPA-PDA '-oxydiphthalimide), 6FDA-PDA (poly (p-phenylene 4,4'-hexafluoro isopropylidene diphthalimide)), BTDA-ODA (3,3', 4,4'-Benzophenonetetracarboxylic dianhydride-4,4'-oxydianiline) , DMAc (Dimethylacetamide), BDSDA-ODA (4,4'-bis (3,4-dicarboxyphenoxy) diphenylsulfide-oxydianhydride), DSDA (3,3 ', 4,4'- diphenylsulfone tetracarboxylic acid dianhydride), BPDA-Bz poly (4,4'-biphenylene biphenyltetracarboximide), TMA-PPD (trimellitic anhydride-p-phenylene diamine) or ODA-PI (4,4'-oxydianiline-polyimide).

In this case, when an organic substrate having a weak chemical resistance such as a polyethersulfone (PES) substrate is used, a photoresist material is coated on the substrate to protect the substrate, the surface having the quantum dot is exposed, and the polyimide precursor layer .

2E, when the substrate 100 on which the insulator precursor layer 500a is formed is heat-treated, the metal layer 400a reacts with the insulator precursor layer 500a to form quantum dots 400, (500a) reacts with the metal layer (400a) to form an insulating layer (500). A soft baking process may be performed prior to the heat treatment to remove the solvent in the insulator precursor layer 500a, and the soft bake may be performed at a temperature of 125 ° C to 135 ° C for 10 minutes to 60 minutes .

In addition, the heat treatment may be a curing process for forming the insulating layer 500. At this time, the insulating layer 500 is not sufficiently hardened for the interfacial oxidation reaction with the upper electrode 600 formed on the insulating layer 500, It is preferable that the heat treatment is performed at a temperature of 300 DEG C for 10 minutes to 60 minutes.

However, the process for forming the quantum dots is not limited thereto, and the metal layer 400a may be deposited by thermal evaporation and then exposed to the atmosphere, thereby forming the metal layer 400a using an oxidation reaction with oxygen.

Referring to FIG. 2F, upper electrodes 600a and 600b are formed on the insulating layer 500. FIG. The upper electrodes 600a and 600b may be formed of the same or different materials and may include a metal that reacts with the insulating layer 500 to form an oxide for an interface reaction with the insulating layer 500 . For example, the upper electrodes 600a and 600b may be any one selected from a metal series including Al, In, Sn, Zn, Cu, Mn, Ni, Co,

The upper electrodes 600a and 600b may be formed using thermal vapor deposition, electron beam deposition, RF sputtering, or magnetron sputtering. In this case, the upper electrodes 600a and 600b may be formed so as to be perpendicular to the lower electrode 200 in order to manufacture a cross-point type memory device.

Referring to FIG. 2G, a metal electrode 700 for a diode is formed in the region of the exposed resistance-variable semiconductor layer 300 to fabricate a Schottky diode comprising a metal-semiconductor junction. The metal electrode 700 may be formed by a sputtering or evaporation method and may be formed of a metal having a large work function so as to function as a Schottky diode by forming a metal- . For example, the metal electrode 700 may be any one selected from the group consisting of In, Au, and Pt.

In addition, the inner space of the device can be filled with a protective film (not shown) to support and protect the device and to maintain the structural stability of the device. The protective layer may be a polymer insulator including polyimide (PI) or poly (methyl methacrylate) (PMMA).

Experimental Example

An ITO transparent electrode was formed on the PES substrate. Subsequently, a 160 nm thick ZnO layer was deposited on the ITO transparent electrode by ultra-high vacuum sputtering. At this time, the initial vacuum state was 5 × ^{10 -10} Torr and the deposition vacuum was 2 × 10 ^-3 Torr. The flow rate of the Ar gas was 10 sccm, and the deposition was carried out at 50 W using RF magnetron sputtering. Thereafter, an Sn metal layer was deposited on the ZnO layer to a thickness of 5 nm by evaporation, and exposed to the atmosphere to form SnO ₂ Quantum dots were formed. Then, a polyimide precursor layer was formed by spin-coating a mixed solution of BPDA-PDA, which is a polyimide precursor, and NMP (N-methyl pyrrolidone), which is a nonvolatile solvent, in a ratio of 1: 3 wt% to a thickness of 50 nm. Subsequently, the solvent was removed by soft baking at 125 DEG C for 30 minutes on a hot plate, and curing was performed at 200 DEG C for 30 minutes in a nitrogen atmosphere to form a polyimide precursor layer having a soft polyimide surface (PI) layer. Next, on the polyimide layer, an Al electrode was formed to a thickness of 200 nm by evaporation. Thereafter, an In electrode is disposed on the ZnO layer to form a Schottky diode, thereby completing the MEMSistor device.

3 is a circuit diagram for analyzing an energy band diagram and device characteristics of a memristor device according to an embodiment of the present invention.

1 and 3, a bandgap is formed between a highest occupied molecular orbital (HOMO) and a lowest unoccupied molecular orbital (LUMO) due to the insulating layer 500, and an upper electrode 600 and an insulating layer 500 are formed. A metal oxide layer is formed due to the metal oxidation reaction at the interface of the metal oxide layer.

Circuit 11 represents a second resistance-change memory including a metal oxide layer (not shown) / upper electrode 600 formed at the interface between the insulating layer 500 and the upper electrode 600. The circuit 3 includes a lower electrode A first resistance change memory made up of a resistance variable semiconductor layer 300, a quantum dot 400, an insulating layer 500, a metal oxide layer (not shown), and an upper electrode 600. The first resistance-change memory and the second resistance-change memory are connected in circuit through a Schottky diode, and the Schottky diode can control the characteristics thereof.

4 is a hysteresis graph showing current-voltage (I-V) characteristics of a first resistance-change memory constituting a MEMSistor according to an embodiment of the present invention.

Referring to FIG. 4, in a current-voltage characteristic curve obtained by performing a voltage sweep 20 times in the range of -4 V to 4 V, the lower electrode / resistance variable semiconductor layer / quantum dot / insulating layer / metal oxide layer / upper electrode It can be seen that the first resistance change memory constituted asymmetrically exhibits a bipolar resistance switching characteristic.

It can be seen that the high resistance state (HRS) and the low resistance state (LRS) are 8.0 × 10 ^-5 A and 4.3 × 10 ^-6 A at 1 V, and the threshold voltage and the current at this time and 2.25x10 ^-9 a in each case of 0.7V V _th1, is found to be 3.8x10 ^-8 a at 3 V for V _th2.

Also, the LRS / HRS ratio is 1.8x10 ⁴ at 1V. The reason for the large change in resistance as described above is that the resistance change effect by the quantum confinement effect and the coulomb blockade effect due to the quantum dot formed in the insulating layer, Oxygen Ion migration.

When a voltage is applied from 0V to 4V, the movement of oxygen ions by the oxygen vacancies inside the resistance variable semiconductor layer starts and the charges are confined to the quantum dots. A coulombic shielding effect that no more charge is constrained to the quantum dots by the stored charge with time increases and a high resistance is maintained. When the threshold voltage (V _th2 ) is reached, a current flows through the insulating layer by an applied voltage do. When a voltage of 4 V to 0 V is applied, charges are passed through the insulating layer by FN (Fowler-Nordheim) tunneling. When the voltage reaches 4 V to the threshold voltage (V _th1 ), the charge flow is suppressed by the insulating layer, Asymmetric bipolar resistance switching effect is observed due to the quantum confinement effect by the charge.

5 is a hysteresis graph showing current-voltage (I-V) characteristics of the second resistance-change memory constituting the memristor device according to an embodiment of the present invention.

5, a metal oxide layer (not shown) / upper electrode (not shown) formed at the interface between the insulating layer and the upper electrode in a current-voltage characteristic curve obtained by performing a voltage sweep 20 times in the range of -4V to 4V The second resistance-change memory structure having a bipolar-type resistance switching characteristic can be confirmed. In this case, the maximum and minimum current values are 4 × 10 ^-4 A at ⁴ V and 9.3 × 10 ^-9 A at 0 V, respectively. Also, the on / off ratio of the current in the voltage range of 0 V to 4 V is 2.45.

In the upper electrode / metal oxide layer / insulation layer structure as described above, the resistance switching characteristic is not sufficiently cured, so that spontaneous oxidation occurs at the interface between the soft insulation layer and the metal electrode which is easy to form an oxide, It is said that it is because it was formed.

6 is a perspective view illustrating a MEMSistor device according to another embodiment of the present invention.

6, a MEMS device according to another embodiment of the present invention includes a substrate 100, a lower electrode 200, a resistance change semiconductor layer 300 having a resistance change memory region A and a diode region B The insulating layer 500 including the quantum dots 400 in the resistance change memory region A, the first upper electrode and the second upper electrodes 600a and 600b formed of different materials are stacked in this order, And the metal electrode 700 is formed in the diode region B of the resistance variable semiconductor layer 300 to form one cell.

Therefore, the first resistance change memory, the second resistance change memory, the third resistance change memory, the fourth resistance change memory, and the Schottky diode are integrated in one cell.

The description of the substrate 100, the lower electrode 200, the resistance-variable semiconductor layer 300, the quantum dot 400, and the metal electrode 700 for forming a diode is the same as described above. .

The insulating layer 500 formed in the resistance-variable memory region A on the resistance-variable semiconductor layer 300 serves as a kind of tunneling barrier for passing charges when a voltage is applied in the resistance-variable memory element constituting the memristor element A metal oxide layer (not shown) may be formed through a spontaneous oxidation reaction occurring at an interface with the upper electrode 600 formed on the insulating layer 500.

The insulating layer 500 can be obtained by heat treating the insulator precursor layer 500a, and the hardness of the surface can be changed by adjusting the heat treatment conditions.

For example, the heat treatment conditions can be adjusted to form an insulating layer 500 whose surface is completely cured, and the heat treatment temperature and time at this time are sufficient to completely cure the surface of the insulating layer 500 so as to be chemically stable Is preferably selected from the range. The heat treatment may be performed at a temperature of 300 ° C to 500 ° C for 30 minutes to 120 minutes. In this case, there is an advantage of being chemically stable. At this time, the oxidation reaction does not occur at the interface with the upper electrode 600.

Therefore, in the above case, the MEMS device according to another embodiment of the present invention includes the lower electrode 200, the resistance-variable semiconductor layer 300, the quantum dot 400, the insulating layer 500, and the first upper electrode 600a. A third resistance change memory including a lower electrode 200, a resistance-variable semiconductor layer 300, a quantum dot 400, an insulating layer 500, and a second upper electrode 600b; And a resistance change semiconductor layer 300 in a region of the resistance variable semiconductor layer 300 and a Schottky diode having a semiconductor-metal junction as the metal electrode 700.

On the other hand, it is possible to form the insulating layer 500 in a soft state in which the surface is not sufficiently cured by adjusting the heat treatment conditions. In this case, oxidation at the interface with the upper electrode 600 formed on the insulating layer 500 A reaction occurs to form a metal oxide layer (not shown). The metal oxide layer has the advantage that the resistance switching characteristic occurs at the interface between the insulating layer 500 and the upper electrode 600 and can function as a resistance change memory. The heat treatment may be performed at 100 ° C to 300 ° C for 10 minutes to 60 minutes.

In this case, the MEMS device according to another embodiment of the present invention includes a lower electrode 200, a resistance-variable semiconductor layer 300, a quantum dot 400, an insulating layer 500, a metal oxide layer (not shown) A first resistance change memory composed of a first upper electrode 600a, a metal oxide layer (not shown) / a first upper electrode 600a formed at the interface between the insulating layer 500 and the first upper electrode 600a, The resistance variable semiconductor layer 300 / the quantum dot 400 / the insulating layer 500 / the metal oxide layer (not shown) / the second upper electrode 600b, (Not shown) formed at an interface between the insulating layer 500 and the second upper electrode 600b, and a second upper electrode 600b, And a resistance-variable semiconductor layer 300 in a region of the resistance-variable semiconductor layer 300, and a Schottky diode having a semiconductor- It consists of a single cell containing the odd.

For example, the insulating layer 500 may include an organic material having an insulating property, and may be formed of a material such as polyethersulfone (PES), polyethylene terephthalate (PET), polystyrene (PS), polyimide (PI), or poly (methyl methacrylate) Polymeric insulator.

The first upper electrode 600a and the second upper electrode 600b formed on the insulating layer 500 are formed of different materials and function as upper electrodes of the resistance change memory constituting the memristor element. When the insulating layer 500 is formed to have a soft characteristic, a metal oxide layer (not shown) is formed through a spontaneous oxidation reaction occurring at the interface with the insulating layer 500 .

When the upper electrode is formed of different materials as described above, the current-voltage characteristic changes due to a difference in oxidation characteristic of each material or a difference in work function due to bonding with the insulator layer 500. As a result, the LRS / HRS ratios are different from each other or the difference between the maximum value and the minimum value of the voltage is displayed. Therefore, the multi-functional resistance change memory can be implemented to variously control the characteristics of the memristor There is an advantage.

The first upper electrode 600a and the second upper electrode 600b may include a metal having good conductivity and react with the insulating layer 500 for an interface reaction with the insulating layer 500, It is preferable to include a metal which is easy to form. For example, the first upper electrode 600a and the second upper electrode 600b may be selected from metal series including Al, In, Sn, Zn, Cu, Mn, Ni, Co,

As described above, in the MEMS device according to another embodiment of the present invention, when the heat treatment conditions of the insulating layer are controlled to form a metal oxide layer, a first resistance change memory, a third resistance change memory And a Schottky diode are integrated. In the case of forming the metal oxide layer, the first resistance change memory, the second resistance change memory, the third resistance change memory, the fourth resistance change memory and the Schottky diode are integrated on one substrate.

The Schottky diode formed in a region of the resistance-variable semiconductor layer can control the characteristics of the MEMS device including the plurality of resistance change memories. In addition, since the memristor device has a plurality of terminal terminals, it can be used as a resistor, a memory, or a diode according to various applications by variously contacting the terminals.

7 is a circuit diagram for analyzing an energy band diagram and device characteristics of a MEMSistor device according to another embodiment of the present invention.

6 and 7, a bandgap is formed between the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) due to the insulating layer 500, the upper electrode 600 and the insulating layer 500 are formed, A metal oxide layer is formed due to the metal oxidation reaction at the interface of the metal oxide layer.

Circuit 11 represents a fourth resistance-change memory including a metal oxide layer (not shown) / second upper electrode 600b formed at the interface between the insulating layer 500 and the second upper electrode 600b, and the circuit 12 A second resistance change memory including a metal oxide layer (not shown) / a first upper electrode 600a formed at an interface between the insulating layer 500 and the first upper electrode 600a. The circuit 3 includes a lower electrode 200, a resistance-variable semiconductor layer 300, a quantum dot 400, an insulating layer 500, a metal oxide layer (not shown), a first or second upper electrode 600a and 600b, And a third resistance change memory.

The plurality of resistance change memories are connected in a circuit through a Schottky diode, and the characteristics can be controlled by the Schottky diode. Therefore, there is an advantage that it can be used as a resistor, a memory or a diode for each application.

100: substrate 200: lower electrode
300: resistance variable semiconductor layer 400: quantum dot
500: insulating layer 600: upper electrode
700: metal electrode

Claims (11)

Board;
A lower electrode formed on the substrate;
A resistance change semiconductor layer formed on the lower electrode and having a resistance change memory region and a diode region;
An insulating layer formed in the resistance change memory region on the resistance variable semiconductor layer;
A quantum dot formed in the insulating layer;
An upper electrode formed on the insulating layer and reacting with the insulating layer to form a metal oxide layer; And
And a metal electrode formed in the diode region on the resistance variable semiconductor layer,
Wherein the insulating layer comprises a polymeric insulator and has soft properties that are not fully cured to form a metal oxide layer at the interface with the upper electrode. The method according to claim 1,
Wherein the upper electrode is formed of the same or different material. 3. The method of claim 2,
Wherein the upper electrode is any one selected from the group consisting of Al, In, Sn, Zn, Cu, Mn, Ni, Co, Fe and V. delete The method according to claim 1,
Wherein the resistance variable semiconductor layer comprises a binary metal oxide or a perovskite oxide. The method according to claim 1,
Wherein the metal electrode is selected from the group consisting of In, Au and Pt. Forming a lower electrode on the substrate;
Forming a resistance-variable semiconductor layer having a resistance-change memory region and a diode region on the lower electrode;
Forming an insulating layer including quantum dots in the resistance change memory region on the resistance variable semiconductor layer;
Forming an upper electrode on the insulating layer; And
And forming a Schottky junction by disposing a metal electrode in a diode region on the resistance variable semiconductor layer,
Wherein the step of forming the insulating layer is performed by heat-treating the insulator precursor layer,
Wherein the heat treatment is performed at a temperature of 100 ° C to 300 ° C for 10 minutes to 60 minutes to form an insulating layer having a soft characteristic that the surface is not completely cured. 8. The method of claim 7,
Further comprising the step of forming a protective film filling the inner space of the device after the step of forming the metal electrode in the diode region on the resistance variable semiconductor layer. 8. The method of claim 7,
Wherein the upper electrode is formed of the same or different material. delete delete

Images