KR20130021864A - Memristor device including resistance random access memory and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A memristor device and a manufacturing method thereof are provided to simultaneously implement a resistor property, a memory property, and a diode property in one cell by using a schottky diode and a resistance change memory with various resistance switching properties. CONSTITUTION: A bottom electrode(200) is formed on a substrate. A resistance change semiconductor layer(300) has a resistance change memory region and a diode region. An insulation layer(500) is formed in the resistance change memory region of the resistance change semiconductor layer. A quantum dot(400) is formed in the insulation layer. A top electrode forms a metal oxide layer by reacting on the insulation layer. A metal electrode(700) is formed in the diode region of the resistance change semiconductor layer. [Reference numerals] (Circuit11) Second ReRAM; (Circuit12) Fourth ReRAM; (Circuit3) First or third ReRAM

Description

Memristor device and method for manufacturing same {Memristor Device including Resistance random access memory and Method of manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memristor device and a method of manufacturing the same, and more particularly, to a memristor device composed of two or more resistance change memories and a schottky diode having various resistance switching characteristics, and a method of manufacturing the same.

Memristors are nanoscale passive devices that connect charges and magnetic fluxes. They memorize the amount of charge and change the resistance according to the stored amount of charge.

Memristors, together with resistors, capacitors and inductors, are one of the basic components of an electrical circuit. The memristor is generally similar to the resistor in that it plays various roles in which the resistor plays a role. However, unlike the resistor, the memristor can change the resistance according to the direction and magnitude of the applied voltage. Have the ability to Therefore, memristor is a new concept device that enables new logic circuit configuration such as terabit memory and defect recognition device by neural network configuration, and belongs to the next generation memory related field based on nano technology.

On the other hand, individual memristors can act as multi-function transistors, replacing seven to twelve transistors, which can dramatically improve energy savings and boot time. There is an advantage. In addition, since transistors always require power, power loss through leakage current is large, while memristors have an advantage of maintaining memory without power.

The conventional memristor consists of a double layer of titanium dioxide, which is a pigment of white paint, and can be added to a conventional silicon semiconductor chip to manufacture an improved device. The memristor array is formed at the cross point of the cross shape of the 100 × 100 conductors. That is, titanium dioxide is formed in a sandwich structure at each intersection point between the two conductors, which serves as a memristor. In addition, the chip's internals are connected to memristors by a series of copper leads.

However, in the case where 10,000 patterns of memristors having the above structure are formed on a conventional complementary metal oxide semiconductor (CMOS) chip, the surface of the CMOS chip is very irregular and thus a ridge having a height of 0.01 mm is formed. There has been a problem with technical difficulties that require complex physicochemical polishing to planarize.

On the other hand, the study of the characteristics of the memristor using nanoparticles exhibiting a reversible switching effect in a specific current and temperature range. In Korean Patent Laid-Open No. 10-2010-0061405, even when a very small amount of current is applied to a chemically synthesized nanoparticle assembly, a very large resistance change is realized at room temperature, thereby changing the switching effect of the resistance value and the current direction. As a result, hysteresis, which shows a change in resistance value, was shown, which visualized the possibility of simply developing a memristor by preparing nanoparticles in pellet form. However, the memristor using the nanoparticles is difficult to control the size and characteristics of the surface of the nanoparticles, so there is still a need for the development of a technology having high performance.

In addition, a technology for manufacturing a memristor thin film device using a resistance random access memory (RRAM), which is a next-generation nonvolatile memory, has been disclosed [Nature materials vol 10, August 2011 p625-630]. However, this lacks a distinguishable difference from that of the resistive change memory itself, which raises the problem of memristor-specific functions.

Accordingly, a first object of the present invention is to provide a memristor device including two or more resistance change memories and a schottky diode having various resistance switching characteristics.

In addition, a second object of the present invention is a Mem including a Schottky diode formed by placing a metal layer in a portion of the resistive change memory and the resistive change semiconductor layer formed through the spontaneous oxidation reaction occurring at the interface between the upper electrode and the insulating layer. The present invention provides a method for manufacturing a Lister element.

The present invention for achieving the above first object is a resistance change semiconductor layer formed on a substrate, a lower electrode formed on the substrate, the lower electrode, having a resistance change memory region and a diode region, the resistance change semiconductor layer An insulating layer formed in the resistance change memory region of the phase, a quantum dot formed in the insulating layer, an upper electrode formed on the insulating layer and reacting with the insulating layer to form a metal oxide layer, and a diode region on the resistance changing semiconductor layer It characterized in that it comprises a metal electrode formed on.

In addition, the present invention for achieving the above second object is to form a lower electrode on a substrate, forming a resistance change semiconductor layer having a resistance change memory region and a diode region on the lower electrode, the resistance change Forming a schottky junction by forming an insulating layer including quantum dots in a resistive change memory region on the semiconductor layer, forming an upper electrode on the insulating layer, and disposing a metal electrode in a diode region on the resistive change semiconductor layer Characterized in that it comprises a step.

The memristor device according to the present invention has the effect of simultaneously implementing the characteristics of a resistor, a memory, and a diode in one cell by using two or more resistance change memories having various resistance switching characteristics and a schottky diode.

In addition, the method of manufacturing a memristor device according to the present invention forms a resistance change memory device through a spontaneous oxidation reaction generated between an insulating layer including a polymer insulator and an upper electrode including a metal, thereby forming a metal oxide semiconductor. By forming a diode by disposing a metal layer in a portion of the resistive change semiconductor layer, it is possible to easily and easily manufacture a memristor device in which the resistive change memory and the diode are integrated.

1 is a perspective view showing a memristor device according to an embodiment of the present invention.
2A to 2G are process diagrams illustrating a method of manufacturing a memristor device according to an embodiment of the present invention.
3 is a circuit diagram for energy band diagram and device characteristic analysis of a memristor device according to an embodiment of the present invention.
FIG. 4 is a hysteresis graph showing current-voltage (IV) characteristics of a first resistance change memory constituting a memristor device according to an embodiment of the present invention.
FIG. 5 is a hysteresis graph showing current-voltage (IV) characteristics of a second resistance change memory constituting a memristor device according to an embodiment of the present invention.
6 is a perspective view showing a memristor device according to another embodiment of the present invention.
7 is a circuit diagram for energy band diagram and device characteristic analysis of a memristor device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. In describing the drawings, like reference numerals refer to like elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a perspective view showing a memristor device according to an embodiment of the present invention.

Referring to FIG. 1, a memristor device according to an embodiment of the present invention includes a resistance change semiconductor layer 300 having a substrate 100, a lower electrode 200, a resistance change memory region A, and a diode region B. FIG. ) Is sequentially formed, and the insulating layer 500 including the quantum dot 400 and the upper electrode 600 are sequentially stacked on the resistance change memory area A, and the metal electrode (B) is disposed on the diode area B. 700 is formed to have a structure in which a resistance change memory and a Schottky diode are integrated.

The substrate 100 is used to support the device. For example, the substrate 100 may be an inorganic substrate selected from glass, quartz, and Al ₂ O ₃ having a transparent and solid property, and PET having a transparent and flexible property. It may be an organic substrate selected from terephthlate (PES), polyethersulfone (PES), polystyrene (PS), polycarbonate (PC), polyimide (PI), polyethylene naphthalate (PEN), and polyarylate (PAR).

The lower electrode 200 formed on the substrate 100 is used as the lower electrode of the resistance change memory device constituting the memristor element, and has a conductivity and may include a metal-based or transparent conducting oxide. Can be. The metal may be Pt, Ru, Al, Ir, W, or Cu, wherein the transparent conductive oxide is ITO, doped ZnO (AZO: Al doped, GZO: Ga doped, IZO: In doped, IGZO: In and Ga doped , MZO: Mg doped), MgO doped with Al or Ga, In ₂ O ₃ doped with Sn, SnO ₂ doped with F Or TiO ₂ doped with Nb Lt; / RTI >

The resistance change semiconductor layer 300 formed on the lower electrode 200 has a resistance change memory region A and a diode region B. That is, the resistance change semiconductor layer 300 serves as a layer in which a conductive filament, which is a path through which current flows, is generated or extinguished in response to voltage application in a resistance change memory device constituting a memristor device. In the Schottky diode constituting, the semiconductor layer forming the metal-semiconductor junction is simultaneously performed.

Accordingly, the resistance change semiconductor layer 300 may exhibit resistance switching characteristics, and may be selected from various materials that may exhibit properties of a semiconductor forming a Schottky junction in relation to a metal electrode 700 to be described later. have.

For example, the resistance change semiconductor layer 300 may include a binary metal oxide series or a perovskite oxide series. The binary metal oxide series may include TiO ₂ , NiO, ZnO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , and perovskite Sky agent film _{SrTiO 3, BiFeO 3, BaTiO 3} , LaMnO 3, may include a SrMnO _3, PrTiO _3. It may also include Pr _{1 - x} Ca _x MnO ₃ (0 ≦ _x ≦ 1) and La _{1 - x} Ca _x MnO ₃ (0 ≦ _x ≦ 1).

The insulating layer 500 formed in the resistance change memory region A on the resistance change semiconductor layer 300 serves as a kind of tunneling barrier for passing charge when a voltage is applied in the resistance change memory device constituting the memristor device. Do this.

In addition, the insulating layer 500 serves to form a metal oxide layer (not shown) through a spontaneous oxidation reaction occurring at an interface with the upper electrode 600 formed on the insulating layer 500. Due to the metal oxide layer, a resistance switching characteristic occurs at an interface between the insulating layer 500 and the upper electrode 600, and thus may function as a resistance change memory.

The insulating layer 500 is preferably cured for a short time at a relatively low temperature so as to have a soft characteristic for interfacial reaction with the upper electrode 600, at 100 ℃ to 300 ℃ Can cure within 1 hour.

For example, the insulating layer 500 may include an organic material having insulating properties, and may include polyethersulfone (PES), polyethylene terephthlate (PET), polystyrene (PS), polyimide (PI), or poly (methyl methacrylate) (PMMA). It may include a polymer insulator.

The quantum dot 400 formed in the lower region of the insulating layer 500 traps charge at the quantum level in the deep quantum well and serves to block or conduct the movement of charge according to the applied voltage. Accordingly, the resistance change memory constituting the memristor element exhibits an asymmetric resistance switching characteristic in a specific voltage range. The quantum dot 400 includes a metal, a metal silicide, a metal oxide, or a metal oxide semiconductor, and may be formed in a single layer or multiple layers.

For example, the metal quantum dot may be at least one selected from Au, Pt, Zn, Al, Co, W, Ni, Ag, Cd, Au, Ti, Sn, Te, Ge, Ga, Se, and Fe. Silicide quantum dots include CoSi, NiSi, WSi, TiSi, V ₃ Si ₂ , MnSi. Cu ₅ Si, CaSi, SrSi, YSi, Mg ₂ Si, Ge ₂ Si, Sn ₂ Si, Pb ₂ Si, SrSi ₂ , ThSi ₂ And PtSi, and the metal oxide or the metal oxide semiconductor quantum dot is In ₂ O ₃ , CuO, Cu ₂ O ₃ , PbO, Bi ₁₂ SiO ₂₀ , ZnO ₂ , SnO ₂ , GaO, MgO, GeO , V ₂ O ₅ , BaO, SrO, Bi ₁₂ GeO ₂₀ , Bi ₁₂ SiO ₂₀ , Cd ₂ SnO ₄ , CdSnO ₃ , GaO and Li ₃ CuO ₃ At least one selected from among.

The upper electrode 600 formed on the insulating layer 500 functions as an upper electrode of the resistance change memory constituting the memristor element. In addition, it serves to form a metal oxide layer (not shown) through a spontaneous oxidation reaction occurring at the interface with the insulating layer 500 described above. Due to the metal oxide layer, a resistance switching characteristic occurs at an interface between the insulating layer 500 and the upper electrode 600, and thus may function as a resistance change memory.

The upper electrode 600 may include a metal that is easily reacted with the insulating layer 500 to form an oxide for interfacial reaction with the insulating layer 500. For example, the upper electrode 600 may be any one selected from the group of metals including Al, In, Sn, Zn, Cu, Mn, Ni, Co, Fe, and V.

The metal electrode 700 formed in the diode region B on the resistance change semiconductor layer 300 forms a metal-semiconductor junction in a relationship with the resistance change semiconductor layer 300 so as to operate as a Schottky diode. It is preferable to form a metal with a large water content. For example, the metal electrode 700 may be any one selected from In, Au, and Pt.

Therefore, the memristor device according to the embodiment of the present invention is a lower electrode 200 / resistance change semiconductor layer 300 / quantum dot 400 / insulating layer 500 / metal oxide layer (not shown) / upper electrode 600 And a second resistance change memory including a first resistance change memory including a metal oxide layer (not shown) and an upper electrode 600 formed at an interface between the insulating layer 500 and the upper electrode 600. A diode region (B) having a Schottky diode having a semiconductor-metal junction from the resistive change memory region (A) to a portion of the resistive change semiconductor layer (300) to the resistive change semiconductor layer (300) to the metal electrode (700) It consists of one cell containing).

As described above, the memristor device according to an embodiment of the present invention has a structure in which a first resistance change memory, a second resistance change memory, and a Schottky diode are integrated on one substrate. Its properties can be controlled. In addition, since the memristor element has a plurality of terminal terminals, it can be used as a resistor, a memory, or a diode according to various applications by contacting it in various ways.

2A to 2G are process diagrams illustrating a method of manufacturing a memristor device according to an embodiment of the present invention.

Referring to FIG. 2A, the lower electrode 200 is formed on the substrate 100. It is used as a lower electrode of the resistance change memory, and may be formed through thermo-phase deposition, electron beam deposition, RF sputtering, or magnetron sputtering.

The substrate 100 may be an inorganic substrate having transparent and solid characteristics, and may be an organic substrate having transparent and flexible characteristics. In addition, the lower electrode 200 formed on the substrate 100 may include a conductive metal or a transparent conductive oxide. The lower electrode 200 may be spaced apart at regular intervals to have a cross-point shape.

Referring to FIG. 2B, a resistance change semiconductor layer 300 is formed on the lower electrode 200. The resistance change semiconductor layer 300 may be formed by physical vapor deposition (PVD) or chemical vapor deposition, such as sputtering, pulsed laser deposition (PLD), thermal evaporation, and electron-beam evaporation. It may be formed using a deposition method (CVD, Chemical Vapor Deposition).

In this case, the resistance change semiconductor layer 300 preferably has a thickness of 1nm to 500nm in order to facilitate the device manufacturing process, spaced apart a predetermined distance through the lithography and etching process to form a cross-point type memory device It may be formed in the form of arranged columns. The resistance change semiconductor layer 300 may include a binary metal oxide series or a perovskite oxide series.

Referring to FIG. 2C, a metal layer 400a is formed on the resistance change semiconductor layer 300 to form a quantum dot. In this case, in order to form a diode to be described later, the metal layer 400a is preferably formed in a portion of the resistance change semiconductor layer 300. That is, the metal layer 400a is formed to expose a portion of the resistance change semiconductor layer 300.

The metal layer 400a may be formed using a physical vapor deposition method or a chemical vapor deposition method. The metal layer 400a is preferably formed to a thickness of 1nm to 5nm. At this time, the thinner the thickness of the metal layer 400a, the smaller the size of the quantum dot 400, and the thicker the thickness of the metal layer 400a, the larger the size of the quantum dot, the thickness of the metal layer 400a in a subsequent process When the metal layer 400a is changed to form a quantum dot, the metal layer 400a is preferably formed to a thickness capable of controlling the size of the quantum dot.

The metal layer 400a may be formed of Au, Pt, Zn, Al, Co, W, Ni, Ag, Cd, Au, Ti, Sn, Te, or Ge, which may react with the insulator precursor layer 500a to be described later. At least one of Ga, Se, Fe, V, Mn, Cu, Ca, Sr, Y, Mg, Pb, Ba, and Li. In addition, in order to form a cross-point type memory device, the metal layer 400a may be formed on the resistance change semiconductor layer 300 formed in a pillar shape spaced at a predetermined distance.

Referring to FIG. 2D, an insulator precursor layer 500a is formed on the metal layer 400a to form quantum dots. The insulator precursor layer 500a may be formed by spin coating, and the thickness of the insulator precursor layer 500a may be 10 nm to 50 nm. In this case, the thickness may be controlled by adjusting the wt% ratio of the insulator precursor to the solvent. The insulator precursor layer 500a may be a polyimide precursor layer.

The polyimide precursor layer is BPDA-PDA (poly (p-phenylene biphenylene carboximide)), PMDA-PDA (poly (p-phenylene pyromellitimide)), ODPA-PDA (poly (p-phenylene 3,3 ', 4,4 '-oxydiphthalimide)), 6FDA-PDA (poly (p-phenylene 4,4'-hexafluoro isopropylidene diphthalimide)), BTDA-ODA (3,3', 4,4'-Benzophenonetetracarboxylic dianhydride-4,4'-oxydianiline) , DMAc (Dimethylacetamide), BDSDA-ODA (4,4'-bis (3,4-dicarboxyphenoxy) diphenylsulfide-oxydianhydride), DSDA (3,3 ', 4,4'-diphenylsulfone tetracarboxylic acid dianhydride), BPDA-Bz ( poly (4,4'-biphenylene biphenyltetracarboximide), trimethylellitic anhydride-p-phenylene diamine (TMA-PPD) or ODA-PI (4,4'-oxydianiline-polyimide).

In this case, when using an organic substrate with weak chemical resistance, such as a polyethersulfone (PES) substrate, a photoresist material is coated on the substrate to protect the substrate, and a surface of the quantum dots is formed to expose the polyimide precursor layer by spin coating. It is preferable to form.

Referring to FIG. 2E, when the substrate 100 on which the insulator precursor layer 500a is formed is heat-treated, the metal layer 400a reacts with the insulator precursor layer 500a to form a quantum dot 400, and the insulator precursor layer 500a reacts with the metal layer 400a to form an insulating layer 500. Before the heat treatment, a soft baking process may be performed to remove the solvent in the insulator precursor layer 500a, and the soft baking may be performed at a temperature of 125 ° C to 135 ° C for 10 minutes to 60 minutes. .

In addition, the heat treatment may be a curing process for forming the insulating layer 500. At this time, the insulating layer 500 is not hardened sufficiently for the interfacial oxidation reaction with the upper electrode 600 formed on the insulating layer 500 to have a soft (soft) characteristics to 100 to It is preferable to perform the heat treatment for 10 to 60 minutes at a temperature of 300 ℃.

However, the process for forming the quantum dot is not limited thereto, and the metal layer 400a may be deposited by thermal evaporation, and then exposed to the atmosphere, thereby forming the quantum dot by using an oxidation reaction with oxygen.

Referring to FIG. 2F, upper electrodes 600a and 600b are formed on the insulating layer 500. The upper electrodes 600a and 600b may be formed of the same or different materials, and include a metal that is easy to form an oxide by reacting with the insulating layer 500 for an interface reaction with the insulating layer 500. It is preferable. For example, the upper electrodes 600a and 600b may be any one selected from a metal series including Al, In, Sn, Zn, Cu, Mn, Ni, Co, Fe, and V.

The upper electrodes 600a and 600b may be formed by using thermal image deposition, electron beam deposition, RF sputtering, or magnetron sputtering. In this case, the upper electrodes 600a and 600b may be formed to vertically cross the lower electrode 200 described above in order to manufacture a cross-point type memory device.

Referring to FIG. 2G, a diode metal electrode 700 is formed in the exposed resistance change semiconductor layer 300 to manufacture a Schottky diode made of a metal-semiconductor junction. The metal electrode 700 may be formed by sputtering or evaporation, and may be formed of a metal having a large work function to operate as a Schottky diode by forming a metal-semiconductor junction in a relationship with the resistance change semiconductor layer 300. It is preferable to be. For example, the metal electrode 700 may be any one selected from In, Au, and Pt.

In addition, the inner space of the device may be filled with a protective film (not shown) to support and protect the device and to maintain structural stability of the device. The protective layer may be a polymer insulator including PI (polyimide) or PMMA (poly (methyl methacrylate)).

Experimental Example

An ITO transparent electrode was formed on the PES substrate. Subsequently, a 160 nm thick ZnO layer was deposited on the ITO transparent electrode using an ultra-high vacuum sputtering method. At this time, the initial vacuum state was 5x10 ^-10 Torr and the deposition vacuum was 2x10 ^-3 Torr. In addition, the Ar gas flow rate was 10 sccm and was deposited at 50 W using RF magnetron sputtering. Subsequently, a Sn metal layer is deposited to a thickness of 5 nm on the ZnO layer by using an evaporation method, and exposed to air to SnO _2. Quantum dots were formed. Thereafter, a polyimide precursor layer was spin-coated to a thickness of 50 nm of a mixed solution of BPDA-PDA which is a polyimide precursor and NMP (N-Methyl pyrrolidone), which is a nonvolatile solvent, in a ratio of 1: 3 wt%. Then, the solvent is removed by soft baking at 125 ° C. for 30 minutes on a hot plate and cured at 200 ° C. for 30 minutes in a nitrogen atmosphere to form the polyimide precursor layer having a soft surface. It was formed as a (PI) layer. Subsequently, an Al electrode was formed to a thickness of 200 nm on the polyimide layer by using an evaporation method. Thereafter, an In electrode is disposed on the ZnO layer to form a Schottky diode to complete the memristor element.

3 is a circuit diagram for energy band diagram and device characteristic analysis of a memristor device according to an embodiment of the present invention.

1 and 3, a band gap is formed between the highest occupied molecular orbital (HOMO) and the lower unoccupied molecular orbital (LUMO) due to the insulating layer 500, and the upper electrode 600 and the insulating layer 500 are formed. The metal oxide layer is formed due to the metal oxidation reaction at the interface of.

Circuit 11 illustrates a second resistance change memory including a metal oxide layer (not shown) / upper electrode 600 formed at an interface between the insulating layer 500 and the upper electrode 600, and the circuit 3 represents a lower electrode ( 200) / the first resistance change memory composed of the resistance change semiconductor layer 300, the quantum dot 400, the insulation layer 500, the metal oxide layer (not shown), and the upper electrode 600. The first resistance change memory and the second resistance change memory may be connected to each other through a Schottky diode, and the characteristics of the Schottky diode may be controlled.

FIG. 4 is a hysteresis graph showing current-voltage (I-V) characteristics of a first resistance change memory constituting a memristor device according to an embodiment of the present invention.

Referring to FIG. 4, in the current-voltage characteristic curve performed 20 times with a voltage sweep in a range of −4 V to 4 V, the lower electrode / resistance change semiconductor layer / quantum dot / insulation layer / metal oxide layer / upper electrode It can be seen that the configured first resistance change memory exhibits asymmetric bipolar type resistance switching characteristics.

The high resistance state (HRS) and the low resistance state (LRS) are 8.0x10 ^-5 A and 4.3x10 ^-6 A at 1 V. The threshold voltage and current at this time 2.25x10 ^-9, and a in each case of 0.7V V _th1, is found to be 3.8x10 ^-8 a at 3 V V _th2 for.

In addition, it can be seen that the LRS / HRS ratio is 1.8x10 ⁴ at 1V. The reason for the large resistance change as described above is due to the resistance change effect due to the quantum confinement effect and the coulomb blockade effect caused by the quantum dots formed inside the insulating layer. Oxygen This is due to the movement of ions.

When a voltage is applied from 0V to 4V, charges are constrained to the quantum dots as oxygen ions are moved by oxygen vacancy inside the resistance change semiconductor layer. As time goes by, the Coulomb shielding effect that the charges are no longer confined to the quantum dots by the stored charges is maintained and high resistance is maintained. When the threshold voltage (V _th2 ) is reached, the current flows through the insulating layer by the applied voltage. do. In addition, when a voltage is applied from 4V to 0V, charges pass through the insulation layer by Fowler-Nordheim (FN) tunneling. When the threshold voltage (V _th1 ) is reached, the flow of charge is suppressed by the insulation layer and stored by the quantum dot. Due to the quantum confinement effect by the charge, an asymmetric bipolar type resistance switching effect is observed.

FIG. 5 is a hysteresis graph showing current-voltage (I-V) characteristics of a second resistance change memory constituting a memristor device according to an embodiment of the present invention.

Referring to FIG. 5, a metal oxide layer (not shown) / upper electrode formed at an interface between an insulating layer and an upper electrode in a current-voltage characteristic curve performed 20 times with a voltage sweep in a range of −4 V to 4 V. It can be seen that the second resistive change memory structure configured to have a bipolar type resistive switching characteristic. At this time, it can be seen that the maximum and minimum current values are 4x10 ^-4 A at 4V and 9.3x10 ^-9 A at 0V. In addition, the on / off ratio of the current in the voltage range of 0V to 4V is 2.45.

As described above, the resistance switching characteristics in the upper electrode / metal oxide layer / insulation layer structure are not sufficiently cured, so that the metal oxide layer is spontaneously oxidized at the interface between the soft electrode and the metal electrode that is easily formed. It is solved because it was formed.

6 is a perspective view showing a memristor device according to another embodiment of the present invention.

Referring to FIG. 6, a memristor device according to another embodiment of the present invention includes a resistance change semiconductor layer 300 having a substrate 100, a lower electrode 200, a resistance change memory region A, and a diode region B. FIG. ) Are sequentially stacked, and the insulating layer 500 including the quantum dots 400 and the first and second upper electrodes 600a and 600b formed of different materials are disposed in the resistance change memory region A. The metal electrode 700 is formed in the diode region B of the resistance change semiconductor layer 300 to form one cell.

Therefore, the first resistor change memory, the second resistor change memory, the third resistor change memory, the fourth resistor change memory, and the Schottky diode are integrated in one cell.

The description of the substrate 100, the lower electrode 200, the resistance change semiconductor layer 300, the quantum dot 400, and the metal electrode 700 for forming the diode constituting the memristor element is omitted as described above. Let's do it.

The insulating layer 500 formed in the resistance change memory region A on the resistance change semiconductor layer 300 serves as a kind of tunneling barrier for passing charge when a voltage is applied in the resistance change memory device constituting the memristor device. In addition, a metal oxide layer (not shown) may be formed through a spontaneous oxidation reaction occurring at an interface with the upper electrode 600 formed on the insulating layer 500.

The insulating layer 500 may be obtained by heat treatment of the insulator precursor layer 500a, and may change the hardness of the surface by adjusting the heat treatment conditions.

For example, the heat treatment conditions may be adjusted to form an insulating layer 500 whose surface is completely cured, and the heat treatment temperature and time at this time are sufficient to completely cure the surface so that the insulating layer 500 is chemically stable. It is preferable to select from the range. The heat treatment may be performed for 30 to 120 minutes at a temperature of 300 ℃ to 500 ℃. In this case, there is a chemically stable advantage, and at this time, the oxidation reaction does not occur at the interface with the upper electrode 600.

Therefore, in the above case, the memristor device according to another embodiment of the present invention uses the lower electrode 200 / resistance change semiconductor layer 300 / quantum dot 400 / insulating layer 500 / first upper electrode 600a. A third resistance change memory including a first resistance change memory including a lower electrode 200, a resistance change semiconductor layer 300, a quantum dot 400, an insulation layer 500, and a second upper electrode 600b; In one region of the resistive change semiconductor layer 300, the resistive change semiconductor layer 300 is composed of one cell including a Schottky diode having a semiconductor-metal junction to the metal electrode 700.

On the other hand, by controlling the heat treatment conditions can be formed in the insulating layer 500 of the soft state that the surface is not sufficiently cured, in this case, the oxidation at the interface with the upper electrode 600 formed on the insulating layer 500 The reaction occurs to form a metal oxide layer (not shown). Due to the metal oxide layer, a resistance switching characteristic occurs at an interface between the insulating layer 500 and the upper electrode 600, and thus may function as a resistance change memory. The heat treatment may be performed for 10 to 60 minutes at 100 ℃ to 300 ℃.

Therefore, in the above case, the memristor device according to another embodiment of the present invention may include the lower electrode 200 / resistance change semiconductor layer 300 / quantum dot 400 / insulating layer 500 / metal oxide layer (not shown) / A first resistance change memory including a first upper electrode 600a, and a metal oxide layer (not shown) / first upper electrode 600a formed at an interface between the insulating layer 500 and the first upper electrode 600a. A second resistance change memory including a lower electrode 200, a resistance change semiconductor layer 300, a quantum dot 400, an insulation layer 500, a metal oxide layer (not shown), and a second upper electrode 600b. A fourth resistance change memory including a third resistance change memory configured to be formed and a metal oxide layer (not shown) / second upper electrode 600b formed at an interface between the insulating layer 500 and the second upper electrode 600b And a Schottky having a semiconductor-metal junction from a portion of the resistance change semiconductor layer 300 to the resistance change semiconductor layer 300 to the metal electrode 700. It consists of a single cell containing the odd.

For example, the insulating layer 500 may include an organic material having insulating properties, and may include polyethersulfone (PES), polyethylene terephthlate (PET), polystyrene (PS), polyimide (PI), or poly (methyl methacrylate) (PMMA). It may include a polymer insulator.

The first upper electrode 600a and the second upper electrode 600b formed on the insulating layer 500 are formed of different materials and function as upper electrodes of the resistance change memory constituting the memristor element. In addition, when the above-described insulating layer 500 is formed to have soft characteristics, it may serve to form a metal oxide layer (not shown) through a spontaneous oxidation reaction occurring at an interface with the insulating layer 500. Can be.

When the upper electrode is formed of a heterogeneous material as described above, the current-voltage characteristic is changed due to the difference in oxidation characteristics of each material or the work function due to the bonding with the insulator layer 500. This results in different LRS / HRS ratios when switching the resistors, or differences in the maximum or minimum voltages. Therefore, the multi-functional resistance change memory can be implemented to vary the operation characteristics of the memristor. There is an advantage to that.

The first upper electrode 600a and the second upper electrode 600b may include a metal series having excellent conductivity, and react with the insulating layer 500 to interface with the insulating layer 500. It is preferable to include a metal which is easy to form. For example, the first upper electrode 600a and the second upper electrode 600b may be selected from metal series including Al, In, Sn, Zn, Cu, Mn, Ni, Co, Fe, and V, respectively.

As described above, in the memristor device according to another embodiment of the present invention, when the metal oxide layer is not formed by adjusting the heat treatment conditions of the insulating layer, the first resistance change memory and the third resistance change memory on one substrate. And a Schottky diode integrated structure. In addition, when the metal oxide layer is formed, the first resistive change memory, the second resistive change memory, the third resistive change memory, the fourth resistive change memory, and the Schottky diode are integrated on one substrate.

The memristor device composed of the plurality of resistance change memories may be controlled by a Schottky diode formed in a portion of the resistance change semiconductor layer. In addition, since the memristor element has a plurality of terminal terminals, it can be used as a resistor, a memory, or a diode according to various applications by contacting it in various ways.

7 is a circuit diagram for energy band diagram and device characteristic analysis of a memristor device according to another embodiment of the present invention.

6 and 7, a band gap is formed between the highest occupied molecular orbital (HOMO) and the lower unoccupied molecular orbital (LUMO) due to the insulating layer 500, and the upper electrode 600 and the insulating layer 500 are formed. The metal oxide layer is formed due to the metal oxidation reaction at the interface of.

Circuit 11 illustrates a fourth resistance change memory including a metal oxide layer (not shown) / second upper electrode 600b formed at an interface between the insulating layer 500 and the second upper electrode 600b. 2 illustrates a second resistance change memory including a metal oxide layer (not shown) / first upper electrode 600a formed at an interface between the insulating layer 500 and the first upper electrode 600a. In addition, circuit 3 includes a lower electrode 200 / resistance change semiconductor layer 300 / quantum dot 400 / insulating layer 500 / metal oxide layer (not shown) / first or second upper electrode 600a, 600b It represents a first or third resistance change memory consisting of.

The plurality of resistance change memories are circuitically connected through a Schottky diode, and the characteristics thereof can be controlled by the Schottky diode. Therefore, there is an advantage that can be used as a resistor, a memory or a diode for each application.

100 substrate 200 lower electrode
300: resistance change semiconductor layer 400: quantum dots
500: insulating layer 600: upper electrode
700: metal electrode

Claims (11)

Board;
A lower electrode formed on the substrate;
A resistance change semiconductor layer formed on the lower electrode and having a resistance change memory region and a diode region;
An insulating layer formed in the resistance change memory region on the resistance change semiconductor layer;
A quantum dot formed in the insulating layer;
An upper electrode formed on the insulating layer and reacting with the insulating layer to form a metal oxide layer; And
And a metal electrode formed in the diode region on the resistance change semiconductor layer. The method of claim 1,
The upper electrode is a memristor element, characterized in that formed of the same or different materials. The method of claim 2,
The upper electrode is any one selected from Al, In, Sn, Zn, Cu, Mn, Ni, Co, Fe and V. The method of claim 1,
The insulation layer includes a polymer insulator, and has a soft property that is not completely cured to form a metal oxide layer at the interface with the upper electrode. The method of claim 1,
The resistance change semiconductor layer is a memristor device comprising a binary metal oxide or a perovskite oxide. The method of claim 1,
The metal electrode is selected from In, Au and Pt memristor element. Forming a lower electrode on the substrate;
Forming a resistance change semiconductor layer having a resistance change memory region and a diode region on the lower electrode;
Forming an insulating layer including a quantum dot in a resistance change memory region on the resistance change semiconductor layer;
Forming an upper electrode on the insulating layer; And
Forming a schottky junction by disposing a metal electrode in a diode region on the resistance change semiconductor layer. The method of claim 7, wherein
And after forming the metal electrode in the diode region on the resistance change semiconductor layer, forming a protective film filling the internal space of the device. The method of claim 7, wherein
The upper electrode is a method of manufacturing a memristor element, characterized in that formed of the same or different materials. The method of claim 7, wherein
The forming of the insulating layer is a method of manufacturing a memristor device, characterized in that formed by heat treatment the insulator precursor layer. The method of claim 10,
The heat treatment is performed for 10 minutes to 60 minutes at a temperature of 100 ℃ to 300 ℃ to produce an insulating layer having a soft characteristic that the surface is not completely cured.

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