WO2017039611A1

WO2017039611A1 - Material stacks for low current unipolar memristors

Info

Publication number: WO2017039611A1
Application number: PCT/US2015/047726
Authority: WO
Inventors: Minxian Max Zhang; Katy SAMUELS; R. Stanley Williams; Zhiyong Li
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2015-08-31
Filing date: 2015-08-31
Publication date: 2017-03-09

Abstract

A nonvolatile memory cell includes a diode electrically coupled in series with a unipolar nonvolatile resistance memory device. The unipolar nonvolatile resistance memory device includes a switching material sandwiched between a bottom electrode and a top electrode. The switching material may include silicon dioxide. The bottom electrode and the top electrode may include copper. A memory array utilizing the memory cell and a method for manufacturing the memory array are also provided.

Description

MATERIAL STACKS FOR LOW CURRENT UNIPOLAR MEMRISTORS

BACKGROUND

[0001 ] Nonvolatile memory is computer memory that can store information even when not powered. Types of nonvolatile memory may include resistive RAM (random access memory) (RRAM or ReRAM), phase change RAM (PCRAM), conductive bridge RAM (CBRAM), ferroelectric RAM (F-RAM), etc.

[0002] Resistance memory elements, such as resistive RAM, or ReRAM, can be programmed to different resistance states by applying programming energy. After programming, the state of the resistive memory elements can be read and remains stable over a specified time period. Large arrays of resistive memory elements can be used to create a variety of resistive memory devices, including nonvolatile solid state memory, programmable logic, signal processing, control systems, pattern recognition devices, and other applications. Examples of resistive memory devices include valence change memory and electrochemical metallization memory, both of which involve ionic motion during electrical switching and belong to the category of memristors.

[0003] Memristors are devices that can be programmed to different resistive states by applying a programming energy, for example, a voltage or current pulse. This energy generates a combination of electric field and thermal effects that can modulate the conductivity of both nonvolatile switch and nonlinear select functions in a memris- tive element. After programming, the state of the memristor can be read and remains stable over a specified time period.

[0004] Memristors may be categorized as either bipolar or unipolar. Bipolar memristors may be characterized by switching between ON and OFF states under opposite voltage polarities, while unipolar memristors may be characterized by switching between ON and OFF states under the same voltage polarity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIGS. 1A-1C depicts, in perspective, a memristor crossbar array (0S1R), a selector-memristor crossbar array (1S 1R), and a diode-unipolar memristor crossbar array (1D1R), respectively, according to an example.

[0006] FIG. 2 depicts a half V scheme with selector-memristor, or diode- unipolar memristor, according to an example.

[0007] FIG. 3 is a cross-sectional view, depicting a device structure for a unipolar memristor, according to an example.

[0008] FIG. 4, in cross-sectional view, illustrates a nonvolatile memory cell that may include a selector electrically coupled in series with a unipolar nonvolatile resistance memory device, according to an example.

[0009] FIG. 5, in cross-sectional view, illustrates a nonvolatile memory cell that may include a diode electrically coupled in series with a unipolar nonvolatile resistance memory device, according to an example.

[0010] FIG. 5 A is a schematic view of the circuit elements that make up the cell depicted in FIG. 5, according to an example.

[001 1 ] FIG. 6A depicts a method of manufacturing a memory array with unipolar nonvolatile resistance memory devices and selectors, according to an example.

[0012] FIG. 6B depicts a method of manufacturing a memory array with unipolar nonvolatile resistance memory devices and diodes, according to an example.

[0013] FIGS. 7A-7E depict a process for manufacturing a memory array with unipolar nonvolatile resistance memory devices and diodes, employing a CMOS procedure, according to an example. [0014] FIGS. 8A-8F show the I-V results for a unipolar memristor having a S1O₂ active region between a C11/CU₂O bottom electrode and a Cu top electrode, using a DC scan from 0 to +3.0 V for different voltage scans, in which FIGS. 8D and 8F are semi- logarithmic plots of the same data shown in FIGS. 8C and 8E, according to an example.

DETAILED DESCRIPTION

[0015] Memristors are nano-scale devices that may be used as a component in a wide range of electronic circuits, such as memories, switches, radio frequency circuits, and logic circuits and systems. In a memory structure, a crossbar array of memristor devices may be used. When used as a basis for memories, memristors may be used to store bits of information, 1 or 0. When used as a logic circuit, a memristor may be employed as configuration bits and switches in a logic circuit that resembles a Field Programmable Gate Array, or may be the basis for a wired-logic Programmable Logic Array. It is also possible to use memristors capable of multi-state or analog behavior for these and other applications. While specific examples to memristors are provided herein, it is appreciated that many other types of nonvolatile memory may beneficially employ the teachings herein. Examples of such other types of nonvolatile memory may include resistive RAM (random access memory) (RRAM or ReRAM), phase change RAM (PCRAM), conductive bridge RAM (CBRAM), ferroelectric RAM (F-RAM), etc.

[0016] The resistance of a memristor may be changed by applying a voltage across or a current through the memristor. Generally, at least one conductive channel may be formed that is capable of being switched between two states— one in which the channel forms an electrically conductive path ("ON") and one in which the channel forms a less conductive path ("OFF"). In some cases, conducting channels may be formed by metal ions and/or oxygen vacancies. Some memristors exhibit bipolar switching, where applying a voltage of one polarity may switch the state of the memristor and where applying a voltage of the opposite polarity may switch back to the original state. Alternatively, memristors may exhibit unipolar switching, where switching is performed, for example, by applying different voltages of the same polarity. [0017] Using memristors in crossbar arrays may lead to read and/or write failure due to sneak currents passing through the cells that are not selected, for example, cells on the same row or column as a targeted cell. Failure may arise when there is insufficient current through the targeted memristor due to current sneaking through untargeted neighboring cells. As a result, effort has been spent on minimizing sneak currents. Using a transistor with each memristor has been proposed to isolate each cell and overcome the sneak current. However, using a transistor with each memristor in a crossbar array may limit array density and increases cost, which may impact the commercialization of memristor devices.

[0018] When used as a switch, the memristor may either be in a low resistance

(ON) or high resistance (OFF) state in a crosspoint memory. During the last few years, researchers have made great progress in finding ways to make the switching function of these memristors behave efficiently. For example, tantalum oxide (TaO_x)-based memristors have been demonstrated to have superior endurance over other nano-scale devices capable of electronic switching. In lab settings, tantalum oxide-based memristors are capable of over 10 billion switching cycles.

[0019] A memristor may use a switching material, such as TiO_x, HfO_x or TaO_x, sandwiched between two electrodes. Memristive behavior is achieved by the movement of ionic species (e.g., oxygen ions or vacancies) within the switching material to create localized changes in conductivity via modulation of a conductive filament between two electrodes, which results in a low resistance "ON" state, a high resistance "OFF" state, or intermediate states. Initially, when the memristor is first fabricated, the entire switching material may be nonconductive. As such, a forming process may be required to form the conductive channel in the switching material between the two electrodes. A known forming process, often called "electroforming", includes applying a sufficiently high (threshold) voltage across the electrodes for a sufficient length of time to cause a nucleation and formation of a localized conductive channel (or active region) in the switching material. The threshold voltage and the length of time required for the forming process may depend upon the type of material used for the switching material, the first electrode, and the second electrode, and the device geometry. [0020] Metal or semiconductor oxides may be employed in memristive devices; examples include either transition metal oxides, such as tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, niobium oxide, zirconium oxide, or other like oxides, or non-transition metal oxides, such as aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, or other like oxides. Further examples include transition metal nitrides, such as aluminum nitride, gallium nitride, boron nitride, and silicon nitride.

[0021 ] TaOx and HfO_x based memristors have demonstrated the most promising results. However, both of these oxide systems have a linear current-voltage relation in the ON state, which is not desired due to the sneak path current issue, described above. For applications in high density crossbar arrays, a nonlinear selector may be in series with each memristor to form a 1 S1R (one selector - one resistor) structure. A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple metal-oxide-metal structure realized by the Schottky emission over the metal/oxide barriers or the resistance change associated with insulator-metal-transition (IMT) or other methods. Some IMT materials can be used for the selectors (e.g., VO2, T12O3, NbC , etc.). The metal for the bottom electrode and the top electrode can be TiN, TaN, etc. As an example, both TaN/Nb0₂/TaN and TiN/Nb₂0/TiN have shown good performance.

[0022] However for practical applications, the selectors presently under development may not be able to meet the requirement for both high nonlinearity (>1000), low leakage current (less than 1 nA at below threshold voltage), and high current density requirement at above threshold voltage (on the order of 10⁶ A/cm²). As used herein, "high nonlinearity" is based on a comparison of the current density level at two different voltages, here, V and V/2, where V is the selected cell voltage and V/2 is the half-selected cell voltage. The selector's threshold voltage is between V/2 and V. The ratio of the two current densities should be at least 10³ to be considered a useful nonlinearity. In some cases, the ratio may approach or even exceed 10⁶ for improved nonlinearity.

[0023] Unipolar memristors are characterized by switching between ON and

OFF states under the same voltage polarity. This will relieve the requirements on selectors so that selectors with diode behavior can be used for unipolar memristors. This may also be a challenge because the unipolar reset process is commonly referred to be thermally -based, which may require high switching OFF energy. For a bipolar memris- tor, the directions of ionic movement can be changed with different voltage polarities. Therefore, it is possible to switch ON a device with low energy, as well as to switch OFF a device with a similar low energy. For a unipolar memristor, the device can be switched to ON with low energy. However, to switch device to OFF, since the direction of ion movement cannot be changed during the reset process, a high energy (Joule heating) may be introduced to "dissolve" or "fuse" the metal-rich conductive channel by thermal oxidation locally at a spot along the channel. Therefore, it is not surprising that unipolar switching may require high switching OFF energy compared to switching ON energy. On the other hand, since the conductive channel is "fused" during the unipolar reset process, it may have the advantage of a high switch ON to switch OFF memristor ratio.

[0024] In accordance with the teachings herein, a low current unipolar memristor may be made with a matrix oxide (e.g., S1O₂) and both electrodes based on a fast diffusing cation metal, such as Cu. By "low current" is meant that the current needed to switch the unipolar memristor is approximately from 10 μΑ to 100 μΑ, where 10 μΑ or sub-10 μΑ may be considered to be low current for the switch ON process, and 100 μΑ or sub- 100 μΑ may be considered to be low current for the switch OFF process. By "fast-diffusing" is meant that the rate of diffusion should be faster than the rate of diffusion of oxygen vacancies in a memristor oxide (or nitrogen vacancies in a memristor nitride). Specifically, interstitial diffusion is much fast than substitutional diffusion. There are two main lattice point defects: interstitial and substitutional. Interstitial diffusion has a lower activation energy, and a higher jump frequency (neighboring interstitial sites are always vacant). Substitutional diffusion has a higher activation energy, and a lower jump frequency (neighboring substitutional site may not be vacant). Cu, Ag, and Au are some examples of fast diffusers.

[0025] A new materials stack is disclosed from which low current unipolar memristor switching may be observed. In an example, a combination of Οι/(¾0 may be used as the bottom electrode, S1O2 as the dielectric active region, and Cu as the top electrode. In one example, unipolar switching was observed at 10 μΑ switch ON, and about 35 μΑ switch OFF. When the switch ON current was lowered to 1 μΑ, the switch OFF current was also lowered to about 6 μΑ. Such low unipolar switch ON and OFF current is comparable to low current bipolar memristors and can be useful in unipolar memristor applications to reduce sneak currents.

[0026] The nonvolatile memory element, here, the unipolar memristor, may be configured in series with a selector, such as a threshold switching selector, a transistor, or a diode. The term "in series" means that the components are electrically connected along a single path so that the same current flows through all of the components. While the components may be in series, they may or may not be in direct contact with one another, and the order of the components may vary.

[0027] In an example, the unipolar memristor may evidence high nonlinearity and nonvolatile characteristics. The terms "linear" and "nonlinear" refer to the nature of the current- voltage (I-V) curve; that is, whether the curve is linear or nonlinear, respectively. As used in the present specification and in the appended claims, the term "nonlinear" may refer to a property of the memristor wherein a change in voltage applied across the memristor results in a disproportionate change in current flowing through the selector or memristor, respectively.

[0028] The sneak-path issue is inherent for crossbar array architectures, regardless of the memory element employed. FIG. 1A depicts a crossbar array 100 containing a plurality of memory elements 102, here, unipolar memristors. This array can be referred to as memristor only (1R or 0S1R, where OS means no selector). Each memory element 102 may include a switching material, such as a switching oxide or switching nitride, sandwiched between a bottom electrode and a top electrode (not visible in FIG. 1, but depicted in FIG. 4). Each memory element 102 may be sandwiched between a bottom electrically conducting trace 106 and a top electrically conducting trace 108. The crossbar 100 is made of a lower layer 1 10 of electrically conducting traces formed by a plurality of bottom conducting traces 106 and an upper layer 1 12 of electrically conducting traces formed by a plurality of top conducting traces 108, with the memory element 102 at each crosspoint 1 14 formed by a bottom trace 106 and a top trace 108. The bottom conductive traces 106 may be referred to as row, or bit, lines, while the top conductive traces 108 may be referred to as column, or word, lines. However, it is immaterial whether the row (bit) lines are above or below the column (word) lines.

[0029] FIG. 1A depicts the situation that while trying to read the high resistive element 102a, a current sneak path may exist due to three low resistive elements 102b. The thin line 116 with arrow head shows the desired current path. The dashed line 118 with arrow head shows a sneak path current path.

[0030] A solution, illustrated in FIG. IB, may be generally referred as 1S1R, where S is the selector and R is the memristor. The selector can be a general threshold switching selector, which may be capable of operating at both voltage polarities for a bipolar memristor, and may operate at single voltage polarity for a unipolar memristor. A special case of FIG. IB is shown in FIG. 1C, where the memristor is unipolar, and the selector is a diode, referred to as 1D1R here. The presence of a diode may be to ensure that the voltage flows only in one direction, that is, of the same polarity as the polarity to operate the memristor. Blocking the opposite voltage polarity flow may result in reduction or even elimination of the sneak path current path 118. As noted above, a nonlinear, nonvolatile memristor cell 102' may include a diode 300 (discussed below in connection with FIG. 3) and the unipolar memristor element 102. The unipolar memristor 102 may be nonlinear and nonvolatile, while the diode 300 may provide required current-voltage non-linearity under forward bias, and prevent current from flowing under reverse bias. While these are the ideal states of the diode 300 and memristor 102, respectively, it is understood that there may be slight variations from the ideal state. In any event, the net intent is to provide a memory cell 102' that is both nonlinear and nonvolatile and in which the voltage is of one polarity.

[0031 ] The nonlinear element in series with memristor in FIG. IB can be a general selector (1S1R), or specifically, a transistor (1T1R), or a diode (1D1R). A selector may have nonlinearity in both voltage polarities. Although a unipolar memristor operates at one voltage polarity, a bipolar selector may be used in series with a unipolar memristor. In this case, the selector and memristor can be stacked up and formed between crossbar junctions. A transistor may also be used in series with a unipolar memristor, since the transistor may be act as cell selector as well as the current limiter (by controlling the gate voltage). However, 1T1R configuration may increase the cell size, since the transistor is a three-terminal device. A diode may also be used as the non-linear element specifically for a unipolar memristor. A diode has strong asymmetry (rectification) with strong non-linearity (exponential). Some advantages of diode selector over transistor selector are: small cell size (the diode is a two-terminal device), simple to fabricate, and easy to operate. A diode may also have excellent operation endurance.

[0032] The crossbar array 160 shown in FIG. 1C is similar to the crossbar array

150 shown in FIG. IB, except the selector (S) 300 in FIG. IB is replaced with a diode (D) 300' in FIG. 1C. This is possible since the memristor 102 is unipolar. The diode may operate in a forward bias voltage polarity for unipolar switching. The diode 300' may be used to mitigate the sneak path current issue by suppressing the total current passing through the non-selected devices in the array at a voltage polarity opposite to that used to operate the unipolar memristor. In some examples, the diode 300' may be a simple p-n junction structure.

[0033] The concept for a selector associated with a popular reading scheme for a general 1S1R cell is shown in FIG. 2. The selected low resistance cell is denoted 102'a and the half selected cells having high resistance are denoted 102'b. The high resistance cells 102'b are in the same row or column as the selected cell 102'a. It is the high resistance cells 102'b that may suppress sneak path currents. V is the selected cell voltage, V/2 is half selected cell voltage, and G is ground. V/2 and V are determined such that the selector threshold voltage is between V/2 and V. It should be pointed out the read scheme in FIG. 2 may also be applied to the 1D1R crossbar array. In the 1D1R case, the selector threshold voltage may be replaced with the diode threshold voltage, or forward biased knee voltage, which is the voltage above which the diode current increases exponentially with bias voltage.

[0034] The unipolar memristor 102, shown in FIG. 3 may include a bottom electrode 202, a top electrode 204, and an active switching region 206 disposed between the two electrodes. The bottom electrode 202 may be made of two sub-layers, copper layer 202a and copper oxide (Ο½0) layer 202b, with the copper oxide layer in physical contact with the active region oxide 206. The top electrode 204 may include copper. Alternatively, the bottom electrode may include copper and the top electrode may be made of the two sublayers. In an example, both the bottom and top electrodes 202, 204 may be made of the two sublayers. The thickness of the electrodes 202, 204 may be in the range of 0.3 to 20 nm. In an alternate configuration, the bottom electrode 202 may made of copper and the top electrode 204 may be made of the two sub-layers 202a, 202b. In some examples, the minimum thickness may be 0.6 nm. In other examples, one or both copper electrodes may be based on a copper alloy. A copper alloy may help improve adhesion of the electrode to an underlying layer and/or to the active region oxide matrix 206. Examples of suitable elements for alloying with copper may include Ni and Pt, either of which can form continuous solid solution with Cu. In addition to providing increased adhesion, Ni can also change the amount of Cu moving into S1O2 under the same electric pulse. Essentially, the presence of nickel can reduce the amount of Cu available to diffuse into the oxide, since nickel has been reported to diffuse much slower than copper in S1O2. Actually, nickel may be used as one of the diffusion barrier materials between copper and S1O2.

[0035] As indicated above and as shown in FIG. 4, an example nonvolatile memory cell 102' may include the selector 300 electrically coupled in series with the unipolar nonvolatile resistance memory device, such as unipolar memristor 102. In a crossbar configuration (FIG. IB, 150), each memory cell 102' may be disposed at the intersection 114 formed by one of the bottom conducting traces 106 and one of the top conducting traces 108. The selector may include a bottom electrode 302, a top electrode 304, and a selector oxide matrix 306 therebetween. One or both of the bottom electrode 302 and the top electrode 304 may include an alloy containing a fast diffusing cation metal and a metal that promotes adhesion to the selector oxide matrix, while the selector oxide matrix 306 may include silicon dioxide, for example.

[0036] In a specific example of a selector and as indicated above and as shown in FIG. 5, an example nonvolatile memory cell 102' may include the diode 300' electrically coupled in series with the nonvolatile resistance memory device, such as unipolar memristor 102. In a crossbar configuration (FIG. 1C, 160), each memory cell 102' may be disposed at the intersection 114 formed by one of the bottom conducting traces 106 and one of the top conducting traces 108. The diode 300' may include an n-type (or p- type) semiconductor layer 310 and a p-type (or n-type) semiconductor layer 312, form- ing a p-n junction 314. The type of the diode (n-p or p-n) may depend on the direction in which the current is required to flow.

[0037] The diode 300', in one example, may be formed with different manufacturing processes. For example, a diode may be formed by thin film deposition techniques, or formed on the silicon wafer during the Front End of Line (FEOL) semiconductor process. A thin film diode may be formed in series with the unipolar memristor at the crosspoint of the bottom conductive trace and the top conducive trace. Examples of thin film diodes may be based on thin film Schottky -barriers or thin film p-n junctions. Thin film Schottky-barrier diodes may be formed with an M/I/M structure, with I being a semiconductor or insulator, and M being a metal or other conductive material. Different M materials may be selected to contact the semiconductor I such that it may form a potential barrier (rectifying) at one contact and form an ohmic interface at the other contact. Thin film p-n junction diodes may be formed between p-type and n-type materials through thin film deposition techniques.

[0038] The diode may also be formed by joining p-type (doped with B, or Al) and n-type (doped with P, As or Sb) semiconductors without disturbing the crystalline continuity across the junction. The p-n junction may be a thin layer depleted with mobile charges (electrons and holes) and may behave like an insulator under zero voltage bias. Under forward voltage bias (positive voltage on p-region and negative voltage on n-region), the depletion layer thickness may decrease, which may increase forward current sharply. On the other hand, under reverse voltage bias, (negative voltage on p- region and positive voltage on n-region), the depletion layer thickness may increase which may prevent current flow through the junction. In an example discussed below, the p-n junction may be formed via a semiconductor process, prior to forming the memristor (see FIGS. 7A-7E).

[0039] As indicated above and as shown in FIG. 4, an example nonvolatile memory cell 102' may include the selector 300 electrically coupled in series with the nonvolatile resistance memory device, such as unipolar memristor 102. In a crossbar configuration (FIG. IB, 150), each memory cell 102' may be disposed at the intersection 114 formed by one of the bottom conducting traces 106 and one of the top conducting traces 108. Likewise, as indicated above and as shown in FIG. 5, an example memory cell 102' may include the diode 300' electrically coupled in series with the nonvolatile resistance memory device, such as unipolar memristor 102. In a crossbar configuration (FIG. 1C, 160), each memory cell 102' may be disposed at the intersection 1 14 formed by one of the bottom conducting traces 106 and one of the top conducting traces 108.

[0040] FIG. 5 A shows the equivalent electrical circuit of the memory cell 102' depicted in FIG. 5, depicting the diode 300' electrically connected in series with the memristor 102, here, a unipolar memristor. The polarity of the diode may be selected such that the unipolar memristor operates under forward bias of the diode.

[0041 ] The teachings herein may be employed with a crossbar that is fabricated with resistance memory devices, or resistance random access memory devices, denoted RRAM or ReRAM, such as phase change RAM (PCRAM), spin transfer torque RAM (STTRAM), conductive bridge RAM (CBRAM), and others. In some examples, the nonvolatile resistance memory device 102 may be a memristor.

[0042] In some examples, the nonvolatile memory cell 102' may include an optional interface layer 308 sandwiched between the first top electrode 204 of the nonvolatile resistance memory device 102 and the p- (or n-) layer 302 of the selector 300. The interface layer 308 may serve as a buffer layer to separate the memristor and diode so that they do not chemically and/or physically interfere with each other. The interface layer 308 may be a good electrical conductor over the temperature range from room temperature (approximately 20° to 26°C) to about 1 10°C and a good diffusion barrier, which may be used to prevent the fast diffusion species such as Cu from diffusing from the memristor 102 to the diode 300, or vice versa. In some examples, the interface layer 308 may be a metal, such as tantalum or tungsten. The choice of a material for the interface layer may depend on layers below and above it. Additional non-limiting examples of the interface layer 308 may include TiN, T14O7, TaN, NbN, Ru, and W. The interface layer 308 is optional, in that it may be omitted, since the nonvolatile memory cell 102' may operate fine without it. Alternatively, it may be used for an improved device 102', but accepting the costs associated with providing the extra layer.

[0043] A memory array, or crossbar, 150 (in FIG. IB), 160 (in FIG. 1C) having nonvolatile resistance memory devices may include a set 110 of electrically conducting row traces 106 intersecting a set 112 of electrically conducting column traces 108 to form intersections 1 14, with a memory cell 102' disposed at each intersection between one of the row lines and one of the column lines. As shown in FIG. 4, the memory cell 102' may be a combination of a selector 300 electrically coupled in series with the nonvolatile resistance memory device 102, as described above. As shown in FIG. 5, the memory cell 102' may be a combination of a diode 300' electrically coupled in series with the nonvolatile resistance memory device 102, as described above. The first bottom electrode 202 may be electrically coupled to a row trace 106 or to a column trace 108 and wherein the second top electrode 304 (selector or diode), may be electrically coupled to the other of the row trace 106 or the column trace 108.

[0044] The electrodes 302, 304 for the selector 300 and the electrically conducting traces 106, 108 may be made of conducting materials such as, but not limited to, aluminum (Al), nickel (Ni), platinum (Pt), tungsten (W), gold (Au), titanium (Ti), ruthenium dioxide (RuC^), titanium nitride (TiN), tungsten nitride (WN₂), tantalum (Ta), hafnium nitride (HfN), niobium nitride (NbN), tantalum nitride (TaN), and the like.

[0045] A method of manufacturing a memory array with nonvolatile resistance memory devices and selectors is depicted in FIG. 6A. The method 600 includes providing 605 a set 1 10 of electrically conducting row traces 106. The electrically conducting row traces 106 may be formed by any of a number of processes, including electroplating, sputtering, evaporation, ALD (atomic layer deposition), co-deposition, chemical vapor deposition, IBAD (ion beam assisted deposition), oxidation of pre-deposited materials, or any other film deposition technology.

[0046] The method 600 further includes providing 610 memory cells 102' disposed at a plurality of locations along the set 1 10 of row traces 106. The memory cell 102' may include the nonvolatile resistance memory device 102 electrically coupled in series with the selector 300, as described above.

[0047] Taking FIG. 4 as an example, deposition of the metal layers 202a and

204 may be performed by such processes as electroplating, sputtering, evaporation, ALD (atomic layer deposition), co-deposition, chemical vapor deposition, IBAD (ion beam assisted deposition), oxidation of pre-deposited materials, or any other film deposition technology. The copper oxide layer 202b, the switching material layer 206, and the optional interface layer 308, may be formed by e-beam deposition, sputter deposition, atomic layer deposition (ALD), and the like. The layers 202a, 202b, 206, 204, 308 (if used), 302, 306, and 304 may be deposited sequentially. It will be appreciated that in FIG. 3, the selector 300 is shown on "top" and the memristor 102 is shown on the "bottom" of the cell 102'. However, in some examples, the memristor 102 may be on "top" and the selector 300 on the "bottom".

[0048] The method 600 concludes with providing 615 a set 112 of electrically conducting column traces 108 to contact the memory cells 102' at unique intersections 114. The electrically conducting column traces 112 may be formed by any of a number of processes, including electroplating, sputtering, evaporation, ALD (atomic layer deposition), co-deposition, chemical vapor deposition, IBAD (ion beam assisted deposition), oxidation of pre-deposited materials, or any other film deposition technology. The process used may be the same as or different than the process used to form the electrically conducting row traces 110. The order of the steps of method 600 may be reversed, so that the column traces 108 are formed first and the row traces 106 are formed last.

[0049] A method of manufacturing a memory array with nonvolatile resistance memory devices and diodes is depicted in FIG. 6B. FIG. 6B is similar to FIG. 6A; indeed, the procedures 605 and 615 may be essentially the same. In procedure 610', the p and n junction may be deposited by thin film deposition of p-type and n-type layers 610, 612.

[0050] An alternate procedure, shown in FIGS. 7A-7E, depicts a method of manufacturing a diode 300' in series with a unipolar nonvolatile resistance memory device 102, such as a memristor. The diodes may be fabricated on a silicon wafer by a Front End of Line (FEOL) semiconductor process. Diode terminals 302, 304 and bottom conducting traces 106 may be formed through metallization. Unipolar memristors 102 may be formed on one of the diode terminals, followed by top conducting traces 108.

[0051 ] In FIG. 7A, a silicon wafer 702 may be provided. Any of the common silicon materials used in semiconductor manufacturing may be employed. [0052] In FIG. 7B, a plurality of p-n junction diodes 300' may be formed, employing a CMOS (complementary metal oxide semiconductor) process. Shown in FIG. 7B are four such diodes 300'.

[0053] In FIG. 7C, diode metallization may be provided. In this case, one terminal of each diode 300 'may be connected to a bit line 106 and the other terminal may be connected to the bottom electrode 202a of a unipolar memristor 102 (to be formed in the next step).

[0054] In FIG. 7D, the unipolar memristor 102 may be fabricated. Fabrication of the unipolar memristor 102 may be performed by any of the procedures described above.

[0055] In FIG. 7E, the word line 108 may be fabricated over the top electrode

204 of the unipolar memristor 102. The specifics of this fabrication step, as well as others in FIGS. 7A-7D, have been described above.

[0056] To prove the concept, a unipolar memristor 102 was fabricated having the structure as shown in FIG. 3. The bottom electrode 202a, 202b was Ti 2 nm/Cu 15 nm/Cu20 5nm. Ti and Cu were evaporated through a shadow mask and C¾0 was sputtered through the same shadow. Ti was used as an adhesion layer between the Si substrate (covered with thermally grown S1O2) and Cu. S1O2 15 nm was a blanket film, sputtered from a S1O2 target, to form the active region 206. The top electrode 204 was Cu 10 nm/Pt 20 nm evaporated through a shadow mask. The effective device stack was CU2O/S1O2/CU. A diode 300 was not included in this example.

[0057] The electric characterizations of the device are shown in FIGS. 8A-8F.

Specifically, as shown in FIG. 8A, under a first positive voltage scan, device switched to ON at about 1.5V and reached current compliance at 1 μΑ. The arrows indicate the direction of the scan. In FIG. 8B, under a second positive voltage scan, the device started from the previous ON state (overlapping the returning portion of the first scan), indicating that the first scan was nonvolatile (i.e., memristor behavior). The arrows indicate the direction of the curve. In FIG. 8C, under a third positive voltage scan, the device started from previous ON state (overlapping the returning portion of the second scan), indicating that the second scan was nonvolatile (i.e., memristor behavior). The arrows indicate the direction of the curve. FIG. 8D, which is a semi-logarithmic plot of FIG. 8C, indi- cates that the switching from the first scan was nonvolatile, which was also confirmed by the second and third scans. In FIG. 8E, under a fourth positive voltage scan where the current compliance was increased, the device started from the previous ON state and then switched to the OFF state under the same voltage polarity (i.e., unipolar memristor behavior). The arrows indicate the direction of the scan. The second and third scan curves have been omitted for clarity. FIG. 8F, which is a semi-logarithmic plot of FIG. 8E, indicates low current unipolar memristor behavior.

[0058] It is appreciated that, in the foregoing description, numerous specific details are set forth to provide a thorough understanding of the examples. However, it is appreciated that the examples may be practiced without limitation to these specific details. In other instances, well-known methods and structures may not be described in detail to avoid unnecessarily obscuring the description of the examples. Also, the examples may be used in combination with each other.

[0059] While a limited number of examples have been disclosed, it should be understood that there are numerous modifications and variations therefrom. Similar or equal elements in the Figures may be indicated using the same numeral.

[0060] It is be noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0061 ] It is appreciated that, in the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, it is appreciated that the examples may be practiced without limitation to these specific details. In other instances, well-known methods and structures may not be described in detail to avoid unnecessarily obscuring the description of the examples. Also, the examples may be used in combination with each other.

[0062] While a limited number of examples have been disclosed, it should be understood that there are numerous modifications and variations therefrom. Similar or equal elements in the Figures may be indicated using the same numeral.

Claims

CLAIMS What is claimed is:

1. A nonvolatile memory cell, including:

a unipolar nonvolatile resistance memory device, the unipolar nonvolatile resistance memory device comprising a switching material sandwiched between a bottom electrode and a top electrode;

wherein the switching material includes silicon dioxide, and wherein the bottom electrode and the top electrode include copper.

2. The nonvolatile memory cell of claim 1, wherein the unipolar nonvolatile resistance memory device is a unipolar memristor.

3. The nonvolatile memory cell of claim 1, wherein one or both electrodes comprises two sub-layers, a copper layer and a copper oxide ((¾0) layer, with the copper oxide layer interfacing between the copper layer and the switching material.

4. The nonvolatile memory cell of claim 1 , wherein the switching material comprises either a mixture of S1O2 and a secondary oxide selected from the group consisting of AI2O₃, Hf0₂, Zr0₂, Ta₂0₅, and T1O2, in which the secondary oxide is present in an amount up to about 10 at% based on the metal cation or a mixture of S1O2 and copper or copper oxide in which copper is present in an amount up to about 5 at%.

5. The nonvolatile memory cell of claim 1, further including a selector in electrical series with the unipolar nonvolatile resistance memory device.

6. The nonvolatile memory cell of claim 5, wherein the selector is a diode.

7. A memory array with nonvolatile memory cells, the memory array including: a set of electrically conducting row lines intersecting a set of electrically conducting column lines to form intersections; and

each nonvolatile memory cell disposed at each intersection between one of the row lines and one of the column lines;

wherein the memory cell comprises a unipolar nonvolatile resistance memory device electrically coupled in series with a selector, the unipolar nonvolatile resistance memory device comprising a switching material sandwiched between a first bottom electrode and a first top electrode,

wherein unipolar nonvolatile resistance memory device includes an active region comprising silicon dioxide,

wherein the second bottom electrode and the second top electrode include copper, and

wherein the first bottom electrode is electrically coupled to a row trace or to a column trace and wherein the second top electrode is electrically coupled to the other of the row trace or the column trace.

8. The memory array of claim 7, wherein the unipolar nonvolatile memory device is a unipolar memristor and wherein the selector is a diode.

9. The memory array of claim 7, wherein one or both electrodes comprises two sub-layers, a copper layer and a copper oxide ((¾0) layer, with the copper oxide layer interfacing between the copper layer and the switching material.

10. The memory array of claim 7, further including an interface layer sandwiched between the first top electrode of the nonvolatile resistance memory element and the second bottom electrode of the diode, the interface layer acting as a diffusion barrier while being electrically conducting, wherein the interface layer comprises a material selected from the group consisting of TiN, T14O7, TaN, Ta, NbN, Ru, and W.

11. A method of manufacturing a memory array with nonvolatile memory cells, the method including:

providing a set of electrically conducting row traces;

providing a memory cell disposed at a plurality of locations along each of the row traces, wherein each memory cell comprises a unipolar nonvolatile memory device electrically coupled in series with a selector, the unipolar nonvolatile resistance memory device comprising a switching material sandwiched between a first bottom electrode and a first top electrode; and

providing a set of electrically conducting column traces to contact the memory cells at unique intersections,

wherein each nonvolatile memory device comprises a switching material sandwiched between a first bottom electrode and a first top electrode,

wherein the first bottom electrode of each memory device is electrically coupled to a given row trace or to a given column trace and wherein the second top electrode of each selector is electrically coupled to the other of the row trace or the column trace.

12. The method of claim 11, wherein the unipolar nonvolatile resistance memory device is a unipolar memristor.

13. The method of claim 11, wherein one electrode comprises Cu metal or Cu alloy, and the other electrode comprises Cu with a layer of CU2O between the Cu and the switching material.

14. The method of claim 11, wherein the selector is a diode.

15. The method of claim 14, wherein the diode has a p-n junction and is provided first, by a Front End of Line CMOS process, followed by providing the set of electrically conducting row traces and the remainder of the method.