CN113013257A - Nanowire type synaptic transistor without tunneling oxide layer and preparation method thereof - Google Patents

Nanowire type synaptic transistor without tunneling oxide layer and preparation method thereof Download PDF

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CN113013257A
CN113013257A CN202110205069.8A CN202110205069A CN113013257A CN 113013257 A CN113013257 A CN 113013257A CN 202110205069 A CN202110205069 A CN 202110205069A CN 113013257 A CN113013257 A CN 113013257A
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nanowire
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黎明
李小康
涂坤
黄如
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Abstract

The invention discloses a nanowire type synaptic transistor without a tunneling oxide layer and a preparation method thereof, belonging to the field of synaptic devices for neuromorphic computing application. The nanowire type synaptic transistor without the tunneling oxide layer adopts the design of a silicon nitride and hafnium oxide double-trapping layer, so that the charge-trapping type synaptic device can simulate long-time synaptic plasticity and short-time synaptic plasticity, and the function of the synaptic transistor is greatly enriched. In addition, the operating voltage of the synapse device is reduced by changing the programming mode, namely, by programming once and then changing the charge trapping position instead of the charge trapping amount, and the combination of the tunneling-free oxide layer and the high-k/metal gate. The synaptic transistor based on the charge trapping mechanism, which has the advantages of low-voltage operation and can simulate multifunctional synaptic plasticity, is expected to be applied to future large-scale artificial neural networks.

Description

Nanowire type synaptic transistor without tunneling oxide layer and preparation method thereof
Technical Field
The invention belongs to the field of synapse devices for artificial neural network accelerator application, and relates to a low-voltage and multifunctional nanowire type synapse transistor without a tunneling oxide layer and a preparation method thereof.
Background
The neuromorphic computing is a novel computing architecture which is expected to break through the bottleneck of von Neumann and is realized by simulating a biological neural network with high energy efficiency, high-density connection and high fault tolerance. At present, synapse devices for building artificial neural networks include Resistive Random Access Memories (RRAMs), Phase change memories (PCRAMs), Magnetic Random Access Memories (MRAMs), Charge Trapping memories (CTRAMs), Ferroelectric Random Access memories (ferams), and the like, wherein the Charge Trapping memories have good CMOS process compatibility and can achieve high integration density through mature three-dimensional integration processes. However, since the conventional charge trap memory operates based on a nonvolatile mechanism, it cannot simulate the same important short-term plasticity. In addition, the current charge trap type memory has a problem of high operating voltage, and a new structure or a new principle is required to lower the operating voltage.
Therefore, developing a synaptic transistor with low voltage operation capability and capable of simulating both short-term plasticity and long-term plasticity charge trapping mechanism is necessary for building complex artificial neural networks in the future.
Disclosure of Invention
In view of the above, the present invention provides a low voltage and multifunctional nanowire-type synapse transistor without a tunneling oxide layer. The transistor adopts a silicon nitride and hafnium oxide double-trapping layer structure, namely, a silicon nitride trapping layer which is close to a channel and has shallow trap energy levels is used for realizing short-time synaptic plasticity, and a hafnium oxide trapping layer which is far away from the channel and has deep energy level defects is used for realizing long-time synaptic plasticity. In addition, the operation mode of one-time programming and then changing the charge trapping position instead of the charge trapping amount is adopted, and the design without a tunneling oxide layer and the structure of a high-k/metal gate are adopted to reduce the operation voltage and reduce the trapping time constant of charges stored in a silicon nitride layer, so that the abundant short-time-range synaptic plasticity is realized.
The low-voltage and multifunctional nanowire type synapse transistor without the tunneling oxide layer comprises an SOI substrate, a nanowire channel region, a source region, a drain region, a charge double trapping layer, a high-k dielectric layer and a metal gate, wherein the charge double trapping layer consists of a silicon nitride trapping layer and a hafnium oxide trapping layer; forming a source drain region and a nanowire channel region connecting the source drain region and the nanowire channel region on the SOI substrate, and sequentially forming a silicon nitride trapping layer, a hafnium oxide trapping layer, a high-k dielectric layer and a metal gate from the nanowire channel region to the outside; and forming a device isolation region between the devices in an island isolation manner, wherein the isolation layer covers the whole device and is used as a metal extraction layer.
In the synapse transistor, the line width of the nanowire channel region is preferably 10-40 nm.
The synapse transistor simultaneously realizes synapse plasticity of short and long time ranges by a double trapping layer structure consisting of a silicon nitride trapping layer with shallow defect energy levels close to a channel and a hafnium oxide trapping layer with deep energy level defects far away from the channel. Preferably, the thickness of the silicon nitride trapping layer is 3-5 nm, and the thickness of the hafnium oxide trapping layer is 3-5 nm.
The gate electrode of the synapse transistor is a metal gate, the material of the metal gate is preferably titanium nitride, aluminum, tantalum, tungsten, tantalum nitride and the like, and the thickness of the metal gate is 50-200 nm. The high-k dielectric layer is preferably made of aluminum oxide, tantalum oxide and the like, and the thickness of the high-k dielectric layer is preferably 8-10 nm.
The isolation layer is generally a silicon oxide isolation layer.
The invention also provides a preparation method of the low-voltage and multifunctional nanowire type synaptic transistor without the tunneling oxide layer, which comprises the following steps:
1) thinning a silicon film on the surface of the SOI substrate, determining the height of a nanowire channel region by the thickness of the thinned silicon film, carrying out light doping on the front surface, and carrying out impurity activation by rapid thermal annealing treatment;
2) patterning by utilizing a photoetching technology, and etching the silicon film to form a nanowire-type structure with source-drain large fan-out regions at two ends;
3) depositing a silicon nitride trapping layer, a hafnium oxide trapping layer, a high-k dielectric layer and a metal gate layer on the structure in the step 2) in sequence;
4) defining metal gate lines by an ultraviolet photoetching technology;
5) performing injection doping on the source region and the drain region, and annealing to activate impurities;
6) and depositing an isolation layer, flattening the surface, and then manufacturing metal extraction of a source drain gate.
For the preparation of the N-type synapse transistor, a P-type SOI substrate is adopted in the step 1), P-type light doping is carried out on a surface silicon film, and N-type heavy doping is carried out on a source region and a drain region in the step 9); and for the preparation of the P-type synapse transistor, an N-type SOI substrate is adopted in step 1), N-type light doping is carried out on a surface silicon film, and P-type heavy doping is carried out on a source region and a drain region in step 9). Wherein the P-type dopant implantation impurity is BF2 +And B+Etc. N-type doping with As As impurity+And P+And the doping method is a conventional technical means in the field, and is not described in detail herein.
The step 2) specifically includes:
2a) spin-coating inorganic negative photoresist such as HSQ (hydrogen silsesquioxane) electron beam photoresist containing hydrogen silicate on an SOI substrate, and patterning the inorganic negative photoresist as a nanowire hard mask by using an electron beam lithography technique;
2b) spin-coating an organic positive photoresist, and patterning the organic positive photoresist as a source-drain mask by using an ultraviolet lithography technology;
2c) the method comprises the following steps of (1) etching a silicon film by a dry method by taking a nanowire hard mask (inorganic glue) and a source-drain mask (organic glue) as a mixed mask to form a nanowire type structure with source-drain large fan-out areas at two ends;
2d) and removing the source drain mask and the nanowire hard mask.
In the step 3), the diluted hydrofluoric acid solution is selected to remove the natural oxide layer, and then the silicon nitride trapping layer, the hafnium oxide trapping layer and the high-k dielectric layer are deposited in sequence, wherein the deposition method comprises but is not limited to the following steps: low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and Atomic Layer Deposition (ALD). In an embodiment of the invention, a silicon nitride trapping layer is deposited in step 3) by LPCVD, and then a hafnium oxide trapping layer and a high-k dielectric layer are sequentially deposited by ALD with good conformality. The Metal gate layer can be deposited by Physical Vapor Deposition (PVD) methods such as atomic layer deposition, Magnetron Sputtering, Metal Evaporation deposition (Metal Evaporation), and the like. The metal gate material is preferably TiN, TaN, and the like, which has low resistivity and is easily removed by dry etching.
The step 4) specifically includes:
4a) depositing silicon oxide on the metal gate layer to be used as a subsequent etching hard mask;
4b) the method comprises the steps of defining a metal gate line by an ultraviolet lithography technology, etching a silicon oxide hard mask, a metal gate layer, a high-k dielectric layer, a hafnium oxide trapping layer and a silicon nitride trapping layer to a silicon oxide layer in the field sequentially by a dry method, controlling the etching amount, ensuring that the field is completely etched, simultaneously not damaging a nano linear structure with a source-drain fan-out area, and finally finishing photoresist removing operation.
And 5) heavily doping the source and drain by an ion implantation technology, and annealing to activate source and drain impurities.
Depositing an isolation layer and flattening the surface, defining a through hole above the source drain gate by using a photoetching technology, and etching the isolation layer to the source drain gate by a dry method by using photoresist as a mask to form the through hole; depositing metal to fill the through hole and form a metal conducting layer, defining a metal leading-out wire by utilizing a photoetching technology after surface planarization, and etching the metal conducting layer to the isolating layer by a dry method by taking photoresist as a mask to form a metal leading-out wire; and finally, removing the photoresist, depositing a passivation layer and carrying out surface planarization.
Preferably, a metal adhesion layer is deposited in the via hole, and then a metal conductive layer is deposited. The metal adhesion layer can be metal Ti, Cr and the like; the metal conducting layer can be selected from metals with high hole filling rate and low resistivity, such as Al, Cu, TiN and composite metal layers thereof.
The lithography technique employed in the above method is a lithography technique capable of forming a nano-scale structure such as 193nm ultraviolet lithography.
The dry Etching techniques adopted in the above method are Reactive Ion Etching (RIE), Inductively Coupled Plasma Etching (ICPE), and the like.
The deposition techniques adopted in the above steps 4) and 6) are low-pressure chemical vapor deposition, Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.
The invention has the following advantages and positive effects:
1) the low-voltage and multifunctional nanowire type synaptic transistor without the tunneling oxide layer realizes long-time plasticity and can simulate some short-time plasticity through the design of the tunneling oxide layer-free and silicon nitride and silicon oxide double-charge trapping layer, so that the functions of the charge trapping synaptic transistor are enriched.
2) In addition, the combination of one-time programming and then changing the position of the trapped charges instead of the amount of the trapped charges and the non-tunneling oxide layer and the high-k/metal gate can help to reduce the operating voltage and the power consumption of the device.
The synaptic transistor based on the charge trapping mechanism, which has the advantages of low-voltage operation and can simulate multifunctional synaptic plasticity, is expected to be applied to future large-scale artificial neural networks.
Drawings
FIGS. 1-11 are schematic diagrams of key process steps for fabricating a low voltage and multifunctional nanowire-type synapse device without a tunneling oxide layer on an SOI substrate; in each figure, (a) is a plan view, (B) is a sectional view taken along the direction A-A ', and (c) is a sectional view taken along the direction B-B'. Wherein:
FIG. 1 illustrates a step of spin-coating HSQ electron beam resist on a P-type SOI substrate;
FIG. 2 is a schematic diagram of the definition of nanowire lines by electron beam lithography, and the conversion of exposed HSQ electron beam resist into SiO2A step of masking;
FIG. 3 is a step of spin-coating a positive photoresist;
FIG. 4 is a step of defining a source-drain bulk by an ultraviolet lithography technique and forming a nanowire with a source-drain fan-out after dry etching;
FIG. 5 is a step of removing the photoresist and the silicon oxide mask over the nanowires;
FIG. 6 is a step of sequentially depositing a silicon nitride trapping layer, a hafnium oxide trapping layer, an aluminum oxide barrier layer and a titanium nitride metal layer and a silicon oxide hard mask;
FIG. 7 is a step of etching a silicon oxide mask, a titanium nitride metal layer and a dielectric layer to a silicon oxide substrate to form a metal gate line;
FIG. 8 is a step of performing source drain doping implantation and activating source drain impurities by high temperature rapid annealing;
FIG. 9 is a step of depositing a silicon oxide isolation layer and planarizing the surface by CMP;
FIG. 10 shows a step of metal line extraction after via etching;
FIG. 11 is a step of depositing a passivation layer of silicon oxide and planarizing the surface by CMP.
Fig. 12 is an illustration of the materials used in fig. 1-11.
Detailed Description
The invention is described in detail below with reference to the figures and the specific examples.
The preparation of the low-voltage and multifunctional nanowire type synaptic transistor without the tunneling oxide layer on the SOI substrate can be realized according to the following steps, and the N type synaptic transistor is taken as an example for illustration:
1) the method is characterized in that the thickness of a surface silicon film of the SOI substrate is reduced to 40nm by adopting a mode of firstly hydrogen-oxygen synthesis oxidation and then hydrofluoric acid diluent (BOE) wet etching on a P-type SOI substrate with a (100) crystal face, and the thickness of the silicon film after reduction determines the height of a nanowire prepared later. Front side implantation BF2 +Implant energy of 33keV and implant dose of 2E12 cm-2Then activating impurities through rapid thermal annealing treatment, wherein the annealing condition is 1000 ℃ and lasts for 10 s;
2) spin coating HSQ electron beam photoresist on the front surface of the substrate as shown in FIG. 1;
3) defining nanowire lines by using an electron beam lithography technology, exposing to form a nanowire etching mask, and taking note that at the moment, after exposure, the HSQ electron beam photoresist is subjected to dehydrogenation reaction and is converted into a silicon oxide mask, the line width and the length of the nanowire are determined by a layout of the electron beam lithography, wherein the line width of the nanowire is designed to be 40nm, as shown in FIG. 2;
4) spin-coating a positive photoresist on the front side of the substrate, as shown in FIG. 3;
5) defining a source-drain region by using an ultraviolet lithography technology, forming a mixed mask with a silicon oxide hard mask above the nanowire, performing dry etching to a silicon oxide layer, and adding a proper over-etching amount, as shown in FIG. 4;
6) removing the optical photoresist above the source drain region, and then removing the silicon oxide hard mask above the nanowire by using a diluted hydrofluoric acid solution, as shown in fig. 5;
7) rinsing a natural oxide layer by using a diluted hydrofluoric acid solution, depositing a silicon nitride trapping layer with the thickness of 4nm by using LPCVD, sequentially depositing a hafnium oxide trapping layer with the thickness of 5nm and an aluminum oxide barrier layer with the thickness of 8nm by adopting ALD, sputtering a TiN metal layer with the thickness of 50nm by adopting PVD, and depositing silicon oxide with the thickness of 100nm as a subsequent etching hard mask, as shown in figure 6;
8) defining a metal gate line by an ultraviolet lithography technology, sequentially etching a silicon oxide hard mask, a titanium nitride metal layer, an aluminum oxide barrier layer, a hafnium oxide trapping layer and a silicon nitride trapping layer to a silicon oxide layer by a dry method in a field region, controlling the etching amount, ensuring that the silicon nanowire and a source drain region are not damaged when the dielectric layer is completely etched, and finally finishing photoresist removing operation, as shown in FIG. 7;
9) using silicon oxide hard mask and metal gate As implantation shielding layer to perform source-drain heavy doping As+The injection dose is 5E15 cm-2Activating source and drain impurities through rapid thermal annealing, wherein the annealing condition is 1000 ℃ and lasts for 10s, as shown in FIG. 8;
10) depositing a silicon oxide isolation layer with the thickness of 300nm, and realizing surface planarization by using CMP (chemical mechanical polishing), as shown in FIG. 9;
11) defining a through hole by a photoetching technology, etching a silicon oxide isolation layer to a source drain region by a dry method in a source drain region, etching the silicon oxide isolation layer to a gate electrode by a dry method in a gate region, depositing 10nm of metal titanium as an adhesion layer, depositing 500nm of metal aluminum as a conductive layer, and realizing surface planarization by CMP (chemical mechanical polishing), as shown in FIG. 10;
12) a 500nm thick passivation layer of silicon oxide was deposited and surface planarized as shown in fig. 11.
For the preparation of the P-type protruding transistor, an N-type SOI substrate is adopted, and the lightly doped implantation impurity of the step 1) is carried out by BF2 +Changed into As+Implanting impurity from As by the source-drain heavy doping of step 9)+Changed into BF2 +The other conditions remain unchanged.
The embodiments of the present invention are not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A nanowire type synaptic transistor without a tunneling oxide layer comprises an SOI substrate, a nanowire channel region, a source region, a drain region, a charge double trapping layer, a high-k dielectric layer and a metal gate, wherein the charge double trapping layer consists of a silicon nitride trapping layer and a hafnium oxide trapping layer; forming a source drain region and a nanowire channel region connecting the source drain region and the nanowire channel region on the SOI substrate, and sequentially forming a silicon nitride trapping layer, a hafnium oxide trapping layer, a high-k dielectric layer and a metal gate from the nanowire channel region to the outside; and forming a device isolation region between the devices in an island isolation manner, wherein the isolation layer covers the whole device and is used as a metal extraction layer.
2. The tunneling oxide-free nanowire-type synapse transistor of claim 1, wherein the nanowire channel region has a linewidth of 10-40 nm.
3. The nanowire-type synapse transistor without a tunneling oxide layer of claim 1, wherein the silicon nitride trapping layer has a thickness of 3-5 nm, and the hafnium oxide trapping layer has a thickness of 3-5 nm.
4. The nanowire-type synapse transistor without a tunneling oxide layer of claim 1, wherein the high-k dielectric layer is made of aluminum oxide or tantalum oxide with a thickness of 8-10 nm; the metal gate is made of titanium nitride, tantalum nitride, aluminum, tantalum and tungsten, and the thickness of the metal gate is 50-200 nm.
5. The method of fabricating a nanowire-type synapse transistor without a tunneling oxide layer as claimed in any of claims 1-4, comprising the steps of:
1) thinning a silicon film on the surface of the SOI substrate, determining the height of a nanowire channel region by the thickness of the thinned silicon film, carrying out light doping on the front surface, and carrying out impurity activation by rapid thermal annealing treatment;
2) patterning by utilizing a photoetching technology, and etching the silicon film to form a nanowire-type structure with source-drain large fan-out regions at two ends;
3) depositing a silicon nitride trapping layer, a hafnium oxide trapping layer, a high-k dielectric layer and a metal gate layer on the structure in the step 2) in sequence;
4) defining metal gate lines by an ultraviolet photoetching technology;
5) performing injection doping on the source region and the drain region, and annealing to activate impurities;
6) and depositing an isolation layer, flattening the surface, and then manufacturing metal lead-out of the source drain gate.
6. The method according to claim 5, wherein for the preparation of an N-type synapse transistor, a P-type SOI substrate is used in step 1) and a surface silicon film is lightly doped P-type, and a source region and a drain region are heavily doped N-type in step 9); and for the preparation of the P-type synapse transistor, an N-type SOI substrate is adopted in step 1), N-type light doping is carried out on a surface silicon film, and P-type heavy doping is carried out on a source region and a drain region in step 9).
7. The method according to claim 5, wherein the step 2) comprises:
2a) spin-coating an inorganic negative photoresist on an SOI substrate, and then patterning the inorganic negative photoresist as a nanowire hard mask by using an electron beam lithography technology;
2b) spin-coating an organic positive photoresist, and patterning the organic positive photoresist as a source-drain mask by using an ultraviolet lithography technology;
2c) the nanowire hard mask and the source-drain mask are used as a mixed mask, and the silicon film is etched by a dry method to form a nanowire type structure with source-drain large fan-out areas at two ends;
2d) and removing the source drain mask and the nanowire hard mask.
8. The method according to claim 5, wherein step 3) comprises removing the native oxide layer with a diluted hydrofluoric acid solution, depositing the silicon nitride trapping layer by low pressure chemical vapor deposition, depositing the hafnium oxide trapping layer and the high-k dielectric layer by atomic layer deposition, and depositing the metal gate layer by atomic layer deposition, magnetron sputtering or metal evaporation deposition.
9. The method according to claim 5, wherein step 4) comprises:
4a) depositing silicon oxide on the metal gate layer to be used as a subsequent etching hard mask;
4b) the method comprises the steps of defining a metal gate line by an ultraviolet lithography technology, etching a silicon oxide hard mask, a metal gate layer, a high-k dielectric layer, a hafnium oxide trapping layer and a silicon nitride trapping layer to a silicon oxide layer in the field sequentially by a dry method, controlling the etching amount, ensuring that the field is completely etched, simultaneously not damaging a nano linear structure with a source-drain fan-out area, and finally finishing photoresist removing operation.
10. The preparation method of claim 5, wherein, after the isolation layer is deposited and the surface is planarized in the step 6), a through hole above the source drain gate is defined by utilizing a photoetching technology, and the isolation layer is etched to the source drain gate by a dry method by taking photoresist as a mask to form the through hole; depositing metal to fill the through hole and form a metal conducting layer, defining a metal leading-out wire by utilizing a photoetching technology after surface planarization, and etching the metal conducting layer to the isolating layer by a dry method by taking photoresist as a mask to form a metal leading-out wire; and finally, removing the photoresist, depositing a passivation layer and carrying out surface planarization.
CN202110205069.8A 2021-02-24 2021-02-24 Nanowire type synaptic transistor without tunneling oxide layer and preparation method thereof Pending CN113013257A (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN113871486A (en) * 2021-09-27 2021-12-31 北京大学 Multi-floating-gate laminated type synaptic transistor and preparation method thereof

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US20200013800A1 (en) * 2015-10-24 2020-01-09 Monolithic 3D Inc. 3d semiconductor memory device and structure
CN111564499A (en) * 2020-05-20 2020-08-21 北京大学 Low-voltage multifunctional charge-trapping type synaptic transistor and preparation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200013800A1 (en) * 2015-10-24 2020-01-09 Monolithic 3D Inc. 3d semiconductor memory device and structure
CN111564499A (en) * 2020-05-20 2020-08-21 北京大学 Low-voltage multifunctional charge-trapping type synaptic transistor and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113871486A (en) * 2021-09-27 2021-12-31 北京大学 Multi-floating-gate laminated type synaptic transistor and preparation method thereof

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Application publication date: 20210622