CN113871527A - Laminated charge-trapping type synaptic transistor and preparation method thereof - Google Patents
Laminated charge-trapping type synaptic transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
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Abstract
The invention discloses a laminated charge trapping type synaptic transistor and a preparation method thereof.A charge trapping layer combines materials to simultaneously realize long-term simulation and short-term simulation by utilizing the characteristics of shallow defect energy level of silicon nitride and deep defect energy level of high-k oxide. Interfaces of different high-k oxide laminated layers serving as charge trapping layers are mutually permeated under a high-temperature process to generate richer interface traps, so that a storage window is improved; the materials with different forbidden band widths are circularly laminated to form a potential well, so that the synaptic weight is easier to change, and the operability is improved. The inner electric field distribution of the surrounding gate silicon nanowire structure adopted by the synapse transistor is concentrated, and the outer electric field is relatively small, so that the injection current of the device is increased during programming, the injection current of the back gate is reduced during erasing, the operation speed of the device is improved, and the operation voltage is reduced; the performance maximization can be realized by adjusting the thickness and the proportion of each layer of the charge trapping layer, and the method has the potential of being applied to future large-scale neural network computing systems.
Description
Technical Field
The invention belongs to the field of neuromorphic computing systems, provides a synapse device unit for providing a basis for neural network hardware, and particularly relates to a laminated charge-trapping type synapse transistor with low power consumption, high speed and multiple functions and a preparation method thereof.
Background
The neuromorphic computing is a novel computing mode for simulating a biological nervous system with high parallelism, high fault tolerance and low power consumption, is a novel computing architecture for realizing storage and computation integration compared with a traditional Von Neumann architecture, and shows more excellent performance. The neuromorphic computing needs to be developed from multiple aspects such as devices, circuits and system architectures, wherein the underlying synapses, nerve components and synapse networks are the basis for building a complex neuromorphic computing system.
The current artificial synapse devices include Resistive Random Access Memory (RRAM), Phase Change Memory (PCRAM), ion-Gated synapse Transistor (IGFET), and Charge-Trapped synapse Transistor (CTFET). The resistive random access memory and the phase change memory are simple in structure and can be integrated, but the problems of large fluctuation, poor reliability and the like exist; most of ion-gated synapse transistors incorporate organic materials and two-dimensional materials, and face the difficulty of CMOS circuit integration. The charge-trapping synapse transistor has the advantages of CMOS process compatibility, high-density integration and read-write separation, but the current charge-trapping synapse transistor has the challenges of incomplete function, high working voltage, insufficient operation speed and the like.
Therefore, a multifunctional, low-power, high-speed charge-trapping synaptic transistor is in urgent need of development and research.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a charge trapping type synapse transistor with multiple functions, low power consumption, and fast erasing/programming speed, and a method for fabricating the same.
Current charge-trapping synaptic transistors work based on a non-volatile charge-trapping mechanism, which can only simulate the long-term plasticity of synapses, but lack the simulation of short-term plasticity, which plays an important role in neuromorphic calculations. In addition, charges need to tunnel through a wide potential barrier during programming and erasing, the writing and erasing speed is slow, and the operating voltage is high.
The invention provides a method for using silicon nitride (Si)3N4) + different high k (high-k) The oxide stack "acts as a synaptic transistor for the charge trapping layer. Using different material trap distributions such as silicon nitride (Si)3N4) The characteristics of shallow defect level, high bulk density and deep high k oxide defect level, the material is combined to realize long-term simulation and short-term simulation of synapse devices at the same time. Furthermore, different high-k oxide laminated layers are adopted as the charge trapping layers, and interfaces of different materials are mutually permeated under a high-temperature process to generate richer interface traps, so that the storage window is improved. Further, when a high-k stack oxide is selected, a material having a large forbidden band width such as yttrium oxide (Y) is selected2O3) And materials with a slightly smaller forbidden band width but higher conductivity such as titanium dioxide (TiO)2) The cyclic stack forms a potential well, so that synaptic weights can be changed more easily, and operability is improved. In addition, the channel of a Gate-All-Around (GAA) silicon nanowire is adopted, so that the inner curvature radius of the tunneling oxide layer is small, and the electric field distribution is concentrated; the curvature radius of the outer barrier layer oxide layer is large, and the electric field is relatively small. The structure enables the injection current of the device to be increased during programming and the injection current of the back gate to be reduced during erasing, so that the operation speed of the synapse device is improved, and the operation voltage is reduced. Finally by adjusting the silicon nitride (Si)3N4) The thickness of the layers, the thickness and the proportioning of the high-k oxide stack can achieve maximum performance.
The invention provides a method for using silicon nitride (Si)3N4) The low-voltage high-speed multifunctional high-k laminated charge-trapping synapse transistor with different high-k oxide laminated layers as charge-trapping layers comprises a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a grid electrode, an isolation layer and a metal leading-out layer, wherein the semiconductor substrate is an SOI substrate, the source region, the drain region and the nanowire channel region connecting the source region and the drain region are formed on the SOI substrate, the interlayer dielectric and the grid electrode are arranged above the nanowire channel region, and the isolation layer covers the surface of a synapse transistor device; the metal lead-out layer forms metal lead-out wires connected to the source region, the drain region and the grid electrode through the through holes respectively; wherein the interlayer dielectric comprises a charge trapping layer and a blocking layer, wherein the charge trapping layer is formed from a silicon nitride layer plus a different high-k oxidationThe materials are laminated.
In the low-voltage high-speed multifunctional high-k laminated charge-trapping synapse transistor, the interlayer dielectric is composed of a tunneling oxide layer, a silicon nitride layer, different high-k oxide laminated layers and a blocking layer which are sequentially laminated from the surface of the nanowire channel region to the outside, or the tunneling oxide layer is omitted. The material of the tunneling oxide layer is preferably silicon oxide (SiO)2) And the thickness is preferably 1 to 2 nm. When the tunneling oxide layer is omitted, ultra-thin silicon nitride (Si) is required3N4) A layer having a thickness of at most 3 to 4 nm.
In the low-voltage high-speed multifunctional high-k stacked charge-trapping synapse transistor, the charge-trapping layer comprises silicon nitride (Si)3N4) A stack of layers and a high k oxide. Silicon nitride (Si)3N4) The thickness of the layer is preferably 4 to 5nm in the presence of a tunnel oxide layer. The stack of high-k oxides is preferably yttrium oxide (Y)2O3) Titanium dioxide (TiO)2) Hafnium oxide (HfO)2) Titanium dioxide (TiO)2) Zirconium oxide (ZrO)2) Titanium dioxide (TiO)2) Hafnium oxide (HfO)2) Tantalum oxide (Ta)2O5) Zirconium oxide (ZrO)2) Tantalum oxide (Ta)2O5) Yttrium oxide (Y)2O3) Praseodymium trioxide (Pr)2O3) Hafnium aluminum oxygen (HfAlO)/titanium dioxide (TiO)2) Hafnium aluminum oxygen (HfAlO)/tantalum oxide (Ta)2O5) And the thickness of the single layer is different according to different layers, preferably 1-4 nm, and the total thickness and the laminating times of the laminated layers are adjusted according to actual requirements.
In the low-voltage high-speed multifunctional high-k stacked charge-trapping synapse transistor, the material of the blocking layer is preferably aluminum oxide (Al)2O3) Silicon oxide (SiO)2) And the thickness is preferably 8 to 10 nm.
In the low-voltage high-speed multifunctional high-k stacked charge-trapping synapse transistor, the gate is preferably made of titanium nitride (TiN), tantalum nitride (TaN) or the like, and the thickness is preferably 50-100 nm.
The invention also provides a preparation method of the low-voltage high-speed multifunctional high-k laminated charge-trapping synapse transistor, which comprises the following steps:
1) patterning and etching the silicon nanowire channel region and a source region and a drain region which are respectively connected with the two ends of the silicon nanowire channel region on the SOI substrate by utilizing a photoetching technology to obtain a dumbbell-shaped silicon structure, and doping and annealing the source region and the drain region;
2) sequentially forming each interlayer medium on the dumbbell-shaped silicon structure, wherein each interlayer medium comprises a charge trapping layer and a barrier layer on the charge trapping layer;
3) depositing a metal gate material on the barrier layer, and forming a gate through photoetching definition and etching;
4) and depositing an isolation layer, flattening the surface, and then manufacturing metal lead-out of the source drain gate.
The step 1) specifically comprises:
1a) spin-coating inorganic negative photoresist such as HSQ (hydrogen silsesquioxane) electron beam photoresist containing hydrogen silicate on an SOI substrate, and patterning the inorganic negative photoresist as a nanowire hard mask by using an electron beam lithography technique;
1b) spin-coating an organic positive photoresist, and patterning the organic positive photoresist as a source-drain mask by a photoetching technology;
1c) the nanowire hard mask (inorganic glue) and the source drain mask (organic glue) are used as mixed masks, and silicon is anisotropically etched to form a dumbbell-shaped structure;
1d) and removing the source and drain masks, reserving the nanowire hard mask, heavily doping the source and drain by an ion implantation technology, then removing the nanowire hard mask by wet etching, and annealing and activating source and drain impurities.
The Annealing method may be one of Rapid Thermal Annealing (RTA), Laser Annealing (Laser Annealing), Flash Annealing (Flash Annealing), and Spike Annealing (Spike Annealing).
In the step 2), a tunneling oxide layer can be formed through an oxidation mode, and then a silicon nitride layer, a high-k oxide lamination and a barrier layer are sequentially deposited. The oxidation method may be dry oxygen oxidation or hydrogen-oxygen synthetic oxidation, and the Deposition method includes Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), and the like.
The Deposition manner of the Metal gate material in the step 3) may adopt Physical Vapor Deposition (PVD) manners such as Magnetron Sputtering (Magnetron Sputtering) and Metal Evaporation (Metal Evaporation).
The silicon oxide is preferably deposited as the isolation layer in the step 4), and the deposition mode can adopt methods such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD) and the like. The planarization is preferably Chemical Mechanical Polishing (CMP).
And 4) when the metal for manufacturing the source and drain gates is led out, defining and etching the through holes for forming the source, drain and gate by utilizing the photoetching technology, depositing metal for filling, defining the metal lead-out wire by utilizing the photoetching technology after surface planarization, and etching the metal layer to the isolation layer to form the metal lead-out.
Further, the lithography technology adopted in the above preparation method is a lithography technology capable of defining nanometer scale, such as 193nm ultraviolet lithography technology; the adopted Etching technology can be Reactive Ion Etching (RIE), Inductively Coupled Plasma Etching (ICPE) and other methods.
The invention has the following advantages and positive effects:
1) the synapse transistor using the silicon nitride + different high-k oxide laminated layers as the charge trapping layer combines materials by utilizing the characteristics of shallow defect energy level of the silicon nitride and deep defect energy level of the high-k oxide, so as to realize long-time range simulation and short-time range simulation at the same time;
2) different high-k oxide laminated layers are adopted as charge trapping layers, and interfaces of different materials are mutually permeated under a high-temperature process to generate richer interface traps, so that a storage window is improved;
3) when the high-k laminated oxide is selected, a material with a large forbidden band width and a material with a small forbidden band width and higher conductivity are selected to form a potential well in a circulating laminated mode, so that the synaptic weight is changed more easily, and the operability is improved;
4) the distribution of an inner electric field of the structure of the gate-surrounding silicon nanowire is concentrated, and an outer electric field is relatively small, so that the injection current of the device is increased during programming, the injection current of a back gate is reduced during erasing, the operation speed of the synapse device is improved, and the operation voltage is reduced;
5) performance maximization can be achieved by adjusting the thickness of the silicon nitride, the thickness of the high-k oxide stack and the ratio.
Drawings
FIGS. 1-8 are schematic diagrams of key process steps for a low voltage, high speed, multifunctional high-k stacked charge-trapping synapse transistor in accordance with the present invention. In the drawings, (a) is a top view of the device, (B) is a cross-sectional view of the device taken along the A-A 'direction, and (c) is a cross-sectional view of the device taken along the B-B' direction. Wherein:
FIG. 1 is an SOI substrate after spin-coating HSQ paste;
FIG. 2 is a diagram illustrating the definition of a nanowire mask by electron beam exposure techniques;
FIG. 3 is a diagram illustrating a dumbbell-structured source-drain and nanowire channel structure formed by defining a source-drain mask and etching the source-drain mask and a nanowire mask as a hybrid mask by using an optical lithography technique;
FIG. 4 is a schematic diagram showing the formation of a tunneling oxide layer by thermal oxidation, followed by the sequential deposition of a silicon nitride layer, a stacked high-k oxide layer (yttria/titania), an alumina barrier layer, and a titanium nitride gate electrode layer;
FIG. 5 illustrates a gate electrode defined using photolithography and etched to form a gate electrode to a barrier alumina layer;
FIG. 6 is a deposition of a silicon oxide isolation layer;
FIG. 7 is a through hole etched to a source drain silicon interface and a gate electrode surface;
FIG. 8 is a metal layer deposited, planarized, and patterned to form metal leads.
Fig. 9 is an illustration of the materials used in fig. 1-8.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples.
As shown in fig. 1 to 8, a high-k stacked charge-trapping type synapse transistor is prepared according to the following steps:
1) thinning a silicon film of an SOI substrate, oxidizing a surface silicon film into a silicon oxide film by dry oxygen oxidation or hydrogen-oxygen synthesis, rinsing the surface silicon oxide film by using a hydrofluoric acid solution, and spin-coating HSQ glue as shown in figure 1;
2) defining a nanowire mask by using an electron beam lithography technology, wherein the width of the nanowire mask is the line width of a subsequently formed silicon nanowire channel, as shown in fig. 2;
3) defining a source-drain mask by utilizing a photoetching technology, forming a mixed exposure mask with a dumbbell-shaped structure together with an inorganic hard mask above the nanowire, and then etching by a dry method to form the dumbbell-shaped silicon structure, wherein the mixed exposure mask is shown in figure 3; and removing the organic mask above the source and drain, reserving the inorganic hard mask above the silicon nanowire, heavily doping the source and drain by an ion implantation technology, removing the inorganic hard mask by wet etching, and activating source and drain impurities by rapid thermal annealing.
4) Generating a tunneling Layer silicon oxide film with the thickness of 2nm on the surface of a silicon nanowire channel through thermal oxidation, then depositing a silicon nitride film with the thickness of 4nm by using a Low Pressure Chemical Vapor Deposition (LPCVD) technology, circularly depositing a single Layer of yttrium oxide/titanium dioxide Layer with the thickness of 2nm and an aluminum oxide barrier Layer with the thickness of 8nm through an Atomic Layer Deposition (ALD) technology, and finally depositing a titanium nitride metal Layer with the thickness of 100nm by using a Magnetron Sputtering (Magnetron Sputtering) technology, as shown in FIG. 4;
5) defining a gate electrode by using a photolithography technique, Etching a titanium nitride layer to a top aluminum oxide layer by using an Inductively Coupled Plasma Etching (ICPE) with a photoresist as a mask, and performing appropriate over-Etching on the aluminum oxide layer to prevent a metal short circuit, as shown in fig. 5;
6) a 200nm thick silicon oxide isolation layer was deposited by low pressure chemical vapor deposition and surface planarized by Chemical Mechanical Polishing (CMP), as shown in fig. 6;
7) defining a through hole above a source drain gate by using a photoetching technology, etching the silicon oxide isolation layer, the barrier layer, the charge trapping layer and the tunneling layer in the source drain through hole by using a photoresist as a mask and a dry etching technology, and etching the silicon oxide isolation layer in the gate through hole, as shown in FIG. 7;
8) depositing metal titanium (adhesion layer) and metal aluminum in sequence by magnetron sputtering to fill the through hole and form a metal film, performing surface planarization by Chemical Mechanical Polishing (CMP), defining a metal lead-out wire by using a photolithography technique, and etching the metal layer to the silicon oxide isolation layer by using ICP, as shown in fig. 8.
The embodiments of the present invention are not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A laminated charge-trapping synapse transistor comprises a semiconductor substrate, a nanowire channel region, a source region, a drain region, an interlayer dielectric, a grid electrode, an isolation layer and a metal leading-out layer, wherein the semiconductor substrate is an SOI substrate, the source region, the drain region and the nanowire channel region connecting the source region and the drain region are formed on the SOI substrate, the interlayer dielectric and the grid electrode are arranged above the nanowire channel region, and the isolation layer covers the surface of the synapse transistor device; the metal lead-out layer forms metal lead-out wires connected to the source region, the drain region and the grid electrode through the through holes respectively; wherein the interlayer dielectric comprises a charge trapping layer and a blocking layer, wherein the charge trapping layer is comprised of a silicon nitride layer plus a stack of different high-k oxides.
2. The stacked charge-trapping synapse transistor of claim 1, wherein the interlayer dielectric comprises a tunneling oxide layer, a silicon nitride layer, a stack of different high-k oxides, and a blocking layer sequentially stacked from the surface of the nanowire channel region to the outside, wherein the silicon nitride layer has a thickness of 4-5 nm; or the interlayer medium is composed of a silicon nitride layer, a different high-k oxide lamination layer and a barrier layer which are sequentially laminated from the surface of the nanowire channel region to the outside, wherein the thickness of the silicon nitride layer is not more than 4 nm.
3. The stacked charge-trapping synapse transistor of claim 2, wherein the tunneling oxide layer is silicon oxide and has a thickness of 1-2 nm.
4. The stacked charge-trapping synapse transistor of claim 1, wherein the different high-k oxide stack is Y2O3/TiO2、HfO2/TiO2、ZrO2/TiO2、HfO2/Ta2O5、ZrO2/Ta2O5、Y2O3/Pr2O3、HfAlO/TiO2Or HfAlO/Ta2O5Combined alternating stacks.
5. The stacked charge-trapping synapse transistor of claim 1, wherein a thickness of a single layer in the stack of different high-k oxides is in a range of 1-4 nm.
6. The stacked charge-trapping synapse transistor of claim 1, wherein the blocking layer is made of alumina or silica with a thickness of 8-10 nm; the grid electrode is made of titanium nitride or tantalum nitride and has a thickness of 50-100 nm.
7. A method for fabricating a stacked charge-trapping synapse transistor as claimed in any of claims 1-6, comprising:
1) patterning and etching the silicon nanowire channel region and a source region and a drain region which are respectively connected with the two ends of the silicon nanowire channel region on the SOI substrate by utilizing a photoetching technology to obtain a dumbbell-shaped silicon structure, and doping and annealing the source region and the drain region;
2) sequentially forming each interlayer medium on the dumbbell-shaped silicon structure, wherein each interlayer medium comprises a charge trapping layer and a barrier layer on the charge trapping layer;
3) depositing a metal gate material on the barrier layer, and forming a gate through photoetching definition and etching;
4) and depositing an isolation layer, flattening the surface, and then manufacturing metal lead-out of the source drain gate.
8. The method of claim 7, wherein step 1) comprises:
1a) spin-coating an inorganic negative photoresist on an SOI substrate, and then patterning the inorganic negative photoresist as a nanowire hard mask by using an electron beam lithography technology;
1b) spin-coating an organic positive photoresist, and patterning the organic positive photoresist as a source-drain mask by a photoetching technology;
1c) the nanowire hard mask and the source drain mask are used as mixed masks, and the silicon is anisotropically etched to form a dumbbell-shaped structure;
1d) and removing the source and drain masks, reserving the nanowire hard mask, heavily doping the source and drain by an ion implantation technology, then removing the nanowire hard mask by wet etching, and annealing and activating source and drain impurities.
9. The method of claim 7, wherein the tunneling oxide layer is formed by oxidation in step 2), and then the silicon nitride layer, the high-k oxide stack and the barrier layer are sequentially deposited; wherein the deposition method is selected from low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition and atomic layer deposition.
10. The preparation method of claim 7, wherein in the step 4), when the metal for manufacturing the source and drain gates is led out, the photolithographic technique is used for defining and etching to form through holes of the source, the drain and the gate, then metal is deposited for filling, the photolithographic technique is used for defining the metal lead-out wire after surface planarization is carried out, and the metal layer is etched to the isolation layer to form the metal lead-out wire.
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