KR101851567B1 - Transistor, electronic device including transistor and manufacturing methods thereof - Google Patents

Transistor, electronic device including transistor and manufacturing methods thereof Download PDF

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KR101851567B1
KR101851567B1 KR1020110066130A KR20110066130A KR101851567B1 KR 101851567 B1 KR101851567 B1 KR 101851567B1 KR 1020110066130 A KR1020110066130 A KR 1020110066130A KR 20110066130 A KR20110066130 A KR 20110066130A KR 101851567 B1 KR101851567 B1 KR 101851567B1
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South Korea
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layer
oxide semiconductor
semiconductor layer
transistor
method
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KR1020110066130A
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Korean (ko)
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KR20130004836A (en
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전상훈
송이헌
안승언
김창정
김영
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삼성전자주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14609Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor

Abstract

Electronic devices including transistors, transistors, and a method of manufacturing the same. The disclosed transistor may include a plurality of oxide semiconductor layers and an active layer having an insulating layer therebetween. The insulating layer may include a material having a high etch selectivity with respect to at least one of the plurality of oxide semiconductor layers. The disclosed electronic device may include the above-described transistor (first transistor) and another transistor (second transistor) connected thereto. The second transistor may include an active layer of a different structure from the active layer of the first transistor. The active layer of the second transistor may have the same structure as any one of the plurality of oxide semiconductor layers constituting the active layer of the first transistor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a transistor, an electronic device including the transistor,

A transistor, and an electronic device including the transistor, and a method of manufacturing the same.

Transistors are widely used in various electronic devices for various purposes. For example, the transistor may be used as a switching device, a driving device, and a photo sensing device, and may be used as a component of various electronic circuits.

The characteristics of the transistor can be greatly changed depending on the material, configuration, and the like of the channel layer. That is, the material and configuration of the channel layer may be an important factor in determining the characteristics of the transistor. Recently, a method of applying an oxide semiconductor layer having a high carrier mobility as a channel layer has been attempted to improve the operational characteristics of the transistor.

However, since the transistor (oxide transistor) having the oxide semiconductor layer as a channel layer has low sensitivity to light, application to an optical element (for example, an optical sensor or the like) may not be easy.

A transistor including a plurality of oxide semiconductor layers and easy to manufacture, and an electronic device using the transistor are provided. A transistor which is excellent in light sensing characteristics and can be manufactured by a relatively simple process and an electronic device including the same are provided.

There is provided an electronic device including a plurality of transistors having different active structures.

And a method of manufacturing the transistor and the electronic device.

According to an aspect of the present invention, there is provided an active layer including a first oxide semiconductor layer, a second oxide semiconductor layer, and an insulating layer provided therebetween; A source and a drain respectively contacting both ends of the active layer; A gate corresponding to the active layer; And a gate insulating layer provided between the active layer and the gate.

The insulating layer may include a material having an etch selectivity of at least 2 with respect to at least one of the first and second oxide semiconductor layers.

The insulating layer may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

The insulating layer may be a silicon oxide layer.

And the first oxide semiconductor layer, the insulating layer, and the second oxide semiconductor layer may be sequentially formed from the gate side.

The second oxide semiconductor layer may include a material having higher sensitivity than the first oxide semiconductor layer.

The second oxide semiconductor layer may include a material having an energy band gap smaller than that of the first oxide semiconductor layer.

The threshold voltage of the transistor may be increased by the first oxide semiconductor layer.

The first oxide semiconductor layer may include at least one of MInZnO, MZnO, MAlO, and MSnO, where M may be a metal element.

The M may be any one of Ga, Hf, Ti, Ta, Zr and Ln.

The first oxide semiconductor layer may be, for example, a GaInZnO layer or an HfInZnO layer.

The second oxide semiconductor layer may include at least one of InZnO, InO, and ZnO.

The second oxide semiconductor layer may be, for example, an InZnO layer.

An etch stop layer may be provided on the active layer.

The gate may be provided under the active layer.

The gate may be provided on the active layer.

According to another aspect of the present invention, there is provided an electronic device including the transistor described above.

According to another aspect of the present invention, there is provided a light sensing circuit comprising the above-described transistor.

The transistor may be an optical sensor transistor of the photo sensing circuit.

The photo sensing circuit may further include a switching transistor coupled to the photo sensor transistor.

The switching transistor may comprise a single layer active layer.

The active layer of the switching transistor may be formed of the same material as the first oxide semiconductor layer.

According to another aspect of the present invention, there is provided an electronic device including the photo sensing circuit described above.

According to another aspect of the present invention, there is provided a semiconductor device including: a first transistor including a first active layer, a first gate, a first source, and a first drain; And a second transistor coupled to the first transistor, the second transistor including a second active layer, a second gate, a second source, and a second drain, wherein the first active layer is sequentially Wherein the first active layer includes a first oxide semiconductor layer, an insulating layer and a second oxide semiconductor layer, and the second active layer has a structure different from that of the first active layer.

The insulating layer may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

The second oxide semiconductor layer may include a material having higher sensitivity than the first oxide semiconductor layer.

The first oxide semiconductor layer may include at least one of MInZnO, MZnO, MAlO, and MSnO, and M may be any one of Ga, Hf, Ti, Ta, Zr, and Ln.

The second oxide semiconductor layer may include at least one of InZnO, InO, and ZnO.

The second active layer may have a single-layer structure.

The second active layer may be formed of the same material as the first oxide semiconductor layer.

The first and second transistors may form a light sensing circuit.

The first transistor may be an optical sensor transistor, and the second transistor may be a switching transistor.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming first and second gates on a substrate; Forming a gate insulating layer covering the first and second gates; Sequentially forming a first oxide semiconductor layer, an insulating layer, and a second oxide semiconductor layer on the gate insulating layer; Forming a first mask layer on the second oxide semiconductor layer above the first gate; Etching the second oxide semiconductor layer and the insulating layer using the first mask layer as an etch barrier; Removing the first mask layer; A first active region including the first oxide semiconductor layer, an insulating layer and a second oxide semiconductor layer is defined on the first gate, and a second active region including the first oxide semiconductor layer is formed on the second gate, Defining; And forming a first source and a first drain in contact with the first active region and forming a second source and a second drain in contact with the second active region, do.

The insulating layer may be formed of a material having an etching selection ratio of 2 or more with respect to the first oxide semiconductor layer.

The insulating layer may be formed of at least one of silicon oxide, silicon oxynitride, and silicon nitride.

The second oxide semiconductor layer may include a material having higher sensitivity than the first oxide semiconductor layer.

The first oxide semiconductor layer may include at least one of MInZnO, MZnO, MAlO, and MSnO, where M may be any one of Ga, Hf, Ti, Ta, Zr, and Ln.

The second oxide semiconductor layer may include at least one of InZnO, InO, and ZnO.

And forming an etch stop layer on the first and second active regions.

The first gate, the first active region, the first source and the first drain may constitute an optical sensor transistor, and the second gate, the second active region, the second source and the second drain may constitute a switching transistor .

A transistor including a plurality of oxide semiconductor layers and an electronic device using the transistor can be realized. A transistor having excellent light sensing characteristics and an electronic device using the same can be realized. A transistor having excellent operation characteristics and high reliability and an electronic device using the transistor can be realized.

The transistor and the electronic device can be easily manufactured by a relatively simple process.

1 to 3 are cross-sectional views illustrating a transistor according to an embodiment of the present invention.
4 is a graph illustrating an energy band diagram of an active layer and a gate insulating layer of a transistor according to an embodiment of the present invention.
5 is a cross-sectional view showing an electronic device (light sensing circuit) including a transistor according to an embodiment of the present invention.
6 is a circuit diagram showing an exemplary circuit configuration of the electronic device (light sensing circuit) of Fig.
7 is a cross-sectional view showing a part of an electronic device (flat panel display) including a transistor according to an embodiment of the present invention.
8 is a cross-sectional view showing a part of an electronic device (flat panel display) including a transistor according to another embodiment of the present invention.
9A to 9H are cross-sectional views illustrating a method of manufacturing an electronic device (light sensing circuit) including a transistor according to an embodiment of the present invention.
10 is a graph illustrating the sensitivity of the first transistor of FIG. 9H to light.
11 is a graph illustrating the sensitivity of the second transistor of FIG. 9H to light.
12 and 13 are cross-sectional views illustrating a transistor according to another embodiment of the present invention.
14 and 15 are sectional views showing an electronic device (light sensing circuit) including a transistor according to another embodiment of the present invention.
16A to 16H are cross-sectional views illustrating a method of manufacturing an electronic device (light sensing circuit) including a transistor according to another embodiment of the present invention.
Description of the Related Art [0002]
10, 11: first oxide semiconductor layer 20, 22: insulating layer
30, 33: second oxide semiconductor layers A1 to A3, A10, A20: active layer
D1 to D3, D10, D20: drain electrode DL1: data line
ES1 to ES3, ES10 and ES20: etch stop layers G1 to G3, G10 and G20:
GI1, GI10: Gate insulating layers GL1, GL2: Gate lines
P1, P10: passivation layers S1 to S3, S10, S20: source electrode
SUB1, SUB10: Substrates Tr1 to Tr3, Tr10, Tr20:
Vdd: Power line

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an electronic device including a transistor, a transistor, and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The widths and thicknesses of the layers or regions illustrated in the accompanying drawings are exaggeratedly shown for clarity of the description. Like reference numerals designate like elements throughout the specification.

1 shows a transistor according to an embodiment of the present invention. The transistor of the present embodiment is a transistor having a bottom gate structure in which a gate G1 is provided below the active layer A1.

Referring to FIG. 1, a gate G1 may be provided on a substrate SUB1. The substrate SUB1 may be a glass substrate, but may be any of other substrates such as a plastic substrate or a silicon substrate and various substrates used in a general semiconductor device process. The gate G1 may be formed of a general electrode material (metal, conductive oxide, etc.). For example, the gate G1 may be formed of a metal material such as Mo, Cu, Ti, Al, Ni, W, Pt or Cr, or a conductive oxide such as indium zinc oxide (IZO) or indium tin oxide , Or may be formed of a material alloyed with two or more kinds of metals. The gate G1 may have a single-layer structure or may have a multi-layer structure including a plurality of different material layers. A gate insulating layer GI1 covering the gate G1 may be provided on the substrate SUB1. The gate insulating layer GI1 may be a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, but may be a layer of another material, for example, a high dielectric constant material having a dielectric constant larger than that of a silicon nitride layer. The gate insulating layer GI1 may have a structure in which at least two layers of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a high-dielectric material layer are stacked.

An active layer A1 may be provided on the gate insulating layer GI1. The active layer A1 may be located above the gate G1. The active layer A1 may include an oxide semiconductor, and may have a multi-layer structure. For example, the active layer A1 may include a first oxide semiconductor layer 10, an insulating layer 20, and a second oxide semiconductor layer 30 which are sequentially stacked. The active layer A1 will be described later in more detail.

A source electrode S1 and a drain electrode D1 which are in contact with both ends of the active layer A1 may be provided on the gate insulating layer GI1. The source electrode S1 and the drain electrode D1 may be a single layer or a multilayer. The source electrode S1 and the drain electrode D1 may be the same material layer as the gate G1, but they may be different material layers. A passivation layer P1 covering the active layer A1, the source electrode S1 and the drain electrode D1 may be provided on the gate insulating layer GI1. The passivation layer P1 may be, for example, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer or an organic insulating layer, or a structure in which at least two or more of these layers are laminated.

Hereinafter, the active layer A1 will be described in more detail.

In the active layer A1, the first oxide semiconductor layer 10 is closer to the gate G1 than the second oxide semiconductor layer 30 and can act as a main channel layer. The first oxide semiconductor layer 10 may include a material having a higher energy bandgap than the second oxide semiconductor layer 30 (oxide semiconductor). The carrier concentration of the first oxide semiconductor layer 10 may be lower than the carrier concentration of the second oxide semiconductor layer 30. The first oxide semiconductor layer 10 may serve to increase the threshold voltage of the transistor. If there is no first oxide semiconductor layer 10, the threshold voltage of the transistor can be excessively lowered. The first oxide semiconductor layer 10 may include at least one of MInZnO, MZnO, MAlO, and MSnO, for example, where M may be a metal element. The M may be any one of Ga, Hf, Ti, Ta, Zr and Ln. As a specific example, the first oxide semiconductor layer 10 may be a GaInZnO layer, an HfInZnO layer, or the like. The oxide semiconductor constituting the first oxide semiconductor layer 10 may be amorphous or crystalline, or may have a crystal structure in which amorphous and crystalline are mixed. The material of the first oxide semiconductor layer 10 is not limited to those described above, and may be variously changed. The thickness of the first oxide semiconductor layer 10 may be, for example, about 10 to 100 nm. However, the thickness of the first oxide semiconductor layer 10 may vary depending on the material of the first oxide semiconductor layer 10.

The second oxide semiconductor layer 30 may be a layer having higher sensitivity to light than the first oxide semiconductor layer 10. The sensitivity of the material to light, i.e., photosensitivity, may be related to the energy bandgap. For example, the smaller the energy bandgap, the greater the light sensitivity. Accordingly, the second oxide semiconductor layer 30 may include a material having a smaller energy band gap than the first oxide semiconductor layer 10. [ The light sensitivity may also be related to the carrier concentration. For example, the higher the carrier concentration of a material, the greater the photosensitivity. Accordingly, the second oxide semiconductor layer 30 may include a material having a carrier concentration higher than that of the first oxide semiconductor layer 10. The second oxide semiconductor layer 30 may be referred to as a " photosensor layer ". The second oxide semiconductor layer 30 may include at least one of InZnO, InO, and ZnO, for example. As a specific example, the second oxide semiconductor layer 30 may be an InZnO layer, an InO layer, or a ZnO layer. The material of the second oxide semiconductor layer 30 is not limited to those described above, and may be variously changed. The thickness of the second oxide semiconductor layer 30 may be, for example, about 10 to 200 nm. The appropriate thickness of the second oxide semiconductor layer 30 may vary depending on the material of the second oxide semiconductor layer 30.

The insulating layer 20 provided between the first oxide semiconductor layer 10 and the second oxide semiconductor layer 30 is etched with respect to at least one of the first oxide semiconductor layer 10 and the second oxide semiconductor layer 30, And may include materials with high etch selectivity. For example, the insulating layer 20 may have an etch selectivity of at least 2 with respect to the first oxide semiconductor layer 10. This means that the etching rate of the insulating layer 20 can be at least two times faster than the etching rate of the first oxide semiconductor layer 10. The etching selection ratio of the insulating layer 20 to the first oxide semiconductor layer 10 may be several tens to several hundreds. That is, the etching rate of the insulating layer 20 may be several tens to several hundred times faster than the etching rate of the first oxide semiconductor layer 10. The insulating layer 20 may include at least one of silicon oxide, silicon oxynitride, and silicon nitride, for example. As a specific example, the insulating layer 20 may be a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The thickness of the insulating layer 20 may be about 10 to 200 nm, but this is illustrative and may vary.

As described above, in the embodiment of the present invention, by using the active layer A1 including a plurality of oxide semiconductor layers 10 and 30, the operation characteristics (threshold voltage and the like) of the transistor are appropriately controlled, The photosensitivity of the photoresist layer can be increased. By using such a transistor, an electronic device, for example, a photo sensing device having excellent operation characteristics and photo-sensing characteristics can be realized.

The structure of Fig. 1 can be modified in various ways. For example, the shape of the active layer A1 is not limited to that shown in the drawings, and may be variously modified. 1, the first oxide semiconductor layer 10 has a structure extending to the ends of the source electrode S1 and the drain electrode D1, but this structure is exemplary and can be modified. An example in which the shape of the first oxide semiconductor layer 10 is modified in FIG. 1 is shown in FIG.

Referring to FIG. 2, both ends of the first oxide semiconductor layer 10 'in the active layer A1' may not extend to the ends of the source electrode S1 'and the drain electrode D1'. In this case, the source electrode S1 'and the drain electrode D1' may completely cover both side surfaces of the first oxide semiconductor layer 10 '. The remaining structure except for the shapes of the first oxide semiconductor layer 10 ', the source electrode S1' and the drain electrode D1 'may be the same as that of FIG.

According to another embodiment of the present invention, the transistor of FIG. 1 may further include an etch stop layer provided on the active layer Al. An example thereof is shown in Fig.

Referring to FIG. 3, an etch stop layer ES1 may be further provided on the active layer A1. The width of the etch stop layer ES1 may be smaller than that of the active layer A1. Both ends of the active layer A1 may not be covered with the etch stop layer ES1. The source electrode S1 may cover one end of the etch stop layer ES1 and one end of the active layer A1 and the drain electrode D1 may cover the other end of the etch stop layer ES1 and the other end of the active layer A1 Can be covered. The etch stop layer ES1 may serve to prevent the active layer A1 from being damaged by the etching in the etching process for forming the source electrode S1 and the drain electrode D1. The etch stop layer ES1 may include, for example, silicon oxide, silicon nitride, organic insulator, or the like. Whether or not the etch stop layer ES1 is used can be determined depending on the material of the active layer A1 and the materials of the source electrode S1 and the drain electrode D1. The structure of FIG. 3 may be the same as that of FIG. 1, except that the etch stop layer ES1 is provided.

Fig. 4 shows an energy band diagram of the active layer A1 and the gate insulating layer GI1 in the structure of Fig. 1 by way of example. At this time, the first oxide semiconductor layer 10, an active layer (A1), an insulating layer 20 and the second oxide semiconductor layer 30, respectively GaInZnO layer, was a SiO 2 layer and the InZnO layer, a gate insulating layer (GI1) Was a structure in which a SiNx layer and an SiO 2 layer were laminated. In FIG. 4, reference symbols E C and E V denote the lowest energy level of the conduction band and the highest energy level of the valence band, respectively. On the other hand, reference symbol E F denotes the Fermi energy level of the gate.

Referring to FIG. 4, it can be seen that the energy band gap of the second oxide semiconductor layer 30 in the active layer Al is somewhat smaller than the energy band gap of the first oxide semiconductor layer 10. It can be seen that the insulating layer 20 having a larger energy bandgap is sandwiched between the first oxide semiconductor layer 10 and the second oxide semiconductor layer 30.

The transistor according to the embodiment of the present invention can be applied to various electronic devices. For example, a transistor according to an embodiment of the present invention may be applied to an optical sensor transistor of a photo sensing circuit. In this case, the sensing performance, the operation characteristics, the reliability, and the like of the light sensing circuit can be improved. The photo sensing circuit may further include a switching element connected to the photo sensor transistor. The switching element may be, for example, a switching transistor. A photo sensor array in which a plurality of unit circuits including the photosensor transistor and a switching transistor connected thereto is arranged can be manufactured and applied to a flat panel display device. In this case, a flat panel display device which can be operated remotely by using external light can be realized. The transistor according to an exemplary embodiment of the present invention can be applied to various electronic devices in addition to the photo sensing circuit, the photo sensor array, and the flat panel display device for various purposes.

5 is a cross-sectional view showing an electronic device (light sensing circuit) including a transistor according to an embodiment of the present invention.

Referring to FIG. 5, an electronic device (light sensing circuit) according to an embodiment of the present invention may include an optical sensor transistor Tr1 and a switching transistor Tr2. The photo sensor transistor Tr1 may have the same (or similar) configuration as the transistor of FIG. More specifically, the photosensor transistor Tr1 includes a first gate G1, a gate insulating layer GI1, a first active layer A1, a first source electrode S1, and a first drain electrode D1. . ≪ / RTI > The first active layer Al may include a first oxide semiconductor layer 10, an insulating layer 20, and a second oxide semiconductor layer 30. The first gate G1, the gate insulating layer GI1, the first active layer A1, the first source electrode S1 and the first drain electrode D1 are connected to the gate G1, The source electrode GI1, the active layer A1, the source electrode S1, and the drain electrode D1. The switching transistor Tr2 may have a different configuration from the optical sensor transistor Tr1. The active layer (hereinafter, the second active layer) A2 of the switching transistor Tr2 may have a different structure from the first active layer A1 of the photosensor transistor Tr1. For example, the second active layer A2 may have the same configuration as the first oxide semiconductor layer 10 of the first active layer A1. When the first oxide semiconductor layer 10 has a single-layer structure, the second active layer A2 may have a single-layer structure. If the first oxide semiconductor layer 10 has a multilayer structure, the second active layer A2 may have a multilayer structure. Since the switching transistor Tr2 is responsible for the switching function instead of the optical sensing, the optical sensor layer, that is, the second oxide semiconductor layer 30 is not used. In the case of this switching transistor Tr2, there is almost no characteristic variation due to light. The materials and configurations of the second gate G2, the second source electrode S2 and the second drain electrode D2 of the switching transistor Tr2 are respectively the first gate G1 and the first source electrode S1, And the first drain electrode D1. The gate insulating layer GI1 can be commonly used in the photosensor transistor Tr1 and the switching transistor Tr2. The passivation layer P1 covering the photosensor transistor Tr1 and the switching transistor Tr2 may be the same as or similar to the passivation layer P1 in Fig.

6 is a circuit diagram showing an exemplary circuit configuration of the electronic device (light sensing circuit) of Fig. In other words, Fig. 6 is a circuit diagram showing an exemplary unit circuit configuration of the optical sensor array according to the embodiment of the present invention.

Referring to FIG. 6, the first gate line GL1 and the second gate line GL2 may be provided in parallel with each other. The data line DL1 and the power source line Vdd may be provided so as to intersect the first gate line GL1 and the second gate line GL2. The unit circuit may include an optical sensor transistor Tr1 and a switching transistor Tr2 connected thereto. The photo sensor transistor Tr1 and the switching transistor Tr2 may have the same (or similar) structure as the photo sensor transistor Tr1 and the switching transistor Tr2 in Fig. 5, respectively. The photosensor transistor Tr1 may be connected between the second gate line GL2 and the power source line Vdd. The switching transistor Tr2 may be connected between the first gate line GL1 and the data line DL1. When a predetermined light is irradiated on the photosensor transistor Tr1, photocurrent may be generated in the photosensor transistor Tr1. At this time, if the switching transistor Tr2 is turned on, data can be output through the photosensor transistor Tr1 and the switching transistor Tr2. The circuit configuration of Fig. 6 is merely an example and can be modified in various ways. Further, a plurality of circuits shown in Fig. 6 may be arranged to constitute an optical sensor array, and such optical sensor array may be applied to a flat panel display device or the like.

7 is a cross-sectional view showing a part of an electronic device (flat panel display) including a transistor according to an embodiment of the present invention.

Referring to Fig. 7, the electronic device (flat panel display device) of this embodiment may include a photo sensing circuit and a switch Tr3 for display. The photo sensing circuit may include the photosensor transistor Tr1 and the switching transistor Tr2 described with reference to FIG. 5 and FIG. On the other hand, the display switch Tr3 formed in the display region may have the same (or similar) structure as the switching transistor Tr2. The display switch Tr3 may include a third gate G3, a gate insulating layer GI1, a third active layer A3, a third source electrode S3, and a third drain electrode D3. The materials and configurations of the third gate G3, the gate insulating layer GI1, the third active layer A3, the third source electrode S3 and the third drain electrode D3 are the second gate G2, It may be the same as that of the gate insulating layer GI1, the second active layer A2, the second source electrode S2 and the second drain electrode D2. As described above, since the display switch Tr3 can be formed in the same (or similar) structure as the switching transistor Tr2, the burden on the process for forming the additional display switch Tr3 may not occur. Although not shown, a pixel electrode connected to the display switch Tr3 may be further provided. The configuration of the display area is well known to those skilled in the art, and a detailed description thereof will be omitted.

According to another embodiment of the present invention, an etch stop layer may further be provided on the first to third active layers A1, A2 and A3 of FIG. An example thereof is shown in Fig. In FIG. 8, the first to third etch stop layers ES1, ES2 and ES3 are for the photosensor transistor Tr1 ', the switching transistor Tr2' and the display switch Tr3 ', respectively.

9A to 9H are cross-sectional views illustrating a method of manufacturing an electronic device (light sensing circuit) including a transistor according to an embodiment of the present invention.

Referring to FIG. 9A, a first gate G10 and a second gate G20 may be formed on a substrate SUB10. The substrate SUB10 may be a glass substrate, but may be any of various substrates such as a plastic substrate or a silicon substrate used in a general semiconductor device process. The first and second gates G10 and G20 may be formed of a common electrode material (metal, conductive oxide, etc.). For example, the first and second gates G10 and G20 may be formed of a metal material such as Mo, Cu, Ti, Al, Ni, W, Pt, Cr, or a conductive oxide such as IZO or ITO. Or more of a metal alloy. The first and second gates G10 and G20 may have a single-layer structure or may have a multi-layer structure including a plurality of different material layers. A gate insulating layer GI10 covering the first and second gates G10 and G20 may be formed on the substrate SUB10. The gate insulating layer GI10 may be formed of silicon oxide, silicon oxynitride, silicon nitride, or another material, for example, a high dielectric constant material having a dielectric constant higher than that of silicon nitride. The gate insulating layer GI1 may have a structure in which at least two layers of a silicon oxide layer, a silicon oxynitride, a silicon nitride layer, and a high-dielectric material layer are stacked.

Referring to FIG. 9B, the first oxide semiconductor layer 11, the insulating layer 22, and the second oxide semiconductor layer 33 may be sequentially formed on the gate insulating layer GI10. The materials of the first oxide semiconductor layer 11, the insulating layer 22 and the second oxide semiconductor layer 33 are the same as those of the first oxide semiconductor layer 10, the insulating layer 20, (30). ≪ / RTI > That is, the first oxide semiconductor layer 11 may include at least one of MInZnO, MZnO, MAlO, and MSnO, where M may be a metal element. The M may be any one of Ga, Hf, Ti, Ta, Zr and Ln. As a specific example, the first oxide semiconductor layer 11 may be a GaInZnO layer, an HfInZnO layer, or the like. The second oxide semiconductor layer 33 may include at least one of InZnO, InO, and ZnO, for example. As a specific example, the second oxide semiconductor layer 30 may be an InZnO layer, an InO layer, a ZnO layer, or the like. The insulating layer 22 may include a material having a high etch selectivity with respect to at least one of the first oxide semiconductor layer 11 and the second oxide semiconductor layer 33. For example, the insulating layer 22 may have an etching selectivity ratio of 2 or more with respect to the first oxide semiconductor layer 11. Since the etch selectivity means the ratio of the etch rate, the etch rate of the insulating layer 22 may be at least twice as fast as the etch rate of the first oxide semiconductor layer 11 with respect to the predetermined etch gas. The insulating layer 22 may comprise at least one of, for example, silicon oxide, silicon oxynitride, and silicon nitride. When the insulating layer 22 is a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, the etching selectivity of the insulating layer 22 to the first oxide semiconductor layer 11 may be as high as several tens to several hundreds. The thicknesses of the first oxide semiconductor layer 11, the insulating layer 22, and the second oxide semiconductor layer 33 may be about 10 to 100 nm, 10 to 200 nm, and 10 to 200 nm, respectively. However, such thickness ranges are exemplary and may vary.

Next, a first mask pattern M10 may be formed on the second oxide semiconductor layer 33 above the first gate G10. The first mask pattern M10 may be, for example, a photoresist layer.

Referring to FIG. 9C, the second oxide semiconductor layer 33 and the insulating layer 22 may be sequentially etched by using the first mask pattern M10 as an etching barrier. In etching the insulating layer 22, for example, etching gas containing CHF 3 can be used. The etching gas may further include O 2 and Ar. The etching gas of the insulating layer 22 disclosed here is illustrative and can be varied in various ways. When the insulating layer 22 is etched, the first oxide semiconductor layer 11 can act as an etch stop layer. This is because the first oxide semiconductor layer 11 may have a very low etch selectivity with respect to the insulating layer 22. Therefore, the insulating layer 22 can be selectively etched without substantially damaging the first oxide semiconductor layer 11.

If the insulating layer 22 is an oxide semiconductor layer (hereinafter referred to as "intermediate oxide semiconductor layer") similar to the first oxide semiconductor layer 11, selective etching as shown in FIG. 9C may be difficult. That is, since the etching selectivity between the first oxide semiconductor layer 11 and the "intermediate oxide semiconductor layer" is substantially zero, the first oxide semiconductor layer 11 is damaged / It is very likely to be lost. As described above, the use of the oxide semiconductor layer (the "intermediate oxide semiconductor layer") in place of the insulating layer 22 may be disadvantageous in terms of process. However, when the insulating layer 22 having a large etch selectivity relative to the first oxide semiconductor layer 11 is used as in the embodiment of the present invention, the first oxide semiconductor layer 11 is not damaged Only the insulating layer 22 can be easily etched. Therefore, the manufacturing process becomes easy, and it can be advantageous in securing the reproducibility of the device and improving the characteristics.

9D, an etch stop material layer ES150 covering the first oxide semiconductor layer 11, the insulating layer 22, and the second oxide semiconductor layer 33, with the first mask pattern M10 removed. Can be formed. The etch stop material layer ES150 can be formed of, for example, silicon oxide, silicon nitride, or organic insulating material.

Next, the etch stop material layer ES150 may be patterned to form the first and second etch stop layers ES10 and ES20 as shown in FIG. 9E. The first etch stop layer ES10 may be formed on the second oxide semiconductor layer 33 above the first gate G10 and the second etch stop layer ES20 may be formed on the second gate oxide layer G20, Can be formed on the oxide semiconductor layer (11). The formation of the first and second etch stop layers ES10 and ES20 is optional.

Referring to FIG. 9F, an electrode layer SD150 covering the first and second etch stop layers ES10 and ES20 may be formed on the first and second oxide semiconductor layers 11 and 33. FIG. Next, a second mask pattern M20 may be formed on the electrode layer SD150. The second mask pattern M20 may be formed of a photosensitive material. The second mask pattern M20 may have a shape that defines a region of a source / drain electrode to be formed from the electrode layer SD150.

The first oxide semiconductor layer 11 can be etched by etching the electrode layer SD150 using the second mask pattern M20 as an etching barrier. The result is shown in Figure 9g.

9G, a first active layer A10 composed of a first oxide semiconductor layer 11, an insulating layer 22, and a second oxide semiconductor layer 33 patterned above a first gate G10 is formed . A first source electrode S10 and a first drain electrode D10 which are in contact with both ends of the first active layer A10 may be formed. And a second active layer A20 composed of the first oxide semiconductor layer 11 patterned above the second gate G20 may be formed. A second source electrode S20 and a second drain electrode D20 which are in contact with both ends of the second active layer A20 may be formed. The first gate G10, the gate insulating layer GI10, the first active layer A10, the first etch stop layer ES10, the first source electrode S10, The gate insulating layer GI10, the second active layer A20, the second etch stop layer ES20, the second source electrode S20, and the second And the drain electrode D20 may constitute the second transistor Tr20.

Referring to FIG. 9H, a passivation layer P10 covering the first and second transistors Tr10 and Tr20 may be formed on the substrate SUB10. The passivation layer P10 may be, for example, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or an organic insulating layer, or a structure in which at least two or more of these layers are laminated. Next, the first transistor Tr10 and the second transistor Tr20 may be annealed at a predetermined temperature. The first transistor Tr10 and the second transistor Tr20 thus formed may correspond to the photosensor transistor Tr1 'and the switching transistor Tr2' in FIG. 8, respectively.

9A to 9H, an electronic device (light sensing circuit) including two different transistors can be easily manufactured by a relatively simple process. In this process, about four mask processes can be used. That is, a first mask process may be used to form the gates G10 and G20 of FIG. 9A, a second mask process may be used to form the first mask pattern M10 of FIG. 9B, and the etch stop layer ES10 and ES20, a third mask process may be used, and a fourth mask process may be used in forming the second mask pattern M20 of FIG. 9F.

If the oxide semiconductor layer (the "middle oxide semiconductor layer") is used instead of the insulating layer 22, etching selectivity between the first oxide semiconductor layer 11 and the "intermediate oxide semiconductor layer" There is a high possibility that the first oxide semiconductor layer 11 is damaged / lost when the "intermediate oxide semiconductor layer" is etched. Therefore, in order to prevent damage / loss of the first oxide semiconductor layer 11, a complicated process must be used, and the number of mask processes can be increased. However, when the insulating layer 22 having a high etching selectivity as in this embodiment is used, an electronic device can be easily manufactured by a simple process as described above. It can also be advantageous in securing the reproducibility of the device and improving the characteristics.

The electronic device manufactured by the method of Figs. 9A to 9H may be, for example, a light sensing circuit. In this case, the first transistor Tr10 may be an optical sensor transistor, and the second transistor Tr20 may be a switching transistor. When manufacturing such a photo sensing circuit, a predetermined display portion can be formed together. The switch of the display unit may have the same (or similar) structure as the second transistor Tr20. Therefore, the burden on the process for forming the switch of the display unit may not occur. When the display unit is formed in this manner, a flat panel display device including the photo sensing circuit can be manufactured.

Further, the manufacturing method of Figs. 9A to 9H can be variously modified. For example, in the step of FIG. 9E, the first oxide semiconductor layer 11 may be patterned to define (form) the first active region and the second active region. At this time, the first active region may be similar to the first active layer A10 of FIG. 9G, and the second active region may be similar to the second active layer A20 of FIG. 9G. After the first oxide semiconductor layer 11 is patterned to define (form) the first and second active regions, the electrode layer SD150 and the second mask pattern M20 of FIG. 9F can be formed. 9A to 9H may be modified in various ways.

10 is a graph illustrating the sensitivity of the first transistor Tr10 of FIG. 9H to light. In this case, the first active layer (A10) was used for each GaInZnO layer, SiO 2 layer and the InZnO layer a first oxide semiconductor layer 11, insulating layer 22, the second oxide semiconductor layer 33, and of these The thicknesses were about 20 nm, 100 nm and 40 nm, respectively. In FIG. 10, 'Dark' is the case where no light is irradiated, and 'Photo' is a case where light of 10,000 nit is irradiated. FIG. 10 includes data when the drain voltage Vd is 2 V and data when the drain voltage Vd is 10 V. FIG.

Referring to FIG. 10, it can be seen that a large difference occurs between the gate voltage (Vg) and the drain current (Id) graph in the case where light is not irradiated (Dark) and when light is irradiated (Photo). The off-current level was significantly increased as compared with the case where light was irradiated (Photo) and the case where light was not irradiated (Dark). That is, with respect to the left graph based on approximately OV, the graph when the light is irradiated (Photo) is located substantially above the graph when the light is not irradiated (Dark). The current I Photo when irradiated with light was greater than about 10 -6 A and the ratio of the current I Photo when irradiated with light to the current I Dark when not irradiated, that is, I Photo / I Dark is about 10 7 or more. From these results, it can be seen that the transistor according to the embodiment of the present invention has a considerably high sensitivity to light. On the other hand, the drain voltage (Vd) is I Photo / Dark I ratio was higher than the case of when the 10V is 2V.

11 is a graph illustrating the sensitivity of the second transistor Tr20 of FIG. 9H to light. More specifically, FIG. 11 shows a result of measuring the change of the characteristics of the gate voltage (Vg) -drain current (Id) with the light irradiation time while irradiating the second transistor Tr20 of FIG. to be. At this time, the second active layer A20 of the second transistor Tr20 was a GaInZnO layer. The drain voltage Vd was about 10V.

Referring to FIG. 11, it can be seen that the gate voltage (Vg) -drain current (Id) graph is hardly changed even when the light irradiation time is increased. This means that the sensitivity of the second transistor Tr20 to light is very low. Since the second transistor Tr20 is not used as an optical sensor but is used for switching purposes, the lower the light sensitivity of the second transistor Tr20 is, the better. It can be seen from this result that the second transistor Tr20 of FIG. 9H is suitable as a switching transistor.

Although the transistor of the bottom gate structure and the electronic device including the bottom gate structure have been illustrated and described above, the idea of the present invention can also be applied to the transistor of the top gate structure. Examples thereof are shown in Figs. 12 to 15. Fig. FIG. 12 is a modification of the structure of FIG. 1 to a top gate structure, FIG. 13 is a modification of the structure of FIG. 3 to a top gate structure, FIG. 15 is a modification to the top gate structure of the photo sensing circuit Tr1 '+ Tr2' in FIG.

Referring to FIG. 12, an active layer A100 may be provided on a substrate SUB100. The active layer A100 may include a second oxide semiconductor layer 300, an insulating layer 200, and a first oxide semiconductor layer 100 which are sequentially stacked. The materials of the first oxide semiconductor layer 100, the insulating layer 200 and the second oxide semiconductor layer 300 are the same as those of the first oxide semiconductor layer 10, the insulating layer 20, (30). ≪ / RTI > Therefore, it can be said that the active layer A100 is similar to the structure in which the active layer A1 of FIG. 1 is inverted upside down. A source electrode S100 and a drain electrode D100 which are in contact with both ends of the active layer A100 may be provided. A gate insulating layer GI100 covering the active layer A100, the source electrode S100 and the drain electrode D100 may be provided on the substrate SUB100. A gate G100 may be provided on the gate insulating layer GI100 above the active layer A100. A passivation layer P100 covering the gate G100 may be provided on the gate insulating layer GI100. The materials of the source electrode S100, the drain electrode D100, the gate insulating layer GI100, the gate G100 and the passivation layer P100 are the same as those of the source electrode S1, the drain electrode D1, May be the same or similar to the material of layer GI1, gate G1 and passivation layer P1.

12, by using the active layer A100 including the plurality of oxide semiconductor layers 100 and 300, the operation characteristics (threshold voltage and the like) of the transistor can be appropriately controlled The photosensitivity of the transistor can be increased. By using such a transistor, an electronic device, for example, a photo sensing device having excellent operation characteristics and photo-sensing characteristics can be realized.

The transistor of FIG. 12 may further include an etch stop layer provided on the active layer A100. An example thereof is shown in Fig.

Referring to FIG. 13, an etch stop layer ES 100 may be further provided on the active layer A 100. The shape and material of the etch stop layer ESlOO may be the same as or similar to the etch stop layer ESl of Fig. The structure of FIG. 13 may be the same as that of FIG. 12, except that the etch stop layer ES100 is provided.

14 is a cross-sectional view showing an electronic device (light sensing circuit) including a transistor according to another embodiment of the present invention.

Referring to FIG. 14, an electronic device (light sensing circuit) according to an embodiment of the present invention may include an optical sensor transistor Tr100 and a switching transistor Tr200. The photo sensor transistor Tr100 may have the same (or similar) configuration as the transistor of Fig. More specifically, the photosensor transistor Tr100 includes a first gate G100, a gate insulating layer GI100, a first active layer A100, a first source electrode S100, and a first drain electrode D100. . ≪ / RTI > The first active layer A 100 may include a first oxide semiconductor layer 100, an insulating layer 200, and a second oxide semiconductor layer 300. The first gate G100, the gate insulating layer GI100, the first active layer A100, the first source electrode S100 and the first drain electrode D100 correspond to the gate G100, The source electrode G100, the active layer A100, the source electrode S100, and the drain electrode D100. The switching transistor Tr200 may have a configuration different from that of the optical sensor transistor Tr100. The active layer (hereinafter, the second active layer) A200 of the switching transistor Tr200 may have a different configuration from the first active layer A100 of the optical sensor transistor Tr100. For example, the second active layer A200 may be a layer composed of the same material as the first oxide semiconductor layer 100 of the first active layer A100. The second active layer A200 may have a single-layer structure, but may have a multi-layer structure in some cases. The switching transistor Tr200 does not use the optical sensor layer, that is, the second oxide semiconductor layer 300, because it performs the switching function instead of the optical sensing. In the case of this switching transistor Tr200, there is almost no characteristic variation due to light. The materials and configurations of the second gate G200, the gate insulating layer GI100, the second source electrode S200 and the second drain electrode D200 of the switching transistor Tr200 are the same as those of the first gate G100, It may be the same as or similar to that of the gate insulating layer GI100, the first source electrode S100, and the first drain electrode D100.

The first etch stop layer and the second etch stop layer may be further provided on the first active layer A 100 and the second active layer A 200 of FIG. An example thereof is shown in Fig.

Referring to FIG. 15, a first etch stop layer ES 100 may be provided on the first active layer A 100 and a second etch stop layer ES 200 may be provided on the second active layer A 200. have. Other configurations may be the same as or similar to those of Fig.

The electronic device of Figs. 14 and 15 may be a photo sensing circuit, and in this case, may have a circuit configuration similar to that of Fig. 14 and 15 can be applied to various electronic devices such as a flat panel display. When the photosensing circuit of Figs. 14 and 15 is applied to a flat panel display device, the display switch of the flat panel display device may have the same structure as the switching transistors Tr200 and Tr200 '.

16A to 16H are cross-sectional views illustrating a method of manufacturing an electronic device (light sensing circuit) including a transistor according to an embodiment of the present invention.

Referring to FIG. 16A, a second oxide semiconductor layer 330 and an insulating layer 220 may be formed on a substrate SUB110. The material of the second oxide semiconductor layer 330 and the insulating layer 220 may correspond to the material of the second oxide semiconductor layer 30 and the insulating layer 20 of FIG.

Next, the second oxide semiconductor layer 330 and the insulating layer 220 may be patterned to form a stacked structure as shown in FIG. 16B. Referring to FIG. 16B, a stacked structure of the patterned second oxide semiconductor layer 330 and the patterned insulating layer 220 is provided.

Referring to FIG. 16C, a first oxide semiconductor layer 110 may be formed to cover the second oxide semiconductor layer 330 patterned on the substrate SUB110 and the stacked structure of the patterned insulating layer 220. [ The material of the first oxide semiconductor layer 110 may be the same as the material of the first oxide semiconductor layer 100 of FIG. Next, a predetermined first mask pattern M110 may be formed on the first oxide semiconductor layer 110. [ The first mask pattern M110 may have a shape that defines the first and second active regions.

The first oxide semiconductor layer 110 can be etched using the first mask pattern M110 as an etching barrier. The result is shown in Figure 16d. Referring to FIG. 16D, a first active layer A110 composed of a patterned second oxide semiconductor layer 330, an insulating layer 220, and a first oxide semiconductor layer 110 may be formed, A second active layer A220 composed of the patterned first oxide semiconductor layer 110 may be formed.

16E, the first etch stop layer ES110 can be formed on the first active layer A110 while the first mask pattern M110 is removed, and the first etch stop layer ES110 can be formed on the second active layer A220 The second etch stop layer ES220 can be formed.

Referring to FIG. 16F, a first source electrode S110 and a first drain electrode D110 which are in contact with both ends of the first active layer A110 are formed, and the first source electrode S110 and the first drain electrode D110, which contact both ends of the second active layer A220, Two source electrodes S220 and a second drain electrode D220 can be formed. The first source electrode S110 and the first drain electrode D110 may cover both ends of the first etch stop layer ES110 and the second source electrode S220 and the second drain electrode D220 may cover both ends of the first etch stop layer ES110, The both ends of the stop layer ES220 can be covered.

16G, the first and second active layers A110 and A220, the first and second source electrodes S110 and S220, the first and second drain electrodes D110 and D220 are formed on the substrate SUB110, (GI110) covering the gate insulating layer Next, the first and second gates G110 and G220 may be formed on the gate insulating layer GI110. The first gate G110 may be formed above the first active layer A110 and the second gate G220 may be formed above the second active layer A220.

Referring to FIG. 16H, a passivation layer P110 covering the first gate G110 and the second gate G220 may be formed on the gate insulating layer GI110. The passivation layer P110 may be a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or an organic insulating layer, or a structure in which at least two or more of these layers are laminated. The first active layer A110, the first etch stop layer ES110, the first source electrode S110, the first drain electrode D110, the gate insulating layer GI10 and the first gate G110 are connected to the first transistor The second source electrode S220, the second drain electrode D220, the gate insulating layer GI110, and the second active layer A220, the second active layer A220, the second etch stop layer ES220, the second source electrode S220, And the second gate G220 may configure the second transistor Tr220. The two transistors Tr110 and Tr220 formed in this manner can be annealed at a predetermined temperature.

The electronic device manufactured by the method of Figs. 16A to 16H may be, for example, a light sensing circuit. In this case, the first transistor Tr100 may be an optical sensor transistor, and the second transistor Tr220 may be a switching transistor. When manufacturing such a photo sensing circuit, a predetermined display portion can be formed together. The switch of the display unit may have the same (or similar) structure as the second transistor Tr220. When the display portions are formed together, the flat panel display device including the photo sensing circuit can be manufactured.

While many have been described in detail above, they should not be construed as limiting the scope of the invention, but rather as examples of specific embodiments. For example, those skilled in the art will appreciate that the structure of the transistors of FIGS. 1 to 3, 12, and 13 may be varied. As a specific example, at least one of the first oxide semiconductor layer 10, 10 ', 100 and the second oxide semiconductor layer 30, 300 in the transistors of FIGS. 1 to 3, 12, and 13 may have a multilayer structure have. Also, the transistor according to the embodiment of the present invention may have a double gate structure. The electronic devices of FIGS. 5, 7, 8, 14, and 15 may be applied to various electronic devices other than the light sensing circuit or the flat display device. Also, the manufacturing method of Figs. 9A to 9H and Figs. 16A to 16H can be variously changed. In addition, those skilled in the art will recognize that the idea of the present invention can be applied to other transistors other than oxide thin film transistors. Therefore, the scope of the present invention is not to be determined by the described embodiments but should be determined by the technical idea described in the claims.

Claims (39)

  1. An active layer including a first oxide semiconductor layer, a second oxide semiconductor layer, and an insulating layer provided therebetween;
    A source and a drain respectively contacting both ends of the active layer;
    A gate corresponding to the active layer; And
    And a gate insulating layer provided between the active layer and the gate,
    Wherein the insulating layer comprises a material having an etch selectivity of at least 2 with respect to at least one of the first and second oxide semiconductor layers.
  2. delete
  3. The method according to claim 1,
    Wherein the insulating layer comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride.
  4. The method according to claim 1,
    Wherein the insulating layer is a silicon oxide layer.
  5. The method according to claim 1,
    And the first oxide semiconductor layer, the insulating layer, and the second oxide semiconductor layer are sequentially formed from the gate side.
  6. 6. The method of claim 5,
    Wherein the second oxide semiconductor layer comprises a material having higher sensitivity than the first oxide semiconductor layer.
  7. 6. The method of claim 5,
    Wherein the second oxide semiconductor layer includes a material having a smaller energy band gap than the first oxide semiconductor layer.
  8. 6. The method of claim 5,
    Wherein a threshold voltage of the transistor is increased by the first oxide semiconductor layer.
  9. 6. The method of claim 5,
    Wherein the first oxide semiconductor layer comprises at least one of MInZnO, MZnO, MAlO, MSnO, wherein M is a metal element.
  10. 10. The method of claim 9,
    Wherein M is any one of Ga, Hf, Ti, Ta, Zr and Ln.
  11. 10. The method of claim 9,
    Wherein the first oxide semiconductor layer is a GaInZnO layer or an HfInZnO layer.
  12. The method according to any one of claims 5 to 11,
    Wherein the second oxide semiconductor layer comprises at least one of InZnO, InO, and ZnO.
  13. 13. The method of claim 12,
    And the second oxide semiconductor layer is an InZnO layer.
  14. The method according to claim 1,
    And an etch stop layer disposed on the active layer.
  15. The method according to claim 1,
    Wherein the gate is below the active layer.
  16. The method according to claim 1,
    Wherein the gate is disposed over the active layer.
  17. A light sensing circuit comprising the transistor of claim 1.
  18. 18. The method of claim 17,
    Wherein the transistor is an optical sensor transistor.
  19. 19. The method of claim 18,
    And a switching transistor coupled to the photosensor transistor.
  20. 20. The method of claim 19,
    Wherein the switching transistor comprises an active layer of a single-layer structure.
  21. 21. The method of claim 20,
    Wherein the active layer of the switching transistor is formed of the same material as the first oxide semiconductor layer.
  22. An electronic device comprising the photo-sensing circuit of claim 17.
  23. A first transistor including a first active layer, a first gate, a first source and a first drain; And
    And a second transistor coupled to the first transistor, the second transistor including a second active layer, a second gate, a second source, and a second drain,
    Wherein the first active layer includes a first oxide semiconductor layer, an insulating layer, and a second oxide semiconductor layer sequentially formed from the first gate side,
    And the second active layer has a different structure from the first active layer.
  24. 24. The method of claim 23,
    Wherein the insulating layer comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride.
  25. 24. The method of claim 23,
    Wherein the second oxide semiconductor layer includes a material having higher sensitivity than the first oxide semiconductor layer.
  26. 24. The method of claim 23,
    Wherein the first oxide semiconductor layer includes at least one of MInZnO, MZnO, MAlO, and MSnO, and M is any one of Ga, Hf, Ti, Ta, Zr, and Ln.
  27. 26. The method according to claim 23 or 26,
    Wherein the second oxide semiconductor layer comprises at least one of InZnO, InO, and ZnO.
  28. 24. The method of claim 23,
    And the second active layer has a single layer structure.
  29. 24. The method of claim 23,
    And the second active layer is formed of the same material as the first oxide semiconductor layer.
  30. 24. The method of claim 23,
    And the first and second transistors constitute a photo-sensing circuit.
  31. 31. The method of claim 30,
    The first transistor is an optical sensor transistor,
    And the second transistor is a switching transistor.
  32. Forming first and second gates on the substrate;
    Forming a gate insulating layer covering the first and second gates;
    Sequentially forming a first oxide semiconductor layer, an insulating layer, and a second oxide semiconductor layer on the gate insulating layer;
    Forming a first mask layer on the second oxide semiconductor layer above the first gate;
    Etching the second oxide semiconductor layer and the insulating layer using the first mask layer as an etch barrier;
    Removing the first mask layer;
    A first active region including the first oxide semiconductor layer, an insulating layer and a second oxide semiconductor layer is defined on the first gate, and a second active region including the first oxide semiconductor layer is formed on the second gate, Defining; And
    Forming a first source and a first drain in contact with the first active region, and forming a second source and a second drain in contact with the second active region.
  33. 33. The method of claim 32,
    Wherein the insulating layer is formed of a material having an etching selection ratio of 2 or more with respect to the first oxide semiconductor layer.
  34. 33. The method of claim 32,
    Wherein the insulating layer is formed of at least one of silicon oxide, silicon oxynitride, and silicon nitride.
  35. 33. The method of claim 32,
    Wherein the second oxide semiconductor layer comprises a material having higher sensitivity than the first oxide semiconductor layer.
  36. 33. The method of claim 32,
    Wherein the first oxide semiconductor layer comprises at least one of MInZnO, MZnO, MAlO and MSnO, wherein M is one of Ga, Hf, Ti, Ta, Zr and Ln.
  37. 37. The method of claim 32 or 36,
    Wherein the second oxide semiconductor layer comprises at least one of InZnO, InO, and ZnO.
  38. 33. The method of claim 32,
    And forming an etch stop layer on the first and second active regions.
  39. 33. The method of claim 32,
    The first gate, the first active region, the first source and the first drain constitute an optical sensor transistor,
    And the second gate, the second active region, the second source and the second drain constitute a switching transistor.
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