CN113594125A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN113594125A
CN113594125A CN202110473369.4A CN202110473369A CN113594125A CN 113594125 A CN113594125 A CN 113594125A CN 202110473369 A CN202110473369 A CN 202110473369A CN 113594125 A CN113594125 A CN 113594125A
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solder
semiconductor device
clip
die
cut
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CN202110473369.4A
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CN113594125B (zh
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里卡多·杨多克
弗洛兰特·费诺尔
马龙·法杜洛
拉米尔·阿蒂恩萨
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Nexperia BV
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Nexperia BV
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Abstract

本公开涉及一种半导体装置，包括：引线框；管芯，其利用第一焊料附接到引线框；夹片，其利用第二焊料附接到管芯，其中，夹片包括用于检查第二焊料的过量而布置的切口。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种形成半导体装置的方法。本发明还涉及一种制造半导体装置的方法。
背景技术
已知半导体装置(例如，MOSFET装置)具有分配在管芯的顶部上的过量焊料的问题。如在图1a和图1b中示出的。焊料10由于源极夹片与管芯之间的非常窄的间隙而到达管芯边缘。可以仅利用x
射线检查、利用电气测试或利用截面来检测该问题。图1a示出了x射线检查的结果。在图2中，示出了封装件的典型的截面，其中，源极夹片下面的材料层和过量的焊料是可见的。由于过量的焊料将漏极12桥接到源极电势，该装置将无法正常起作用，并且将导致电流泄漏。
该已知问题是不受控制的焊料分配在源极可焊接的顶部触点上，导致过量的焊料，这导致MOSFET装置的漏极与源极/栅极的桥接。
存在一些解决上述问题的已知方法。这些方法中的一些要求管芯设计的重大改变，这非常昂贵且低效。其它可能性是提供额外的过量的焊料检测设备，这也将是一种昂贵且低效的选择。此外，可以完成MOSFET装置封装外形尺寸的改变，但这将导致对模具和修整形成分离(trim forming singulation，TFS)工具的修改。与先前的选择相似，该选择实施起来也将非常昂贵且低效。通常，影响管芯尺寸、电性能和封装外形尺寸的任何变化都将非常困难，因此实施起来昂贵且低效。
通常，生产操作员将遵循后续步骤，以在制造MOSFET装置时进行额外的过量的焊料检测。首先，操作员将取出少量生产组装的样品，以通过将其带到可位于不同区域的x射线室来检查过量焊料。如果在夹片下面观察到较暗的图像或阴影，则表明已分配了过量的焊料。然后，操作员将返回机器并调整焊料分配设定。他们将重复该过程，直到再也看不到夹片下面有过量的焊料的痕迹。其次，如果操作员无法或错过通过x射线检查样品，则检查过量的焊料问题的下一种可能性是进行电气测试。然而，在进行最终测试之前，需要先完成装置，即，必须完成整个组装过程(模制、电镀和分离)，由于操作员将无法在封装或由塑料模制并从引线框分离之前对MOSFET装置进行测试。因此，在最终测试中发现过量的焊料之前，许多MOSFET装置将已经组装好并且必须报废。在测试由于边缘情况而未能过滤掉过量的焊料的情况下，将不报废MOSFET装置，并且在使用此类MOSFET装置期间可能失败；这显然不是优选的选择，因为它可能会引起潜在的客户投诉。第三，操作员还可以通过重复x射线工艺或通过进行横截面来验证任何短路的装置，这在得出结果之前将需要几天的时间。总而言之，用于管理过量焊料的问题的所有以上步骤都不是优选的，因为它们可能很昂贵和/或很耗时，这在MOSFET装置工业中是完全不可接受的。
图2a、图2b和图2c分别示出了已知的MOSFET装置的俯视图、等距视图和侧视图。任何过量的焊料(例如，在标记的位置14处)通过可视检查是不可见的。
图3a和图3b中示出了一种用于过量的焊料检查的已知解决方案。焊料检查孔16用于可视地检查过量的焊料。然而，当创建检查孔16时，这导致窄的宽度18。如此窄的宽度将导致较高的封装电阻。较高的封装电阻将导致MOSFET装置的更多的功耗。图3b中所示的带有检查孔16的示例仅适用于较宽的引线。这种检查孔不适用于具有窄引线的MOSFET装置。例如，这些检查孔不能用在双管芯焊盘夹片键合的封装件中。在窄引线中添加的任何孔都将导致封装电阻的增大以及引线共面性在冲压工艺期间的不稳定。
总而言之，如上所述的用于过量的焊料检查的解决方案均不适用于需要窄引线的MOSFET装置和其他半导体装置。
发明内容
各种示例实施例针对如上所述缺点和/或可以从以下公开变得显而易见的其它缺点。
根据本发明的实施例，半导体装置包括：引线框；管芯，其利用第一焊料附接到引线框；以及夹片，其利用第二焊料附接到管芯。夹片包括用于检查第二焊料的过量而布置的切口。
利用这样的切口能够进行过量的焊料检查，而不修改封装外观尺寸、当前的管芯设计并且不改变制造步骤。
通过在夹片中引入切口特征，对于操作员而言，容易可视地判断焊料是否过量，而无需离开制造机器以执行半导体装置的昂贵且耗时的x射线检查。因此，本发明提供了节省成本，并且防止了所生产的半导体装置的潜在质量问题。
此外，由于该切口不使夹片的宽度明显变窄，因此该切口将不增大封装电阻。
根据本发明的实施例，切口的形状为矩形或半圆形。在切口的形状是半圆形的情况下，优选半圆形的半径与夹片的厚度具有相同或相似的尺寸。在本发明的另一优选实施例中，半圆形的半径和夹片的厚度为大约0.2mm。
在本发明的实施例中，切口通过铜冲压或通过蚀刻工艺制成。与使用化学蚀刻工艺相比，铜冲压工艺在大规模生产方面相对便宜。
在本发明的优选实施例中，半导体装置是MOSFET装置，其中，MOSFET装置包括源极、栅极和漏极。切口位于MOSFET装置的源极与漏极之间和/或栅极和漏极之间。
本发明还涉及一种制造半导体装置的方法，其中，在其他标准制造步骤之中，所述方法包括以下步骤：形成引线框；利用第一焊料将管芯附接到引线框；以及利用第二焊料将夹片附接到管芯。夹片包括用于检查第二焊料的过量而布置的切口。同样，切口的形状可以是矩形或半圆形。在切口的形状是半圆形的情况下，在本发明的优选实施例中，这样的半圆形的半径与夹片的厚度具有相同或相似的尺寸。优选地，半圆形的半径和夹片的厚度为大约0.2mm。切口可以通过铜冲压或通过蚀刻工艺制成。
附图说明
为了可以详细地理解本公开的特征，参照其中一些在附图中示出的实施例进行了更具体的描述。然而，要注意，附图仅示出了典型的实施例，因此不应被认为是对其范围的限制。附图用于促进对本公开的理解，因此不一定按比例绘制。结合附图阅读本描述之后，所要求保护的主题的优点对于本领域技术人员将变得显而易见，在附图中，同样的附图标记用于表示同样的元件，并且在附图中：
图1a和图1b示出了已知的MOSFET装置，其中，过量的焊料分配在管芯的顶部上；
图2a、图2b和图2c分别示出了已知的MOSFET装置的俯视图、等距视图和侧视图；
图3a和图3b示出了具有焊料检查孔的已知的MOSFET装置；
图4a、图4b和图4c分别示出了根据本发明的实施例的半导体装置的俯视图、等距视图和侧视图；
图5示出了根据本发明的实施例的制造半导体装置的方法。
具体实施方式
图4a、图4b和图4c中示出了本发明的实施例。这些图分别示出了半导体装置100(即，MOSFET装置、绝缘栅双极型晶体管、双极型晶体管、JFET装置、晶闸管、二极管等)的俯视图、等距视图和侧视图。
半导体装置100包括引线框102和利用第一焊料104附接到引线框102的管芯106。利用第二焊料116将夹片120附接到管芯106。夹片120包括用于检查第二焊料116的过量而布置的切口200。在图4a、图4b和图4c中所示的示例中，切口200是侧切口。具有这样的切口200特征容易以相对简单的方式(即，不使用昂贵的x射线机器)进行第二焊料116的过量的可视检查。
侧切口200可以具有不同的形状，例如，矩形、半圆形(如图4a、图4b和图4c中的示例实施例中所示出的)等。切口200可以通过铜冲压、通过蚀刻工艺等来创建。如果切口200具有半圆形形状，则在优选的示例实施例中，半圆形的半径的最小尺寸与夹片120的厚度相同。夹片120可以由铜制成。在本发明的优选的实施例中，夹片120的半径和厚度的尺寸为大约0.2mm左右。
建议在应检查过量的焊料的位置中设置这样的切口200。在本发明的示例实施例中，切口200设置在从一侧的半导体装置100的源极电势和栅极电势以及从另一侧的管芯106的边缘之间。管芯106的该边缘对应于半导体装置的漏极电势。在生产半导体装置100时，由于存在切口200，机器操作员将能够阻止可能过量的焊料，随后立即调整焊料的分配。
切口200特别被设计为不减小夹片120的宽度，以确保维持半导体装置100的源极端子上的扩展电阻。
通过在夹片120中引入切口200，解决了上述现有技术的问题。操作员可以可视地判断焊料是否过量。不需要使用以上提及的诸如半导体装置的x射线检查的其它昂贵且低效的方法。因此，本发明的实施方式明显低节省了成本，并且防止会由焊料的过量导致的可能的质量问题。
如图4a和图4b中的示例实施例中所示出的，切口200设置在用于半导体装置的源极的夹片120上，并且还设置在用于半导体装置的栅极的夹片120上。这对于需要较低的扩展电阻的MOSFET装置特别有利，并且根据本发明的实施例的切口200支持这样的较低的扩展电阻。由于切口200不使夹片120的宽度显著变窄，因此切口将不增大封装电阻。
使用切口200的另一优点是其可以通过铜冲压工艺来完成，与使用成本为其10倍的化学蚀刻工艺相比，在大规模生产方面，铜冲压工艺相对便宜。由于夹片的宽度足够宽，因此铜冲压工艺不适用于窄宽度的夹片，但是适用于根据本发明的实施例的切口。
图5中示出了根据本发明的实施例的制造半导体装置的方法。
所述方法包括以下步骤：
步骤301：提供可被冲压或蚀刻底部的引线框102
步骤303：在引线框102上打印、写入或分配第一焊料104
步骤305：形成利用第一焊料104附接到引线框102的管芯106步骤307：在管芯106上打印、写入或分配第二焊料116
步骤309：形成包括切口200的夹片120，并且将夹片120附接到硅管芯106的顶部上；夹片120包含源极端子和栅极端子；横杆(dambar)124连接这些端子；因此组装的部分随后将进入回流工艺，以固化凝固物或固化所涂敷的焊料
步骤311：对从前一步骤固化且组装后的装置执行模制，以用密封剂122封装硅；需要封装以保护硅管芯免受任何氧化和污染；产品将在模制之后进一步进行锡(Sn)电镀工艺，以电镀外部引线，以便于保护铜免于氧化
步骤313：执行修整/形成/分离(TFS)工艺，其中，引线框和夹片的某些部分将被去除以制成最终的半导体装置
步骤315：执行横杆124的切割，其中，创建了分离的半导体装置
如图5中所示的步骤315是分离的半导体装置的顶视图。图5中的项目317和319分别示出了其中内层可视的该分离的半导体装置的等距视图和侧视图。
所附独立权利要求中阐述了本发明的特定和优选的方面。来自从属权利要求和/或独立权利要求的特征的组合可以适当地结合，而不仅是如权利要求中所阐述的。
本公开的范围包括任何新颖的特征或其中明确或隐含地公开的特征的组合或其任何概括，而不管其是否涉及要求保护的发明或减轻了本发明所解决的任何或所有问题。申请人特此通知，在起诉本申请或由此衍生的任何此类进一步申请期间，可以对这样的特征提出新的权利要求。特别地，参照所附权利要求，可以将从属权利要求的特征与独立权利要求的特征组合，并且可以以任何适当的方式而不是仅仅以权利要求中列举的特定组合来组合来自各个独立权利要求的特征。
在单独的实施例的上下文中描述的特征也可以在单个实施例中组合提供。相反，为简洁起见，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合来提供
术语“包括”不排除其他元件或步骤，术语“一”或“一个”不排除多个。权利要求中的附图标记不应解释为限制权利要求的范围。

Claims (11)

1.一种半导体装置，包括：
引线框，
管芯，其利用第一焊料附接到所述引线框，
夹片，其利用第二焊料附接到所述管芯，
其中，所述夹片包括用于检查所述第二焊料的过量而布置的切口。
2.根据权利要求1所述的半导体装置，其中，所述切口的形状为矩形或半圆形。
3.根据前述权利要求中任一项所述的半导体装置，其中，所述切口通过铜冲压工艺或蚀刻工艺制成。
4.根据权利要求2所述的半导体装置，其中，所述切口的形状是半圆形，并且其中，所述半圆形的半径与所述夹片的厚度具有相同或相似的尺寸。
5.根据权利要求4所述的半导体装置，其中，所述半圆形的半径和所述夹片的厚度为大约0.2mm。
6.根据前述权利要求中任一项所述的半导体装置，其中，所述半导体装置是晶体管(MOSFET装置)，所述晶体管(所述MOSFET装置)包括源极、栅极和漏极，其中，所述切口位于所述源极与所述漏极之间以及/或者所述栅极与所述漏极之间。
7.一种制造半导体装置的方法，所述方法包括以下步骤：
形成引线框，
利用第一焊料将管芯附接到所述引线框，
利用第二焊料将夹片附接到所述管芯，
其中，所述夹片包括用于检查所述第二焊料的过量而布置的切口。
8.根据权利要求7所述的制造半导体装置的方法，其中，所述切口的形状为矩形或半圆形。
9.根据权利要求7或8所述的制造半导体装置的方法，所述切口通过铜冲压工艺或蚀刻工艺制成。
10.根据权利要求8所述的制造半导体装置的方法，其中，所述切口的形状是半圆形，并且其中，所述半圆形的半径与所述夹片的厚度具有相同或相似的尺寸。
11.根据权利要求10所述的制造半导体装置的方法，其中，所述半圆形的半径和所述夹片的厚度为大约0.2mm。
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