CN113589884A - Data processing system - Google Patents

Abstract

The present disclosure relates to a data processing system that may be implemented in a board card that includes a chip and other mating components including, but not limited to: a memory device, an interface arrangement and a control device. The memory device is connected with the chip in the chip packaging structure through a bus and used for storing data. The memory device may include a plurality of groups of memory cells.

Description

Data processing system

Technical Field

The present disclosure relates generally to the field of circuitry and, more particularly, to data processing systems.

Background

Conventionally, a data collector (e.g., an image sensor, a deserializer, etc.) and a processor are connected by a single-ended signal with 8 bits or more and a clock signal, and the interconnection method has short signal transmission distance, low image resolution and low image frame rate, taking the image sensor as an example. At present, the transmission mode is only suitable for some low-end application scenes and cannot meet complex applications such as traffic, mobile phones, single-lens reflex and tablet computers.

With the rapid development of intelligent mobile electronic devices, new challenges are brought about by interface transmission bandwidths between a data collector and a processor with high pixels and a large frame rate, and the traditional interface cannot meet the requirements. Driven by market demand, differential signaling has become a bridge interconnecting data collectors and processors, and has been undertaken by the mobile industry processor interface (mipi) alliance, which is a mobile industry processor interface, initiated by companies such as Texas Instruments (TI), nokia, ARM, and semiconductor by law, minds (ST), which aims to define and generalize standards for use between interfaces and processors such as data collectors, liquid crystal displays, and baseband.

Currently, a mobile device does not satisfy a single data collector, and a plurality of data collectors (such as image sensors) are standard, for example, a mobile phone. The traditional method is that a processor is added with a plurality of MIPI interfaces to realize the access of a plurality of data collectors. But a plurality of MIPI interfaces have no correlation and are completely independent.

However, because the requirements of the data acquisition devices on the bandwidth of the MIPI signal are inconsistent in different scenes, the processor is configured with a plurality of high-speed MIPI interfaces, which causes a certain waste and increases the cost and volume of the processor; a plurality of low-speed MIPI interfaces are configured to only meet part of scenes, so that the competitiveness of a processor is reduced; therefore, the quantity configuration and the standard of the MIPI can not be unified, and a plurality of MIPI interfaces can not be flexibly configured.

Disclosure of Invention

In order to at least partially solve the problem of poor scalability of the system mentioned in the background art, a data processing system with strong scalability is provided.

According to a first aspect of the present disclosure, a data processing system is provided, which includes a data interface, a clock interface, a mode switching unit, and a processor, where the processor is provided with a first port and a second port, the data interface includes a first, a second, a third, and a fourth data interface, and the clock interface includes a first clock interface and a second clock interface; the first data interface and the second data interface are used for receiving a first data signal of the data collector and are respectively connected to a first port of the processor through a first data channel and a second data channel; the third data interface and the fourth data interface are used for receiving a second data signal of the data collector and are respectively connected to a second port of the processor through a third data channel and a fourth data channel; the clock interface is used for receiving a clock signal of the data acquisition unit and is connected to the first port and the second port of the processor through corresponding clock channels by switching of the mode switching component.

According to a second aspect of the present disclosure, a data processing system is provided, which includes a data interface, a clock interface, a mode switching component and a processor, wherein the processor is provided with a first port, a second port, a third port and a fourth port, the data interface includes first to eighth data interfaces, the clock interface includes first to fourth clock interfaces, the data interface is used for connecting a data collector, and the mode switching component includes a first mode switching component and a second mode switching component, wherein the data collector includes a first low-precision sensor, a second low-precision sensor and a high-resolution sensor, the first low-precision sensor is connected to the first and second data interfaces and is connected to the first port of the processor through a first data channel and a second data channel, respectively; the second low-precision sensor is connected to third and fourth data interfaces and is connected to a second port of the processor through a third data channel and a fourth data channel, respectively; the first mode switching section is switched so that: the first low-precision sensor is connected to a first clock interface and a first port of the processor through a first clock channel; the second low-precision sensor is connected to a second clock interface and a second port of the processor through a second clock channel; and the high-precision sensor is connected to fifth and sixth data interfaces and is connected to a third port of the processor through a fifth data channel and a sixth data channel, respectively; the high-precision sensor is connected to seventh and eighth data interfaces and is connected to a fourth port of the processor through a seventh data channel and an eighth data channel, respectively; the high-precision sensor is connected to the third port and the fourth port of the processor through a third clock interface or a fourth clock interface, via switching by the second mode switching section, and through a third clock channel and a fourth clock channel.

According to a third aspect of the present disclosure, there is provided a board comprising the data processing system as described above.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising the data processing system as described above.

The technical scheme of the disclosure can be flexibly configured according to actual requirements so as to connect data collectors with different precisions, such as image sensors with different resolutions and different frame rates.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 shows a schematic diagram of a data processing system, according to an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of a data processing system when the data collector is a low precision sensor according to one embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of a data processing system, according to an embodiment of the present disclosure;

FIG. 4 shows a schematic diagram of a data processing system, according to another embodiment of the present disclosure;

FIG. 5 shows a schematic diagram of a data processing system, according to an embodiment of the present disclosure;

FIGS. 6 a-6 f are more specific representations of FIG. 5 showing a schematic diagram of a data processing system according to one embodiment of the present disclosure;

FIGS. 7 a-7 d illustrate embodiments for switching from one connection mode to another connection mode;

FIG. 8 shows a schematic diagram of a data processing system, according to an embodiment of the present disclosure;

fig. 9 shows a schematic diagram of a board card.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

FIG. 1 shows a schematic diagram of a data processing system, according to one embodiment of the present disclosure.

As shown in fig. 1, the processing system may include a data interface, a clock interface 120, a mode switching unit 130, and a processor 20, wherein the processor 20 is provided with a first port 210 and a second port 220, the data interface includes a first data interface 1110, a second data interface 1120, a third data interface 1130, and a fourth data interface 1140, and the clock interface 120 includes a first clock interface 1210 and a second clock interface 1220; the first data interface 1110 and the second data interface 1120 are used for receiving a first data signal of a data collector, and are connected to the first port 210 of the processor 20 through a first data channel L1 and a second data channel L2 respectively; the third data interface 1130 and the fourth data interface 1140 are used for receiving a second data signal of the data collector and are connected to the second port 220 of the processor through a third data channel L3 and a fourth data channel L4, respectively; the clock interface 120 is configured to receive a clock signal of a data collector, and is connected to the first port 210 and the second port 220 of the processor via corresponding clock channels by switching of the mode switching unit 130. These components can be arranged on the circuit board 10 or on a card.

It should be understood that the data interface 1110 and 1140 and the clock interface 1210 and 1220 are only exemplary representations, and in practical applications, the corresponding data interface and clock interface may be added or deleted according to actual requirements, so that they can cooperate with the corresponding data collector. The types of the interfaces can be adjusted correspondingly according to the type of the adopted data collector. It is also to be understood that the mode switching member 130 herein may be a switch, by adjusting which various connections are formed, or may be a resistor or discrete device, by adjusting the position of these mode switching members 130, which various connections are formed.

The data lanes L1-L4 may be data lanes that transmit data signals. FIG. 2 illustrates one embodiment of the data lanes L1-L4. In fig. 2, each data channel is divided into P-channel and N-channel, i.e., the first data channel L1 is divided into channel P1 and channel N1, the second data channel L2 is divided into channel P2 and channel N2, the third data channel L3 is divided into channel P3 and channel N3, and the fourth data channel L4 is divided into channel P4 and channel N4.

The clock channel can receive the differential clock signal and input the differential clock signal into different ports of the processor under the control of the mode switching part according to the type of the adopted data collector so as to process the signals acquired by different types of data collectors. The clock channels are also divided into P-channels and N-channels, i.e., clock channels CLK P1 and CLK N1, and clock channels CLK P2 and CLK N2.

The data collector can be divided into a low-precision sensor, a high-precision sensor and the like, wherein the precision can represent resolution, frame rate and the like, and can also be other factors capable of influencing the precision. Low-accuracy sensors transmit less data and therefore can transmit data through a smaller number of data channels, while high-accuracy sensors transmit more data and therefore need to transmit data through a larger number of data channels. It should be understood that low precision and high precision are relative concepts, and when a certain amount (for example, two) of data channels are enough to complete data transmission in a predetermined time, the data is considered as low precision data; and when a certain amount of data channels can not finish data transmission within a preset time, the data is considered to be high-precision.

The ports of the Processor 20 may include various types, and may include, for example, a Mobile Industry Processor Interface (MIPI) or a Low Voltage Differential Signaling (LVDS). The processors in the present application may also employ any other suitable type of interface.

The mode switching component 130 can switch to select an appropriate clock channel according to the type of data collector used, and the switching can be manual or automatic. It is to be understood that the mode switching component 130 can be a set of switches rather than just a single switch, which would control the connection and disconnection of multiple lines, respectively. The mode switching component 130 may be a small resistor with a resistance value of approximately 0 to replace a switching chip (e.g., a clock chip or a clock buffer) in the prior art. One advantage of having a small resistor as the mode switching means is that costs can be reduced, and furthermore, having a small resistor as the mode switching means allows switching to be accomplished by removal, replacement, or the like.

FIG. 3 shows a schematic diagram of a data processing system when the data collector is a low precision sensor according to one embodiment of the present disclosure.

As shown in fig. 3, when the data collector 30 comprises a first low-precision sensor 310 and a second low-precision sensor 320, the first low-precision sensor 310 is connected to a first data interface 1110 and a second data interface 1120, and is connected to the first port 210 of the processor through a first data channel L1 and a second data channel L2, respectively; the second low-precision sensor 320 is connected to a third data interface 1130 and a fourth data interface 1140 and to the second port 220 of the processor via a third data channel L3 and a fourth data channel L4, respectively.

In this embodiment, two low- precision sensors 310 and 320 are illustratively connected. Because the low-precision sensors transmit less data, one low-precision sensor can be connected to each port of the processor.

As shown in fig. 3, the mode switching part 130 may be switched so that: the first low-precision sensor 310 is connected to a first clock interface 1210 and to the first port 210 of the processor through a first clock channel via the mode switching means 130; the second low-precision sensor 320 is coupled to a second clock interface 1220 coupled to the second port 220 of the processor via a second clock channel.

In fig. 3, the mode switching part 130 may be represented by a resistor. In fig. 3, only the clock signal of the first low-precision sensor 310 reaches the first port 210 of the processor 20 through the mode switching part, and the clock signal of the second low-precision sensor 320 may be directly connected to the second port 220 of the processor 20 through a wire.

In this embodiment, the mode switching component 130 may be disconnected, such that the clock signal of the first low-precision sensor 310 may be disconnected from the first port 210 of the processor 20, while the second low-precision sensor 320 may be always connected to the second port 220 of the processor 20 through a wire.

FIG. 4 shows a schematic diagram of a data processing system according to another embodiment of the present disclosure.

As shown in fig. 4, when the data collector 30 comprises a first low-precision sensor 310 and a second low-precision sensor 320, the first low-precision sensor 310 is connected to a first data interface 1110 and a second data interface 1120, and is connected to the first port 210 of the processor through a first data channel L1 and a second data channel L2, respectively; the second low-precision sensor 320 is connected to a third data interface 1130 and a fourth data interface 1140 and to the second port 220 of the processor via a third data channel L3 and a fourth data channel L4, respectively.

In distinction from the circuit shown in fig. 3, the mode switching section 130 may be switched so that: the first low-precision sensor 310 is connected to a first clock interface 1210, connected to the first port 210 of the processor through a first clock channel; the second low-precision sensor 320 is connected to a second clock interface 1220 and, via the mode switch block 130, to the second port 220 of the processor via a second clock channel.

In fig. 4, the mode switching part 130 may be represented by a resistor. In fig. 4, only the clock signal of the second low-precision sensor 320 reaches the second port 220 of the processor 20 through the mode switching unit, and the clock signal of the first low-precision sensor 310 may be directly connected to the second port 210 of the processor 20 through a wire.

In this embodiment, the mode switching component 130 may be disconnected, such that the clock signal of the second low-precision sensor 320 may be disconnected from the second port 220 of the processor 20, while the first low-precision sensor 310 may be always connected to the first port 210 of the processor 20 through a wire.

FIG. 5 shows a schematic diagram of a data processing system, according to an embodiment of the present disclosure.

As shown in fig. 5, when the data collector comprises the high-precision sensor 330, the high-precision sensor 330 is connected to the first data interface 1110 and the second data interface 1120, and is connected to the first port 210 of the processor through the first data channel L1 and the second data channel L2, respectively; the high-precision sensor 330 is connected to a third data interface 1130 and a fourth data interface 1140, and is connected to the second port 220 of the processor through a third data channel L3 and a fourth data channel L4, respectively; the high-precision sensor 330 is connected to the first port 210 and the second port 220 of the processor through the first clock interface 1210 or the second clock interface 1220, through switching by the mode switching part 130, and through the first clock channel and the second clock channel.

In fig. 5, the four data interfaces of the high-precision sensor 330 are respectively connected to the first port 210 of the processor 20 through the first data interface 1110 and the second data interface 1120, and are connected to the second port 220 of the processor 20 through the third data interface 1130 and the fourth data interface 1140, so that a large amount of data obtained by the high-precision sensor 330 can be input into the processor through more data channels.

In fig. 5, the high-precision sensor 330 only needs to be connected to one clock interface 1210 or 1220 (illustratively, the clock signal path connecting the first clock interface 1210 and the second clock interface 1220 is shown by a dotted line in fig. 5). Thus, the clock signal received by the clock interface 1210 or 1220 is divided into two paths to be input into the first port 210 and the second port 220. In this embodiment. The mode switching component may be a resistor of a passive device that will ensure that the clock signals input into the first port 210 and the second port 220 remain synchronized. This reduces the need for synchronous control of the clock signal compared to prior art chips (active devices) as mode switching components.

Fig. 6 a-6 f are more detailed representations of fig. 5 showing a schematic diagram of a data processing system according to one embodiment of the present disclosure.

As shown in fig. 6a, the high-precision sensor 330 is connected to the first port 210 of the processor through a first clock channel via the mode switching part 130 through a first clock interface 1210; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel through a first clock interface 1210.

In fig. 6a, the second clock interface 1220 may be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the first clock interface 1210, one path enters the first port 210 through the mode switching unit 130, and the other path enters the second port 220 through the direct connection line.

As shown in fig. 6b, the high-precision sensor 330 is connected to the first port 210 of the processor through a first clock channel via a first clock interface 1210; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel via the mode switching part 130 through a first clock interface 1210.

In fig. 6b, the second clock interface 1220 may be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the first clock interface 1210, one path enters the second port 220 through the mode switching unit 130, and the other path enters the first port 210 through a direct connection.

As shown in fig. 6c, the high-precision sensor 330 is connected to the first port 210 of the processor through a first clock channel via the mode switching part 130 through a second clock interface 1220; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel through a second clock interface 1220.

In fig. 6c, the first clock interface 1210 may be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths through the second clock interface 1220, one path enters the first port 210 through the mode switching unit 130, and the other path enters the second port 220 through the direct connection.

As shown in fig. 6d, the high-precision sensor 330 is connected to the first port 210 of the processor through a second clock interface 1220 and through a first clock channel; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel via the mode switching part 130 through a second clock interface 1220.

In fig. 6d, the first clock interface 1210 may be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths through the second clock interface 1220, one path enters the second port 220 through the mode switching unit 130, and the other path enters the first port 210 through a direct connection.

Figure 6e is an electrically equivalent variant of the data processing system shown in figure 6 b. As shown in fig. 6e, the electrical structural equivalence of fig. 6b is that the high precision sensor 330 is connected to the first port 210 of the processor through a first clock channel via a first clock interface 1210; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel via the mode switching part 130 through a first clock interface 1210. In fig. 6e, the second clock interface 1220 may be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the first clock interface 1210, one path enters the second port 220 through the mode switching unit 130, and the other path enters the first port 210 through a direct connection.

Fig. 6b and 6e are electrically equivalent, but in fig. 6e, the mode switching part 130 can be disposed on a connection line between two clock channels, which makes it unnecessary to make any adjustment to the existing clock channels, but only to dispose a new line between the two clock channels, thereby simplifying the design of the circuit. In other embodiments, the signal transmission quality can be improved by adjusting or removing redundant lines or devices in the clock channel.

Figure 6f is an electrically equivalent variation of the data processing system shown in figure 6 c. As shown in fig. 6f, the high-precision sensor 330 is connected to the first port 210 of the processor through a first clock channel via the mode switching part 130 through a second clock interface 1220; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel through a second clock interface 1220. In fig. 6f, the first clock interface 1210 may be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths through the second clock interface 1220, one path enters the first port 210 through the mode switching unit 130, and the other path enters the second port 220 through the direct connection.

Fig. 6c and 6f are electrically equivalent, but in fig. 6f, the mode switching means 130 can be arranged on the connection line between the two clock channels, which makes it unnecessary to make any adjustments to the existing clock channels, but only to arrange a new line between the two clock channels, thereby simplifying the design of the circuit. In other embodiments, the signal transmission quality can be improved by adjusting or removing redundant lines or devices in the clock channel.

The connections shown in fig. 6a to 6f are essentially equivalent, and any of these may be used in an actual circuit design. It should also be understood that the position of the mode switching component in fig. 6 a-6 f is merely an example, and any circuit that is equivalent in circuit structure to this structure is within the scope of the present disclosure.

According to the above description, the data processing system of the present application can conveniently connect the low-precision sensor and the high-precision sensor, and after the sensor type is changed, only the mode switching component needs to be adjusted to form the corresponding circuit.

Fig. 7 a-7 d show embodiments for switching from one connection mode to another.

As shown in fig. 7a, when connecting the first low-precision sensor 310 and the second low-precision sensor 320, the first low-precision sensor 310 may be connected to the contact T1 through the first clock interface 1210, and the contact T1 may be connected to the first port 210 through the mode switching member 130; the second low-precision sensor 320 may be connected to the contact T2 through the second clock interface 1220 and then to the second port 220 through the contact T2.

When the high-precision sensor 330 is connected, the mode switching section 130 can switch, i.e., disconnect the contact T1 and connect the contact T2, so that the high-precision sensor 330 is connected to the second port 220 through the second clock interface 1220 and the contact T2 and is connected to the first port 210 through the second clock interface 1220 and the mode switching section 130.

The structure shown in fig. 7b is equivalent in circuit structure to that of fig. 7a, but the physical location of the mode switching part 130 in fig. 7b is different from that of fig. 7 a. This will result in a slight difference between the two in terms of chip packaging, circuit routing.

Figure 7c shows a schematic diagram of switching from connecting a low-precision sensor to a high-precision sensor.

As shown in fig. 7c, when the low-precision sensor is connected, it appears as shown in the upper diagram of fig. 7c, where the mode switching part 130 is connected between the first clock interface 1210 and the first port 210. When it is desired to connect a high-precision sensor, the first clock interface 1210 can be disabled without connecting a low-precision sensor, and the mode switching component 130 can be removed, the removal and disabling being indicated by the "X" label in FIG. 7c for ease of understanding.

When a high-precision sensor is connected, the first clock interface 1210 is disabled and the second clock interface 1220 receives the clock signal of the high-precision sensor. The removed mode switching component 130 is connected between the two clock channels so that the clock signal from the high precision sensor goes all the way directly to the second port 220 of the processor and the other way through the mode switching component 130 to the first port 210 of the processor. Thereby, switching from connecting the low-precision sensor to connecting the high-precision sensor is completed. FIG. 7d shows a schematic diagram of switching from connecting a high-accuracy sensor to a low-accuracy sensor.

Fig. 7d is the reverse operation of fig. 7 c. As shown in fig. 7d, when the high-precision sensor is connected, the mode switching section 130 is connected between two clock channels. When it is desired to connect a low-precision sensor, the first clock interface 1210 can be enabled and the mode switching component 130 connected between the two clock channels can be removed, the removal in FIG. 7d also being indicated by the "X" label for ease of understanding.

When a low-precision sensor is connected, the first clock interface 1210 is enabled and receives the clock signal from the first low-precision sensor 310, while the second clock interface 1220 receives the clock signal of the second low-precision sensor 320. The removed mode switching means 130 is connected between the first clock interface 1210 and the first port 210 (or between the second clock interface 1220 and the second port 220), thereby completing the switching from connecting the high-precision sensor to connecting the low-precision sensor.

It is to be understood that the mode switching section 130 in the circuit connecting the low-precision sensor and the mode switching section 130 in the circuit connecting the high-precision sensor may not be the same as long as the connection of the circuits can be achieved.

The above described switching is only an example and a person skilled in the art may refer to various mode switching means to implement a plurality of switching functions.

FIG. 8 shows a schematic diagram of a data processing system, according to an embodiment of the present disclosure.

As shown in fig. 8, the data processing system comprises a data interface, a clock interface 120 and a mode switching unit 130 and a processor 20, the processor 20 is provided with a first port 210, a second port 220, a third port 230 and a fourth port 240, the data interfaces include first through eighth data interfaces 1110-1180, the clock interfaces include first through fourth clock interfaces 1210-1240, the data interface is used for connecting the data collector 30, the mode switching part 130 includes a first mode switching part 1310 and a second mode switching part 1320, wherein the data collector 30 comprises a first low-precision sensor 310, a second low-precision sensor 320 and a high-resolution sensor 330, the first low-precision sensor 310 is connected to a first data interface and 1110 a second data interface 1120, and connected to the first port 210 of the processor through a first data path L1 and a second data path L2, respectively; the second low-precision sensor 320 is connected to a third data interface 1130 and a fourth data interface 1140 and to the second port 220 of the processor through a third data channel and a fourth data channel L4 of L3, respectively; the first mode switching section 1310 is switched so that: the first low-precision sensor 310 is connected to a first clock interface 1210, connected to the first port 210 of the processor through a first clock channel; the second low-precision sensor 320 is connected to a second clock interface 1220, which is connected to the second port 220 of the processor through a second clock channel; and the high accuracy sensor 330 is connected to a fifth data interface 1150 and a sixth data interface 1160 and to a third port 230 of the processor via a fifth data channel L5 and a sixth data channel L6, respectively; the high-precision sensor is connected to a seventh data interface 1170 and an eighth data interface 1180, and is connected to the fourth port 240 of the processor through a seventh data channel L7 and an eighth data channel L8, respectively; the high accuracy sensor 330 is connected to the third port 230 and the fourth port 240 of the processor through the third clock interface 1230 or the fourth clock interface 1240, through the second mode switching unit 1320, and through the third clock channel and the fourth clock channel. These components may be disposed on the circuit board 10

In fig. 8, the connections of the low-accuracy sensors may be varied as described above in connection with fig. 4 and 5, while the connections of the high-accuracy sensors may be varied as described above in connection with fig. 6 a-6 f, and the high-accuracy sensors and the low-accuracy sensors may be varied as described above in connection with fig. 7 a-7 d.

In fig. 8, there may be multiple ports per processor 20. Taking four ports as an example, two low-precision sensors and one high-precision sensor can be connected; along with different requirements, the mode switching component can be adjusted, so that four low-precision sensors can be connected, and two high-precision sensors can be connected. Therefore, the technical scheme of the disclosure can be flexibly configured according to actual requirements.

It will be appreciated that the number of ports of the processor 20 is not limited in this disclosure and that various changes may be made to the data processing system described above.

In some embodiments, the present disclosure also discloses a board card including a chip, which may be the processor 30 described above. Referring to fig. 9, an exemplary card is provided that may include other kits in addition to the chip 902, including but not limited to: a memory device 904, an interface device 906 (which may be a data interface and a clock interface as described above in this disclosure), and a control device 908.

The memory device is connected with the chip in the chip packaging structure through a bus and used for storing data. The memory device may include a plurality of sets of memory cells 910. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The interface device is electrically connected with a chip in the chip packaging structure. The interface device is used to enable data transmission between the chip and an external device 912 (e.g., a server, a computer, or the high-precision and/or low-precision sensors described above in this disclosure). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. In another embodiment, the interface device may also be another interface, and the disclosure does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the interface device.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing and/or a plurality of processing circuits in the chip.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, optical, acoustic, magnetic or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. With this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing detailed description of the embodiments of the present disclosure has been presented for purposes of illustration and description and is intended to be exemplary only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed; meanwhile, for the person skilled in the art, based on the idea of the present disclosure, there may be variations in the specific embodiments and the application scope, and in summary, the present disclosure should not be construed as limiting the present disclosure.

Claims (12)

1. A data processing system comprises a data interface, a clock interface, a mode switching component and a processor, wherein the processor is provided with a first port and a second port, the data interface comprises a first data interface, a second data interface, a third data interface and a fourth data interface, and the clock interface comprises a first clock interface and a second clock interface;

the first data interface and the second data interface are used for receiving a first data signal of the data collector and are respectively connected to a first port of the processor through a first data channel and a second data channel;

the third data interface and the fourth data interface are used for receiving a second data signal of the data collector and are respectively connected to a second port of the processor through a third data channel and a fourth data channel;

the clock interface is used for receiving a clock signal of the data acquisition unit and is connected to the first port and the second port of the processor through corresponding clock channels by switching of the mode switching component.

2. The data processing system of claim 1, wherein, when the data collector comprises a first low-precision sensor and a second low-precision sensor,

the first low-precision sensor is connected to the first and second data interfaces and is connected to the first port of the processor through a first data channel and a second data channel, respectively;

the second low-precision sensor is connected to third and fourth data interfaces and is connected to a second port of the processor through a third data channel and a fourth data channel, respectively;

the mode switching section is switched so that:

the first low-precision sensor is connected to a first clock interface and a first port of the processor through a first clock channel;

the second low-precision sensor is connected to a second clock interface and to a second port of the processor through a second clock channel.

3. The data processing system of claim 2,

the mode switching section is switched so that:

the first low-precision sensor is connected to a first clock interface and to a first port of the processor through a first clock channel via the mode switching component;

the second low-precision sensor is connected to a second clock interface and to a second port of the processor through a second clock channel.

4. The data processing system of claim 2, wherein the mode switching component is switched such that:

the first low-precision sensor is connected to a first clock interface and a first port of the processor through a first clock channel;

the second low-precision sensor is connected to a second clock interface and to a second port of the processor through a second clock channel via the mode switch component.

5. The data processing system of claim 1, wherein, when the data collector comprises a high-precision sensor,

the high-precision sensor is connected to the first and second data interfaces and is connected to the first port of the processor through a first data channel and a second data channel respectively;

the high-precision sensor is connected to a third data interface and a fourth data interface and is connected to a second port of the processor through a third data channel and a fourth data channel respectively;

the high-precision sensor is connected to the first port and the second port of the processor through the first clock interface or the second clock interface, through switching of the mode switching unit, and through the first clock channel and the second clock channel.

6. The data processing system of claim 5,

the high-precision sensor is connected to a first port of the processor through a first clock channel through a first clock interface via the mode switching component; and

the high-precision sensor is connected to a second port of the processor through a second clock channel through a first clock interface; or

The high-precision sensor is connected to a first port of the processor through a first clock channel through a first clock interface; and

the high-precision sensor is connected to a second port of the processor through a second clock channel via the mode switching component through a first clock interface.

7. The data processing system of claim 5,

the high-precision sensor is connected to a first port of the processor through a first clock channel through a second clock interface and the mode switching component; and

the high-precision sensor is connected to a second port of the processor through a second clock interface and a second clock channel; or

The high-precision sensor is connected to a first port of the processor through a first clock channel through a second clock interface; and

the high-precision sensor is connected to a second port of the processor through a second clock interface through a second clock channel via the mode switching component.

8. A data processing system comprises a data interface, a clock interface, a mode switching component and a processor, wherein the processor is provided with a first port, a second port, a third port and a fourth port, the data interface comprises a first data interface, a second data interface, a third data interface, a fourth data interface, the clock interface comprises a first clock interface, a second clock interface, a fourth clock interface, the data interface is used for connecting a data acquisition unit, the mode switching component comprises a first mode switching component and a second mode switching component, the data acquisition unit comprises a first low-precision sensor, a second low-precision sensor and a high-resolution sensor,

the first low-precision sensor is connected to the first and second data interfaces and is connected to the first port of the processor through a first data channel and a second data channel, respectively;

the second low-precision sensor is connected to third and fourth data interfaces and is connected to a second port of the processor through a third data channel and a fourth data channel, respectively;

the first mode switching section is switched so that:

the first low-precision sensor is connected to a first clock interface and a first port of the processor through a first clock channel;

the second low-precision sensor is connected to a second clock interface and a second port of the processor through a second clock channel; and

the high-precision sensor is connected to fifth and sixth data interfaces and is connected to a third port of the processor through a fifth data channel and a sixth data channel, respectively;

the high-precision sensor is connected to seventh and eighth data interfaces and is connected to a fourth port of the processor through a seventh data channel and an eighth data channel, respectively;

the high-precision sensor is connected to the third port and the fourth port of the processor through a third clock interface or a fourth clock interface, via switching by the second mode switching section, and through a third clock channel and a fourth clock channel.

9. The data processing system of any of claims 1-8, wherein the mode switching component is a resistor.

10. The data processing system of any of claims 1-9, wherein the port comprises a mobile industry processor port or a low voltage differential signal port.

11. A board comprising the data processing system of any of claims 1 to 10.

12. An electronic device comprising a data processing system according to any one of claims 1 to 10.

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