CN113589148B - A multichannel power strip for chip test field - Google Patents
A multichannel power strip for chip test field Download PDFInfo
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- CN113589148B CN113589148B CN202110946570.XA CN202110946570A CN113589148B CN 113589148 B CN113589148 B CN 113589148B CN 202110946570 A CN202110946570 A CN 202110946570A CN 113589148 B CN113589148 B CN 113589148B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a multichannel power panel for the field of chip testing; the circuit card board comprises a main board and four sub boards, wherein the main board comprises an FPGA chip, a power conversion circuit, an output current sampling circuit, an EEPROM, a communication chip and the sub boards comprise a voltage and current output circuit, a voltage and current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit; the invention uses 1 FPGA board card plus software algorithm to achieve the functions of a plurality of standard instrument power supplies and digital multimeters; the source and sink functions are provided; 40 channels and can be independently controlled; the output voltage is controllable from-10V to +10V, and the resolution reaches 1mV; output voltage accuracy: <0.05%, output voltage measurement accuracy: <0.05%; the output currents-1A to +1A are controllable; outputting current measurement accuracy; communication control is supported.
Description
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a multichannel power panel for the field of chip testing.
Background
An integrated circuit abbreviated IC; microcircuits (microcircuits), microchips, chips/dies (chips) are known as a way of miniaturizing circuits (mainly including semiconductor devices, also including passive components, etc.) in electronics and often fabricated on semiconductor wafer surfaces, and after transistor discovery and mass production, various solid state semiconductor components such as diodes, transistors, etc. are used in large quantities, replacing the functions and roles of vacuum tubes in the circuits. Advances in semiconductor fabrication technology have been made in the middle and late 20 th century. It is a tremendous advancement that integrated circuits can integrate a large number of micro-transistors into a small chip, as opposed to manually assembled circuits using individual discrete electronic components. The mass-productivity, reliability, and modularity of the circuit design ensures that the use of discrete transistors is replaced by a standardized integrated circuit that has two major advantages for discrete transistors: cost and performance. The cost is low because the chip prints all the components as a unit by photolithographic techniques rather than just making one transistor at a time. The high performance is due to the fast switching of the components, consuming less energy, because the components are small and close to each other. In the field of chip testing, multiple-channel, high-precision and programming-controlled power supplies are needed in many cases, but various problems still exist in various test power supplies on the market.
The system for testing the core power supply of the main board disclosed by the grant publication No. CN112630678A solves the problem that the quality test of the core power supply of the domestic large-current chip is inaccurate due to the fact that the hardware environment for specially testing the quality of the core power supply of the domestic large-current chip is not available at present, but the problem that the number of power output channels of the existing small-power supply module is generally smaller than or equal to 16 is not solved; the power supply generally only has the problem of source function, and therefore we propose a multi-channel power panel for the chip test field.
Disclosure of Invention
The invention aims to provide a multichannel power panel for the field of chip testing, so as to solve the problems in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions: the multi-channel power panel comprises a circuit card board, wherein the circuit card board comprises a main board and four sub-boards, the main board comprises an FPGA chip, a power conversion circuit, an output current sampling circuit, an EEPROM, a communication chip and the sub-boards comprise a voltage and current output circuit, a voltage and current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit;
the power supply conversion circuit is electrically connected with the FPGA chip, the power supply conversion circuit is electrically connected with an output current sampling circuit, the output current sampling circuit is electrically connected with the FPGA chip, and the FPGA chip is electrically connected with the EEPROM and the communication chip;
the back side of the voltage current output circuit is electrically connected with the voltage current clamping circuit, the back side of the voltage current clamping circuit is electrically connected with the power operational amplifier circuit, and the current feedback circuit and the voltage feedback circuit are electrically connected with the voltage current clamping circuit;
the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, 16-bit DAC conversion, 16-bit ADC conversion and amplification circuit;
the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip;
the FPGA chip defines and controls the power supply conversion circuit, and external signals and internal control signals are processed, controlled and instructed through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8-F, a clock active crystal oscillator U6-F, a memory chip U9-F for storing calibration data and a memory chip U10-F;
the power supply output measuring circuit is divided into 6 measuring ranges according to the current, the FPGA chip receives a measuring instruction, the relay of the corresponding circuit is controlled to be attracted, and the voltage at two ends of the sampling resistor is measured to realize current measurement;
the voltage at the SS1 end of the voltage-current output circuit is the voltage at the power supply output Sense end, and the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1 to provide a reference level for the subsequent voltage regulation and the voltage-current clamp circuit;
the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a main board sampling resistor, and the voltages are output to IFB1 after passing through an operational amplifier and a differential amplifier, so that reference levels are provided for subsequent voltage regulation and the voltage current clamping circuit;
the current feedback circuit and the U11-1 chip of the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to an FMODEL1 pin for clamping, and a clamp1 signal and an fb1 signal are output to the clamping circuit;
the input ends of VF1 and fb1 of the voltage and current clamping circuit output AZ1, a clamping circuit part, and the partial pressure of feedback voltage and clamping voltage through an adder and a reversing circuit are taken as the input end of AD712, when the voltage is greater than 0, the voltage is output to be +15V after passing through U2-1A, a diode D2-1 is conducted, the 3-pin voltage of U2-1A is always clamped at 0V, when the voltage is less than 0, the voltage is output to be-15V after passing through U2-1B, a diode D3-1 is conducted, and the 3-pin voltage of U2-1B is always clamped at 0V;
the power supply circuit is characterized by further comprising a board voltage output setting circuit and a clamping setting circuit, wherein the board voltage output setting circuit and the clamping setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamping voltage is controlled, each chip controls 2 paths of power supply output, and each daughter board realizes 10 paths of power supply control through 5 DAC chips.
Preferably, the power supply conversion circuit comprises a group of 24V voltage conversion circuits, a group of 15V voltage conversion circuits, three groups of filter circuits and a group of voltage reduction circuits.
Preferably, the 24V voltage conversion circuit and the 15V voltage conversion circuit are connected in series and parallel with four groups of electrolytic capacitors, two groups of induction coils are connected between the four groups of electrolytic capacitors and the four groups of capacitors, the three groups of filter circuits comprise two groups of electrolytic capacitors and two groups of capacitors which are connected in series and parallel with each other, induction coils are electrically connected between the two groups of electrolytic capacitors and the two groups of capacitors, the step-down circuit comprises step-down chips AMS 1-33, and two sides of the step-down chips AMS 1-117 are electrically connected with two groups of capacitors, one group of electrolytic capacitors and one group of resistors.
Preferably, the communication chip is provided with six groups, a pin and twenty-four pins on two sides of the communication chip are respectively and electrically connected with a capacitor, two pins of the four groups of communication chips are electrically connected with the capacitor on the pin through a resistor, and the twenty-four pins are electrically connected with twenty-three pins.
Preferably, the power output measurement circuit includes a TP1C6B273 chip, resistors are electrically connected to CLK and CLR pins of the TP1C6B273 chip, two groups of resistors are electrically connected, a capacitor is further electrically connected to the CLR pin, and a capacitor is also electrically connected to VCC pin of the TP1C6B273 chip.
Preferably, the voltage and current output circuit includes an INA105U gain differential amplifier chip and a plurality of operational amplifiers, wherein two sides of the INA105U gain differential amplifier chip are respectively and electrically connected with three operational amplifiers, and one of the operational amplifiers is connected with one operational amplifier in series.
Preferably, the output current sampling circuit comprises an INA149AIDR differential operational amplifier chip and a plurality of operational amplifiers, wherein the two sides of the INA149AIDR differential operational amplifier chip are respectively and electrically connected with three operational amplifiers.
8. The multi-channel power strip for chip testing according to claim 1, wherein: the current feedback circuit and the voltage feedback circuit adopt ADG453BRZ multiplexers.
Preferably, the device further comprises a program control time sequence of the board card, wherein the program control time sequence comprises a read-write command of the tester, the read-write command of the tester is transmitted to the FPGA chip, and the FPGA chip decodes the read-write command of the tester through an address.
Preferably, the read-write command of the decoding test machine includes a query board card command, a mode setting command, an applied voltage command, a clamping voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM write data command and a ROM read data command.
Compared with the prior art, the invention has the beneficial effects that:
1. 1 FPGA board card plus software algorithm is used to achieve the functions of a plurality of standard instrument power supplies and digital multimeters;
2. the source and sink functions are provided;
3.40 channels and independently controllable;
4. the output voltage is controllable from-10V to +10V, and the resolution reaches 1mV;
5. output voltage accuracy: <0.05%, output voltage measurement accuracy: <0.05%;
6. the output currents-1A to +1A are controllable;
7. output current measurement accuracy:
-40uA to+40uA@20nA@±0.2％
-400uA to+400uA@200nA@±0.2％
-4mA to+4mA@2uA@±0.2％
-40mA to+40mA@20uA@±0.2％
-400mA to+400mA@200uA@±0.1％
-1A to+1A@800uA@±0.2％；
8. communication control is supported.
Drawings
FIG. 1 is a schematic diagram of a system architecture of the present invention;
FIG. 2 is a circuit diagram of a power conversion circuit according to the present invention;
FIG. 3 is a circuit diagram of a communication chip according to the present invention;
FIG. 4 is a circuit diagram of an FPGA chip and its external circuitry according to the present invention;
FIG. 5 is a circuit diagram of a power output measurement circuit of the present invention;
FIG. 6 is a circuit diagram of a voltage-current output circuit of the present invention;
FIG. 7 is a circuit diagram of an output current sampling circuit of the present invention;
FIG. 8 is a circuit diagram of a current feedback circuit and a voltage feedback circuit of the present invention;
FIG. 9 is a circuit diagram of a voltage current clamp circuit of the present invention;
FIG. 10 is a circuit diagram of a board voltage output setting circuit and a clamp setting circuit of the present invention;
fig. 11 is a schematic diagram illustrating a program control timing sequence of the board FPGA according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 to 11, the present invention provides a technical solution: the multi-channel power panel comprises a circuit card board, wherein the circuit card board comprises a main board and four sub-boards, the main board comprises an FPGA chip, a power conversion circuit, an output current sampling circuit, an EEPROM, a communication chip and the sub-boards comprise a voltage and current output circuit, a voltage and current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit;
the power supply conversion circuit is electrically connected with the FPGA chip, the power supply conversion circuit is electrically connected with an output current sampling circuit, the output current sampling circuit is electrically connected with the FPGA chip, and the FPGA chip is electrically connected with the EEPROM and the communication chip;
the back side of the voltage current output circuit is electrically connected with the voltage current clamping circuit, the back side of the voltage current clamping circuit is electrically connected with the power operational amplifier circuit, and the current feedback circuit and the voltage feedback circuit are electrically connected with the voltage current clamping circuit;
the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, 16-bit DAC conversion, 16-bit ADC conversion and amplification circuit;
the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip;
the FPGA chip defines and controls the power supply conversion circuit, and external signals and internal control signals are processed, controlled and instructed through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8-F, a clock active crystal oscillator U6-F, a memory chip U9-F for storing calibration data and a memory chip U10-F;
the power supply output measuring circuit is divided into 6 measuring ranges according to the current, the FPGA chip receives a measuring instruction, the relay of the corresponding circuit is controlled to be attracted, and the voltage at two ends of the sampling resistor is measured to realize current measurement;
the voltage at the SS1 end of the voltage-current output circuit is the voltage at the power supply output Sense end, and the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1 to provide a reference level for the subsequent voltage regulation and the voltage-current clamp circuit;
the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a main board sampling resistor, and the voltages are output to IFB1 after passing through an operational amplifier and a differential amplifier, so that reference levels are provided for subsequent voltage regulation and the voltage current clamping circuit;
the current feedback circuit and the U11-1 chip of the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to an FMODEL1 pin for clamping, and a clamp1 signal and an fb1 signal are output to the clamping circuit;
the input ends of VF1 and fb1 of the voltage and current clamping circuit output AZ1, a clamping circuit part, and the partial pressure of feedback voltage and clamping voltage through an adder and a reversing circuit are taken as the input end of AD712, when the voltage is greater than 0, the voltage is output to be +15V after passing through U2-1A, a diode D2-1 is conducted, the 3-pin voltage of U2-1A is always clamped at 0V, when the voltage is less than 0, the voltage is output to be-15V after passing through U2-1B, a diode D3-1 is conducted, and the 3-pin voltage of U2-1B is always clamped at 0V;
the power supply circuit is characterized by further comprising a board voltage output setting circuit and a clamping setting circuit, wherein the board voltage output setting circuit and the clamping setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamping voltage is controlled, each chip controls 2 paths of power supply output, and each daughter board realizes 10 paths of power supply control through 5 DAC chips.
In order to realize stable power supply operation of the system, so that voltage is stable, in this embodiment, preferably, the power supply conversion circuit includes a group of 24V voltage conversion circuit and a group of 15V voltage conversion circuit, three groups of filter circuits and a group of voltage reduction circuit, the 24V voltage conversion circuit and the 15V voltage conversion circuit include four groups of electrolytic capacitors and four groups of capacitor strings connected in parallel, two groups of induction coils are connected between the four groups of electrolytic capacitors and the four groups of capacitors, the three groups of filter circuits include two groups of electrolytic capacitors and two groups of capacitor strings connected in parallel, the two groups of electrolytic capacitors and the two groups of capacitors are electrically connected with induction coils, the voltage reduction circuit includes voltage reduction chips AMS1 117-33, and two groups of capacitors, one group of electrolytic capacitors and one group of resistors are electrically connected to two sides of the voltage reduction chips AMS 1-117-33.
In order to realize data information transmission for communication, in this embodiment, preferably, the communication chip is provided with six groups, a pin on two sides of the communication chip and twenty-four pins are respectively and electrically connected with capacitors, two pins of the four groups of communication chips are electrically connected with the capacitors on the pins through resistors, and the twenty-four pins are electrically connected with twenty-three pins.
In order to effectively measure the output circuit and maintain the stability of the circuit voltage, in this embodiment, preferably, the power output measurement circuit includes a TP1C6B273 chip, resistors are respectively electrically connected to CLK pins and CLR pins of the TP1C6B273 chip, two groups of resistors are electrically connected, a capacitor is further electrically connected to the CLR pins, and a capacitor is also electrically connected to VCC pins of the TP1C6B273 chip.
In order to realize detection of voltage and current of the circuit, control and adjustment are convenient, and in order to improve accuracy of data and facilitate acquisition and use, in this embodiment, preferably, the voltage and current output circuit includes an INA105U gain differential amplifier chip and a plurality of operational amplifiers, two sides of the INA105U gain differential amplifier chip are respectively and electrically connected with three operational amplifiers, and one of the operational amplifiers is connected with one operational amplifier in series.
In order to detect the output current and improve the samplings of the data, in this embodiment, preferably, the output current sampling circuit includes an INA149AIDR differential operational amplifier chip and a plurality of operational amplifiers, and two sides of the INA149AIDR differential operational amplifier chip are respectively and electrically connected with three operational amplifiers.
In order to realize effective selective on-off of the data information of the current feedback and the voltage feedback, in this embodiment, it is preferable that the current feedback circuit and the voltage feedback circuit adopt an ADG453BRZ multiplexer.
In order to realize the control adjustment on the board card in the program, in this embodiment, preferably, the method further includes a program control time sequence of the board card, where the program control time sequence includes a read-write command of a test machine, the test machine read-write command is transmitted to the FPGA chip, the FPGA chip decodes the test machine read-write command through an address, and the decoded test machine read-write command includes a query board card command, a mode setting command, an applied voltage command, a clamp voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM write data command, and a ROM read data command.
The working principle and the using flow of the invention are as follows: the method comprises the steps that a test machine read-write command is transmitted to an FPGA chip, the FPGA chip decodes the test machine read-write command through an address, the decoded test machine read-write command comprises a query board card command, a mode setting command, an applied voltage command, a clamping voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM write data command and a ROM read data command, then the board card operates, and a power supply conversion circuit is used for converting an external input power supply into a power supply of an internal FPGA chip, a 16-bit DAC conversion circuit, a 16-bit ADC conversion circuit and an amplifying circuit; the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip; the FPGA chip defines a control power supply conversion circuit, and external signals and internal control signals are processed, controlled and instructed through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8-F, a clock active crystal oscillator U6-F, a memory chip U9-F for storing calibration data and a memory chip U10-F; the power supply output measuring circuits are divided into 6 measuring ranges according to the current, the measuring instructions are received through the FPGA chip, the relay of the corresponding circuit is controlled to be attracted, and the voltages at two ends of the sampling resistor are measured to realize current measurement; the SS1 end of the voltage-current output circuit is the voltage of the power supply output Sense end, and the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1 to provide a reference level for the subsequent voltage regulation and voltage-current clamp circuit; the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of the main board sampling resistor, and the voltages are output to IFB1 after passing through the operational amplifier and the differential amplifier, so that reference levels are provided for subsequent voltage regulation and voltage current clamping circuits; the current feedback circuit and the U11-1 chip of the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to an FMODEL1 pin for clamping, and a clamp1 signal and an fb1 signal are output to the clamping circuit; the input ends of VF1 and fb1 of the voltage-current clamping circuit output AZ1 through an adder and an inverse circuit, a clamping circuit part, and the partial pressure of feedback voltage and clamping voltage are taken as the input ends of AD712, when the voltage is greater than 0, the voltage is +15V through the output of U2-1A, the diode D2-1 is conducted, the 3-pin voltage of U2-1A is always clamped at 0V, when the voltage is less than 0, the voltage is-15V through the output of U2-1B, the diode D3-1 is conducted, and the 3-pin voltage of U2-1B is always clamped at 0V; the board card voltage output setting circuit and the clamping setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamping voltage is controlled, each chip controls 2 paths of power supply output, and each sub-board realizes 10 paths of power supply control through 5 DAC chips.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A multichannel power strip for chip test field, including circuit cardboard, its characterized in that: the circuit card board comprises a main board and four sub boards, wherein the main board comprises an FPGA chip, a power supply conversion circuit, an output current sampling circuit, an EEPROM (electrically erasable programmable read-Only memory) and a communication chip, and the sub boards comprise a voltage and current output circuit, a voltage and current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit;
the power supply conversion circuit is electrically connected with the FPGA chip, the power supply conversion circuit is electrically connected with an output current sampling circuit, the output current sampling circuit is electrically connected with the FPGA chip, and the FPGA chip is electrically connected with the EEPROM and the communication chip;
the back side of the voltage current output circuit is electrically connected with the voltage current clamping circuit, the back side of the voltage current clamping circuit is electrically connected with the power operational amplifier circuit, and the current feedback circuit and the voltage feedback circuit are electrically connected with the voltage current clamping circuit;
the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, 16-bit DAC conversion, 16-bit ADC conversion and amplification circuit;
the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip;
the FPGA chip defines and controls the power supply conversion circuit, and external signals and internal control signals are processed, controlled and instructed through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8-F, a clock active crystal oscillator U6-F, a memory chip U9-F for storing calibration data and a memory chip U10-F;
the power supply output measuring circuit is divided into 6 measuring ranges according to the current, the FPGA chip receives a measuring instruction, the relay of the corresponding circuit is controlled to be attracted, and the voltage at two ends of the sampling resistor is measured to realize current measurement;
the voltage at the SS1 end of the voltage-current output circuit is the voltage at the power supply output Sense end, and the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1 to provide a reference level for the subsequent voltage regulation and the voltage-current clamp circuit;
the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a main board sampling resistor, and the voltages are output to IFB1 after passing through an operational amplifier and a differential amplifier, so that reference levels are provided for subsequent voltage regulation and the voltage current clamping circuit;
the current feedback circuit and the U11-1 chip of the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to an FMODEL1 pin for clamping, and a clamp1 signal and an fb1 signal are output to the clamping circuit;
the input ends of VF1 and fb1 of the voltage and current clamping circuit output AZ1, a clamping circuit part, and the partial pressure of feedback voltage and clamping voltage through an adder and a reversing circuit are taken as the input end of AD712, when the voltage is greater than 0, the voltage is output to be +15V after passing through U2-1A, a diode D2-1 is conducted, the 3-pin voltage of U2-1A is always clamped at 0V, when the voltage is less than 0, the voltage is output to be-15V after passing through U2-1B, a diode D3-1 is conducted, and the 3-pin voltage of U2-1B is always clamped at 0V;
the power supply circuit is characterized by further comprising a board voltage output setting circuit and a clamping setting circuit, wherein the board voltage output setting circuit and the clamping setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamping voltage is controlled, each chip controls 2 paths of power supply output, and each daughter board realizes 10 paths of power supply control through 5 DAC chips.
2. The multi-channel power strip for chip testing according to claim 1, wherein: the power supply conversion circuit comprises a group of 24V voltage conversion circuits, a group of 15V voltage conversion circuits, three groups of filter circuits and a group of voltage reduction circuits.
3. The multi-channel power strip for chip testing according to claim 2, wherein: the 24V voltage conversion circuit and the 15V voltage conversion circuit are connected in series and parallel with four groups of electrolytic capacitors, two groups of induction coils are connected between the four groups of electrolytic capacitors and the four groups of capacitors, the three groups of filter circuits comprise two groups of electrolytic capacitors and two groups of capacitors which are connected in series and parallel with each other, the two groups of electrolytic capacitors and the two groups of capacitors are electrically connected with induction coils, the step-down circuit comprises step-down chips AMS1 117-33, and two sides of the step-down chips AMS 1-33 are electrically connected with two groups of capacitors, one group of electrolytic capacitors and one group of resistors.
4. The multi-channel power strip for chip testing according to claim 1, wherein: the communication chip is provided with six groups, one pin and twenty-four pins on two sides of the communication chip are respectively and electrically connected with a capacitor, two pins of the four groups of communication chips are electrically connected with the capacitor on the pin through resistors, and the twenty-four pins are electrically connected with twenty-three pins.
5. The multi-channel power strip for chip testing according to claim 1, wherein: the power output measurement circuit comprises a TP1C6B273 chip, resistors are respectively and electrically connected to CLK and CLR pins of the TP1C6B273 chip, two groups of resistors are electrically connected, a capacitor is also electrically connected to the CLR pin, and a capacitor is also electrically connected to a VCC pin of the TP1C6B273 chip.
6. The multi-channel power strip for chip testing according to claim 1, wherein: the voltage and current output circuit comprises an INA105U gain differential amplifier chip and a plurality of operational amplifiers, wherein the two sides of the INA105U gain differential amplifier chip are respectively and electrically connected with three operational amplifiers, and one operational amplifier is connected with one operational amplifier in series.
7. The multi-channel power strip for chip testing according to claim 1, wherein: the output current sampling circuit comprises an INA149AIDR differential operational amplifier chip and a plurality of operational amplifiers, wherein the two sides of the INA149AIDR differential operational amplifier chip are respectively and electrically connected with the three operational amplifiers.
8. The multi-channel power strip for chip testing according to claim 1, wherein: the current feedback circuit and the voltage feedback circuit adopt ADG453BRZ multiplexers.
9. The multi-channel power strip for chip testing according to claim 1, wherein: the system also comprises a program control time sequence of the board card, wherein the program control time sequence comprises a read-write command of a testing machine, the read-write command of the testing machine is transmitted to the FPGA chip, and the FPGA chip decodes the read-write command of the testing machine through an address.
10. The multi-channel power strip for chip testing as defined in claim 9, wherein: the read-write command of the decoding test machine comprises a query board card command, a mode setting command, an applied voltage command, a clamping voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM write data command and a ROM read data command.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110946570.XA CN113589148B (en) | 2021-08-18 | 2021-08-18 | A multichannel power strip for chip test field |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110946570.XA CN113589148B (en) | 2021-08-18 | 2021-08-18 | A multichannel power strip for chip test field |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113589148A CN113589148A (en) | 2021-11-02 |
| CN113589148B true CN113589148B (en) | 2023-09-01 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999421A (en) * | 1999-03-31 | 1999-12-07 | Liu; Kwang H. | Dual-channel power system with an eight-pin PWM control chip |
| CN110857959A (en) * | 2018-08-24 | 2020-03-03 | 西安恩狄集成电路有限公司 | Chip reset test board and test method |
| CN211239813U (en) * | 2020-01-21 | 2020-08-11 | 合肥本源量子计算科技有限责任公司 | Multi-channel voltage source |
| CN112114246A (en) * | 2020-09-22 | 2020-12-22 | 杭州长川科技股份有限公司 | Adjustable power supply of integrated circuit test board and integrated circuit test board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11050496B2 (en) * | 2018-05-21 | 2021-06-29 | National Instruments Corporation | Over-the-air testing of millimeter wave integrated circuits with integrated antennas |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999421A (en) * | 1999-03-31 | 1999-12-07 | Liu; Kwang H. | Dual-channel power system with an eight-pin PWM control chip |
| CN110857959A (en) * | 2018-08-24 | 2020-03-03 | 西安恩狄集成电路有限公司 | Chip reset test board and test method |
| CN211239813U (en) * | 2020-01-21 | 2020-08-11 | 合肥本源量子计算科技有限责任公司 | Multi-channel voltage source |
| CN112114246A (en) * | 2020-09-22 | 2020-12-22 | 杭州长川科技股份有限公司 | Adjustable power supply of integrated circuit test board and integrated circuit test board |
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