CN221261114U - Loop selection circuit module - Google Patents
Loop selection circuit module Download PDFInfo
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- CN221261114U CN221261114U CN202322948827.2U CN202322948827U CN221261114U CN 221261114 U CN221261114 U CN 221261114U CN 202322948827 U CN202322948827 U CN 202322948827U CN 221261114 U CN221261114 U CN 221261114U
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- silicon gate
- cmos device
- gate cmos
- loop selection
- speed silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 238000012360 testing method Methods 0.000 claims abstract description 28
- 239000013256 coordination polymer Substances 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 22
- 230000000087 stabilizing effect Effects 0.000 claims description 15
- 238000001514 detection method Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Abstract
The utility model relates to the technical field of resistance testing, in particular to a loop selection circuit module which comprises a plurality of loop selection units which are sequentially connected in series, wherein each loop selection unit comprises a high-speed silicon gate CMOS device and a plurality of test switch modules which are connected with the high-speed silicon gate CMOS device, the high-speed silicon gate CMOS device of the first loop selection unit is provided with a data input signal end DSA, the high-speed silicon gate CMOS device of each loop selection unit is provided with a shift enable signal end CP and a reset signal RST end, the data input signal end DSA is used for receiving an initial signal, the shift enable signal end CP is used for controlling an output signal of the high-speed silicon gate CMOS device, and the reset signal RST end is used for eliminating the output of the high-speed silicon gate CMOS device to close the test switch modules. The utility model has novel structure, is convenient to measure a plurality of resistors at the same time, and improves the production efficiency and the detection efficiency.
Description
Technical Field
The utility model relates to the technical field of resistance testing, in particular to a loop selection circuit module.
Background
The multichannel resistance test equipment is test equipment widely applied to the electronic field. In the course of product manufacturing, in order to ensure product quality, accurate measurements of the resistance of the product loop are required. There are a large number of resistance test devices on the market at present, but the following problems exist: the traditional manual testing instrument has low testing efficiency and can not meet the requirements of modern production; most of traditional test instruments are single-path or double-path resistance tests, and cannot test a plurality of resistance values at the same time, so that the test time is long and the efficiency is low.
Disclosure of Invention
The utility model provides a loop selection circuit module aiming at the problems of the prior art, which has novel structure and ingenious design, can complete the detection of all loop selection units at one time, is convenient for measuring a plurality of resistors at the same time, and improves the production efficiency and the detection efficiency.
In order to solve the technical problems, the utility model adopts the following technical scheme:
The utility model provides a loop selection circuit module, which comprises a plurality of loop selection units connected in series in sequence, wherein each loop selection unit comprises a high-speed silicon gate CMOS device and a plurality of test switch modules connected with the high-speed silicon gate CMOS device, the high-speed silicon gate CMOS device of the first loop selection unit is provided with a data input signal end DSA, the high-speed silicon gate CMOS device of each loop selection unit is provided with a shift enable signal end CP and a reset signal RST end, the data input signal end DSA is used for receiving an initial signal, the shift enable signal end CP is used for controlling an output signal of the high-speed silicon gate CMOS device, and the reset signal RST end is used for eliminating the output of the high-speed silicon gate CMOS device to close the test switch modules.
The model of the high-speed silicon gate CMOS device is 74HC164.
The high-speed silicon gate CMOS devices of each loop selection unit are respectively connected with a voltage stabilizing capacitor, and the high-speed silicon gate CMOS devices of each loop selection unit are grounded through the voltage stabilizing capacitors.
The test switch module comprises an MOS switch tube, wherein a grid electrode of the MOS switch tube is connected with the high-speed silicon gate CMOS device, a source electrode of the MOS switch tube is grounded, and a drain electrode of the MOS switch tube is connected with an external device to be tested.
The test switch module further comprises a filter capacitor, wherein two ends of the filter capacitor are respectively connected with the source electrode of the MOS switch tube and the drain electrode of the MOS switch tube.
The utility model has the beneficial effects that:
The utility model has novel structure and ingenious design, can complete the detection of all loop selection units at one time, is convenient for simultaneously measuring a plurality of resistors, and improves the production efficiency and the detection efficiency.
Drawings
Fig. 1 is a circuit diagram of a loop selection circuit module according to the present utility model.
Fig. 2 is a circuit diagram of a first loop selection unit and a second loop selection unit of the present utility model.
Detailed Description
The utility model will be further described with reference to examples and drawings, to which reference is made, but which are not intended to limit the scope of the utility model. The present utility model will be described in detail below with reference to the accompanying drawings.
Example 1
The circuit selection circuit module comprises a plurality of circuit selection units which are sequentially connected in series, each circuit selection unit comprises a high-speed silicon gate CMOS device and a plurality of test switch modules which are connected with the high-speed silicon gate CMOS device, wherein the high-speed silicon gate CMOS device of the first circuit selection unit is provided with a data input signal end DSA, the high-speed silicon gate CMOS device of each circuit selection unit is provided with a shift enable signal end CP and a reset signal RST end, the data input signal end DSA is used for receiving an initial signal, the shift enable signal end CP is used for controlling an output signal of the high-speed silicon gate CMOS device, and the reset signal RST end is used for eliminating the output of the high-speed silicon gate CMOS device to close the test switch modules. Specifically, when the utility model works, the external MCU controls the high-speed silicon gate CMOS device of the utility model, and the external MCU is provided with input signals: the external MCU is provided with an input command input signal which is an initial signal, a data input signal end DSA is arranged on the high-speed silicon gate CMOS device which is input to the first loop selection unit, the data input signals of the high-speed silicon gate CMOS devices of the other loop selection units are all provided by the output signals of the data of the high-speed silicon gate CMOS devices of the previous loop selection unit, the external MCU controls the output signals of the high-speed silicon gate CMOS devices through the shift enable signal which is input to the shift enable signal end CP of the high-speed silicon gate CMOS device, and the shift enable signal end CP is triggered from rising edges; the external MCU is used for clearing the output of all the high-speed silicon gate CMOS devices by inputting a reset signal to the reset signal RST end of the high-speed silicon gate CMOS devices and setting the reset signal RST end to be low level, namely turning off all the test switch modules; when the test switch module works and the high-speed silicon gate CMOS device outputs high level, the test switch module is conducted to connect the loop selection unit, the structure is novel, the design is ingenious, the detection of all the loop selection units can be completed at one time, the measurement of a plurality of resistor loops is convenient, and the production efficiency and the detection efficiency are improved.
In the embodiment of the application, the high-speed silicon gate CMOS device of each loop selection unit is respectively connected with a voltage stabilizing capacitor, and the high-speed silicon gate CMOS device of each loop selection unit is grounded through the voltage stabilizing capacitor. The high-speed silicon gate CMOS devices of the 8 loop selection units respectively comprise a chip U1, a chip U2, a chip U3, a chip U4, a chip U5, a chip U6, a chip U7 and a chip U8, wherein the chip U1, the chip U2, the chip U3, the chip U4, the chip U5, the chip U6, the chip U7 and the chip U8 are respectively connected with the ground through a voltage stabilizing capacitor C64, a voltage stabilizing capacitor C65, a voltage stabilizing capacitor C66, a voltage stabilizing capacitor C67, a voltage stabilizing capacitor C76, a voltage stabilizing capacitor C77, a voltage stabilizing capacitor C78 and a voltage stabilizing capacitor C79. Specifically, under the action of the voltage stabilizing capacitor, the high-speed silicon gate CMOS device can be stabilized; the models of the chip U1, the chip U2, the chip U3, the chip U4, the chip U5, the chip U6, the chip U7 and the chip U8 are 74HC164; when the signal of the shift enable signal terminal CP is shifted from low level to high level, all outputs of the chips U1, U2, U3, U4, U5, U6, U7 and U8 are shifted one bit backward; the test switch module comprises an MOS switch tube, wherein a grid electrode of the MOS switch tube is connected with the high-speed silicon gate CMOS device, a source electrode of the MOS switch tube is grounded, and a drain electrode of the MOS switch tube is connected with an external device to be tested. The test switch module further comprises a filter capacitor, wherein two ends of the filter capacitor are respectively connected with the source electrode of the MOS switch tube and the drain electrode of the MOS switch tube. Specifically, under the action of the filter capacitor, interference signals can be removed, and the test result is stable.
Example two
The second embodiment of the present application differs from the first embodiment in that: the MOS switch tube may be replaced with a relay.
The present utility model is not limited to the preferred embodiments, but is intended to be limited to the following description, and any modifications, equivalent changes and variations in light of the above-described embodiments will be apparent to those skilled in the art without departing from the scope of the present utility model.
Claims (5)
1. A loop selection circuit module characterized by: the high-speed silicon gate CMOS device of each loop selection unit is provided with a shift enable signal end CP and a reset signal RST end, wherein the data input signal end DSA is used for receiving an initial signal, the shift enable signal end CP is used for controlling an output signal of the high-speed silicon gate CMOS device, and the reset signal RST end is used for eliminating output of the high-speed silicon gate CMOS device to close the test switch module.
2. A loop selection circuit module according to claim 1, characterized in that: the model of the high speed silicon gate CMOS device is 74HC164.
3. A loop selection circuit module according to claim 1, characterized in that: the high-speed silicon gate CMOS device of each loop selection unit is respectively connected with a voltage stabilizing capacitor, and the high-speed silicon gate CMOS device of each loop selection unit is grounded through the voltage stabilizing capacitor.
4. A loop selection circuit module according to claim 3, characterized in that: the test switch module comprises an MOS switch tube, wherein a grid electrode of the MOS switch tube is connected with the high-speed silicon gate CMOS device, a source electrode of the MOS switch tube is grounded, and a drain electrode of the MOS switch tube is connected with an external device to be tested.
5. The loop selection circuit module of claim 4, wherein: the test switch module further comprises a filter capacitor, wherein two ends of the filter capacitor are respectively connected with the source electrode of the MOS switch tube and the drain electrode of the MOS switch tube.
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221261114U true CN221261114U (en) | 2024-07-02 |
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