CN113589148A - Multi-channel power panel for chip testing field - Google Patents
Multi-channel power panel for chip testing field Download PDFInfo
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- CN113589148A CN113589148A CN202110946570.XA CN202110946570A CN113589148A CN 113589148 A CN113589148 A CN 113589148A CN 202110946570 A CN202110946570 A CN 202110946570A CN 113589148 A CN113589148 A CN 113589148A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a multi-channel power panel used in the field of chip testing; the power supply comprises a circuit card board, wherein the circuit card board comprises a main board and four sub-boards, the main board comprises an FPGA chip, a power supply conversion circuit, an output current sampling circuit, an EEPROM (electrically erasable programmable read-only memory) and a communication chip, and the sub-boards comprise a voltage current output circuit, a voltage current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit; the invention uses 1 FPGA board card and software algorithm to achieve the function of adding digital multimeter to the power supply of a plurality of standard instruments; the function of source and sink is provided; 40 channels and can be independently controlled; the output voltage is controllable from-10V to +10V, and the resolution reaches 1 mV; output voltage precision: < 0.05%, output voltage measurement accuracy: < 0.05%; the output current is controllable from-1A to + 1A; the output current measurement precision; supporting communication control.
Description
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a multi-channel power panel used in the field of chip testing.
Background
An Integrated Circuit (IC) is abbreviated; or microcircuits (microcircuits), microchips (microchips), and chips (chips) are a way to miniaturize circuits (mainly including semiconductor devices, including passive components, etc.) in electronics, and are often fabricated on the surface of semiconductor wafers. By the middle and late 20 th century, semiconductor manufacturing technology advances, making integrated circuits possible. It is a great advance that integrated circuits can integrate a very large number of micro-transistors into a single small chip, as opposed to manually assembling the circuits using individual discrete electronic components. The integrated circuit has two main advantages for discrete transistors, namely, the mass production capacity, the reliability and the modularization method of circuit design ensure that a standardized integrated circuit is rapidly adopted to replace the discrete transistor used by design: cost and performance. The cost is low because the chip prints all the components as a unit by photolithography, rather than making only one transistor at a time. The high performance is due to the components switching fast, consuming less energy, because the components are small and close to each other. In the field of chip testing, a power supply which is multi-channel, high in precision and supports programming control is required to be used under many scenes, however, various testing power supplies in the market still have various problems.
For example, the publication No. CN112630678A discloses a testing system for a motherboard core power supply, which solves the problem that the quality test of the domestic large-current chip core power supply is not accurate due to the absence of a hardware environment for specially testing the quality of the domestic large-current chip core power supply at the present stage, but does not solve the problem that the existing low-power supply module has power output channels generally smaller than or equal to 16; the power supply generally only has the problem of source function, and therefore a multi-channel power supply board used in the field of chip testing is provided.
Disclosure of Invention
The present invention is directed to a multi-channel power board for use in the field of chip testing, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a multi-channel power panel used in the field of chip testing comprises a circuit panel, wherein the circuit panel comprises a main panel and four sub-panels, the main panel comprises an FPGA chip, a power supply conversion circuit, an output current sampling circuit, an EEPROM and a communication chip, and the sub-panels comprise a voltage current output circuit, a voltage current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit;
the power supply conversion circuit is electrically connected with the FPGA chip, the power supply conversion circuit is electrically connected with an output current sampling circuit, the output current sampling circuit is electrically connected with the FPGA chip, and the FPGA chip is electrically connected with the EEPROM and the communication chip;
the rear side of the voltage and current output circuit is electrically connected with the voltage and current clamping circuit, the rear side of the voltage and current clamping circuit is electrically connected with the power operational amplifier circuit, and the current feedback circuit and the voltage feedback circuit are electrically connected with the voltage and current clamping circuit;
the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, the 16-bit DAC conversion circuit, the 16-bit ADC conversion circuit and the amplifying circuit;
the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip;
the FPGA chip defines and controls the power supply conversion circuit, external signals and internal control signals are processed and controlled and give out instructions through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8_ F, a clock active crystal oscillator U6_ F, a storage chip U9_ F for storing calibration data and a storage chip U10_ F;
each power output measuring circuit is divided into 6 ranges according to the current, a measuring instruction is received through the FPGA chip, the relay of the corresponding circuit is controlled to be attracted, and the voltage at two ends of the sampling resistor is measured to realize current measurement;
the SS1 end of the voltage and current output circuit is the voltage of the Sense end of the power supply, the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1, and a reference level is provided for subsequent voltage regulation and the voltage and current clamping circuit;
the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a mainboard sampling resistor, and the voltages are output to the IFB1 after passing through an operational amplifier and a differential amplifier so as to provide reference levels for subsequent voltage regulation and the voltage and current clamping circuit;
the U11_1 chips of the current feedback circuit and the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to a pin FMODEL1 for clamping, and a clamp1 signal and a fb1 signal are output to the clamping circuit;
the input ends of VF1 and fb1 of the voltage and current clamping circuit output AZ1, the clamping circuit part, feedback voltage and the divided voltage of the clamping voltage through an adder and a reverse circuit to serve as AD712 input ends, when the voltage is greater than 0, the divided voltage is output to be +15V after passing through U2_1A, a diode D2_1 is conducted, the voltage of a pin 3 of U2_1A is clamped to be 0V all the time, when the voltage is less than 0, the divided voltage is output to be-15V after passing through U2_1B, a diode D3_1 is conducted, and the voltage of a pin 3 of U2_1B is clamped to be 0V all the time;
the integrated circuit board voltage output setting circuit and the clamp setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamp voltage is controlled, 2 power outputs are controlled through each chip, and 10 power controls are achieved through 5 DAC chips for the daughter board.
Preferably, the power conversion circuit includes a group of 24V voltage conversion circuits, a group of 15V voltage conversion circuits, three groups of filter circuits, and a group of voltage reduction circuits.
Preferably, the 24V voltage conversion circuit and the 15V voltage conversion circuit include four sets of electrolytic capacitors and four sets of capacitor strings connected together, two sets of induction coils are connected between the four sets of electrolytic capacitors and the four sets of capacitors, the three sets of filter circuits include two sets of electrolytic capacitors and two sets of capacitor strings connected together, the induction coils are electrically connected between the two sets of electrolytic capacitors and the two sets of capacitors, the voltage reduction circuit includes a voltage reduction chip AMS 1117-33, and two sides of the voltage reduction chip AMS 1117-33 are electrically connected with two sets of capacitors, one set of electrolytic capacitors and one set of resistors.
Preferably, the communication chip is provided with six groups, capacitors are respectively and electrically connected to one pin and twenty-four pins on two sides of the communication chip, two pins of the four groups of communication chips are electrically connected to the capacitors on the pins through resistors, and the twenty-four pins are electrically connected to the twenty-three pins.
Preferably, the power output measuring circuit comprises a TP1C6B273 chip, the CLK and CLR pins of the TP1C6B273 chip are electrically connected with a resistor, two sets of resistors are electrically connected, the CLR pin is also electrically connected with a capacitor, and the VCC pin of the TP1C6B273 chip is also electrically connected with a capacitor.
Preferably, the voltage-current output circuit comprises an INA105U gain differential amplifier chip and a plurality of operational amplifiers, two sides of the INA105U gain differential amplifier chip are respectively and electrically connected with three operational amplifiers, and one of the operational amplifiers is connected with one operational amplifier in series.
Preferably, the output current sampling circuit comprises an INA149aid differential operational amplifier chip and a plurality of operational amplifiers, and two sides of the INA149aid differential operational amplifier chip are respectively and electrically connected with three operational amplifiers.
8. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the current feedback circuit and the voltage feedback circuit adopt ADG453BRZ multiplexers.
Preferably, the test system further comprises a program control time sequence of the board card, wherein the program control time sequence comprises a read-write command of the tester, the read-write command of the tester is transmitted to the FPGA chip, and the FPGA chip decodes the read-write command of the tester through an address.
Preferably, the read-write command of the decoding tester comprises an inquiry board card command, a mode setting command, a voltage applying command, a clamping voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM write data command and a ROM read data command.
Compared with the prior art, the invention has the beneficial effects that:
1. 1 FPGA board card and a software algorithm are used for achieving the functions of a plurality of standard instrument power supplies and a digital multimeter;
2. the function of source and sink is provided;
3.40 channels and can be independently controlled;
4. the output voltage is controllable from-10V to +10V, and the resolution reaches 1 mV;
5. output voltage precision: < 0.05%, output voltage measurement accuracy: < 0.05%;
6. the output current is controllable from-1A to + 1A;
7. output current measurement accuracy:
-40uA to+40uA@20nA@±0.2％
-400uA to+400uA@200nA@±0.2％
-4mA to+4mA@2uA@±0.2％
-40mA to+40mA@20uA@±0.2％
-400mA to+400mA@200uA@±0.1％
-1A to+1A@800uA@±0.2％；
8. supporting communication control.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a circuit diagram of a power conversion circuit of the present invention;
FIG. 3 is a circuit diagram of a communication chip according to the present invention;
FIG. 4 is a circuit diagram of an FPGA chip and its external circuitry of the present invention;
FIG. 5 is a circuit diagram of a power output measurement circuit of the present invention;
FIG. 6 is a circuit diagram of the voltage-current output circuit of the present invention;
FIG. 7 is a circuit diagram of an output current sampling circuit of the present invention;
FIG. 8 is a circuit diagram of the current feedback circuit and the voltage feedback circuit of the present invention;
FIG. 9 is a circuit diagram of a voltage current clamp circuit of the present invention;
FIG. 10 is a circuit diagram of the board voltage output setting circuit and clamp setting circuit of the present invention;
fig. 11 is a schematic diagram illustrating a program control timing of the board FPGA according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 11, the present invention provides a technical solution: a multi-channel power panel used in the field of chip testing comprises a circuit panel, wherein the circuit panel comprises a main panel and four sub-panels, the main panel comprises an FPGA chip, a power supply conversion circuit, an output current sampling circuit, an EEPROM and a communication chip, and the sub-panels comprise a voltage current output circuit, a voltage current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit;
the power supply conversion circuit is electrically connected with the FPGA chip, the power supply conversion circuit is electrically connected with an output current sampling circuit, the output current sampling circuit is electrically connected with the FPGA chip, and the FPGA chip is electrically connected with the EEPROM and the communication chip;
the rear side of the voltage and current output circuit is electrically connected with the voltage and current clamping circuit, the rear side of the voltage and current clamping circuit is electrically connected with the power operational amplifier circuit, and the current feedback circuit and the voltage feedback circuit are electrically connected with the voltage and current clamping circuit;
the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, the 16-bit DAC conversion circuit, the 16-bit ADC conversion circuit and the amplifying circuit;
the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip;
the FPGA chip defines and controls the power supply conversion circuit, external signals and internal control signals are processed and controlled and give out instructions through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8_ F, a clock active crystal oscillator U6_ F, a storage chip U9_ F for storing calibration data and a storage chip U10_ F;
each power output measuring circuit is divided into 6 ranges according to the current, a measuring instruction is received through the FPGA chip, the relay of the corresponding circuit is controlled to be attracted, and the voltage at two ends of the sampling resistor is measured to realize current measurement;
the SS1 end of the voltage and current output circuit is the voltage of the Sense end of the power supply, the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1, and a reference level is provided for subsequent voltage regulation and the voltage and current clamping circuit;
the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a mainboard sampling resistor, and the voltages are output to the IFB1 after passing through an operational amplifier and a differential amplifier so as to provide reference levels for subsequent voltage regulation and the voltage and current clamping circuit;
the U11_1 chips of the current feedback circuit and the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to a pin FMODEL1 for clamping, and a clamp1 signal and a fb1 signal are output to the clamping circuit;
the input ends of VF1 and fb1 of the voltage and current clamping circuit output AZ1, the clamping circuit part, feedback voltage and the divided voltage of the clamping voltage through an adder and a reverse circuit to serve as AD712 input ends, when the voltage is greater than 0, the divided voltage is output to be +15V after passing through U2_1A, a diode D2_1 is conducted, the voltage of a pin 3 of U2_1A is clamped to be 0V all the time, when the voltage is less than 0, the divided voltage is output to be-15V after passing through U2_1B, a diode D3_1 is conducted, and the voltage of a pin 3 of U2_1B is clamped to be 0V all the time;
the integrated circuit board voltage output setting circuit and the clamp setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamp voltage is controlled, 2 power outputs are controlled through each chip, and 10 power controls are achieved through 5 DAC chips for the daughter board.
In order to realize stable power supply operation of the system, so that the voltage is stable, in the present embodiment, it is preferable that, the power conversion circuit comprises a group of 24V voltage conversion circuits, a group of 15V voltage conversion circuits, three groups of filter circuits and a group of voltage reduction circuits, the 24V voltage conversion circuit and the 15V voltage conversion circuit comprise four groups of electrolytic capacitors and four groups of capacitors connected in series, two groups of induction coils are connected between the four groups of electrolytic capacitors and the four groups of capacitors, the three groups of filter circuits comprise two groups of electrolytic capacitors and two groups of capacitors connected in series, the two groups of electrolytic capacitors and the two groups of capacitors are electrically connected with the induction coils, the voltage reduction circuit comprises a voltage reduction chip AMS 1117-33, and two sides of the voltage reduction chip AMS 1117-33 are electrically connected with two groups of capacitors, a group of electrolytic capacitors and a group of resistors.
In order to realize data information transmission for communication, in this embodiment, it is preferable that the communication chip has six groups, and one pin and twenty-four pins on two sides of the communication chip are respectively and electrically connected with a capacitor, and two pins of the four groups of communication chips are electrically connected with the capacitors on the pins through resistors, and the twenty-four pins are electrically connected with the twenty-three pins.
In order to implement effective measurement on an output circuit and maintain the stability of the circuit voltage, in this embodiment, it is preferable that the power output measurement circuit includes a TP1C6B273 chip, the CLK and CLR pins of the TP1C6B273 chip are electrically connected with resistors respectively, the two sets of resistors are electrically connected, the CLR pin is also electrically connected with a capacitor, and the VCC pin of the TP1C6B273 chip is also electrically connected with a capacitor.
In order to detect the voltage and the current of the circuit, facilitate control and adjustment, and improve the accuracy of data and facilitate acquisition and use, in this embodiment, preferably, the voltage and current output circuit includes an INA105U gain differential amplifier chip and a plurality of operational amplifiers, two sides of the INA105U gain differential amplifier chip are respectively and electrically connected with three operational amplifiers, and one of the operational amplifiers is connected in series with one operational amplifier.
In order to detect the output current and improve the data sampling performance, in this embodiment, preferably, the output current sampling circuit includes an INA149AIDR differential operational amplifier chip and a plurality of operational amplifiers, and two sides of the INA149AIDR differential operational amplifier chip are electrically connected to three operational amplifiers respectively.
In order to realize effective selective on/off of the data information of the current feedback and the voltage feedback, in this embodiment, it is preferable that an ADG453BRZ multiplexer is used for the current feedback circuit and the voltage feedback circuit.
In order to implement the programmed control adjustment of the board card, in this embodiment, it is preferable that the method further includes a program control sequence of the board card, where the program control sequence includes a read-write command of the tester, the read-write command of the tester is transmitted to the FPGA chip, the FPGA chip reads the read-write command through an address decoding tester, and the read-write command of the decoding tester includes a query board card command, a mode setting command, a voltage application command, a clamp voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM write data command, and a ROM read data command.
The working principle and the using process of the invention are as follows: the test machine read-write command is transmitted to the FPGA chip, the FPGA chip decodes the test machine read-write command through an address, the decoding test machine read-write command comprises an inquiry board card command, a mode setting command, a voltage applying command, a clamping voltage command, a measurement selection command, a measurement command, a read-write data command, a ROM data writing command and a ROM data reading command, then the board card runs, and the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, 16-bit DAC conversion, 16-bit ADC conversion and amplification circuit; the communication chip receives an external communication signal and transmits the external communication signal into the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip; the FPGA chip defines and controls the power supply conversion circuit, external signals and internal control signals are processed and controlled and give out instructions through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8_ F, a clock active crystal oscillator U6_ F, a storage chip U9_ F for storing calibration data and a storage chip U10_ F; each power output measuring circuit is divided into 6 ranges according to the current, a measuring instruction is received through an FPGA chip, a relay of the corresponding circuit is controlled to be closed, and the voltage at two ends of the sampling resistor is measured to realize current measurement; the SS1 end of the voltage and current output circuit is the voltage of the Sense end of the power supply, the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1, and a reference level is provided for the subsequent voltage regulation and voltage and current clamping circuit; the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a mainboard sampling resistor, and the voltages are output to the IFB1 after passing through an operational amplifier and a differential amplifier to provide reference levels for a subsequent voltage regulation and voltage current clamping circuit; the U11_1 chip of the current feedback circuit and the voltage feedback circuit selects current for a feedback mode, selects voltage or current for clamping according to the pin FMODEL1, and outputs a clamp1 signal and a fb1 signal to the clamping circuit; the input ends of VF1 and fb1 of the voltage and current clamp circuit output AZ1, the clamp circuit part, feedback voltage and the divided voltage of the clamp voltage as an AD712 input end through an adder and a reverse circuit, when the voltage is greater than 0, the divided voltage is output to be +15V after passing through U2_1A, a diode D2_1 is conducted, the voltage of a pin 3 of U2_1A is clamped to be 0V all the time, when the voltage is less than 0, the divided voltage is output to be-15V after passing through U2_1B, a diode D3_1 is conducted, and the voltage of the pin 3 of U2_1B is clamped to be 0V all the time; the integrated circuit board voltage output setting circuit and the clamp setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamp voltage is controlled, each chip controls 2 paths of power supply output, and each daughter board realizes 10 paths of power supply control through 5 DAC chips.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. The utility model provides a multichannel power strip for chip test field, includes the circuit cardboard, its characterized in that: the circuit card board comprises a main board and four sub-boards, wherein the main board comprises an FPGA chip, a power supply conversion circuit, an output current sampling circuit, an EEPROM and a communication chip, and the sub-boards comprise a voltage current output circuit, a voltage current clamping circuit, a power operational amplifier circuit, a current feedback circuit and a voltage feedback circuit;
the power supply conversion circuit is electrically connected with the FPGA chip, the power supply conversion circuit is electrically connected with an output current sampling circuit, the output current sampling circuit is electrically connected with the FPGA chip, and the FPGA chip is electrically connected with the EEPROM and the communication chip;
the rear side of the voltage and current output circuit is electrically connected with the voltage and current clamping circuit, the rear side of the voltage and current clamping circuit is electrically connected with the power operational amplifier circuit, and the current feedback circuit and the voltage feedback circuit are electrically connected with the voltage and current clamping circuit;
the power supply conversion circuit is used for converting an external input power supply into a power supply of the internal FPGA chip, the 16-bit DAC conversion circuit, the 16-bit ADC conversion circuit and the amplifying circuit;
the communication chip receives an external communication signal and transmits the external communication signal to the FPGA chip so as to realize external communication, and the communication chip adopts a bidirectional transceiver 74LVC4245 chip;
the FPGA chip defines and controls the power supply conversion circuit, external signals and internal control signals are processed and controlled and give out instructions through the FPGA chip, and the FPGA chip further comprises a peripheral FPGA program downloading interface U8_ F, a clock active crystal oscillator U6_ F, a storage chip U9_ F for storing calibration data and a storage chip U10_ F;
each power output measuring circuit is divided into 6 ranges according to the current, a measuring instruction is received through the FPGA chip, the relay of the corresponding circuit is controlled to be attracted, and the voltage at two ends of the sampling resistor is measured to realize current measurement;
the SS1 end of the voltage and current output circuit is the voltage of the Sense end of the power supply, the voltage is output to the VFB1 end through the operational amplifier and the differential amplifier U5_1, and a reference level is provided for subsequent voltage regulation and the voltage and current clamping circuit;
the IBEF1 and IAF1 ends of the output current sampling circuit are voltages at two ends of a mainboard sampling resistor, and the voltages are output to the IFB1 after passing through an operational amplifier and a differential amplifier so as to provide reference levels for subsequent voltage regulation and the voltage and current clamping circuit;
the U11_1 chips of the current feedback circuit and the voltage feedback circuit are used for selecting current for a feedback mode, selecting voltage or current is set according to a pin FMODEL1 for clamping, and a clamp1 signal and a fb1 signal are output to the clamping circuit;
the input ends of VF1 and fb1 of the voltage and current clamping circuit output AZ1, the clamping circuit part, feedback voltage and the divided voltage of the clamping voltage through an adder and a reverse circuit to serve as AD712 input ends, when the voltage is greater than 0, the divided voltage is output to be +15V after passing through U2_1A, a diode D2_1 is conducted, the voltage of a pin 3 of U2_1A is clamped to be 0V all the time, when the voltage is less than 0, the divided voltage is output to be-15V after passing through U2_1B, a diode D3_1 is conducted, and the voltage of a pin 3 of U2_1B is clamped to be 0V all the time;
the integrated circuit board voltage output setting circuit and the clamp setting circuit are composed of DAC chips, VF output is controlled through the DAC chips, clamp voltage is controlled, 2 power outputs are controlled through each chip, and 10 power controls are achieved through 5 DAC chips for the daughter board.
2. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the power conversion circuit comprises a group of 24V voltage conversion circuits, a group of 15V voltage conversion circuits, three groups of filter circuits and a group of voltage reduction circuits.
3. The multi-channel power panel used in the chip testing field as claimed in claim 2, wherein: the 24V voltage conversion circuit and the 15V voltage conversion circuit comprise four groups of electrolytic capacitors and four groups of capacitor strings which are connected, two groups of induction coils are connected between the four groups of electrolytic capacitors and the four groups of capacitors, the three groups of filter circuits comprise two groups of electrolytic capacitors and two groups of capacitor strings which are connected, the induction coils are electrically connected between the two groups of electrolytic capacitors and the two groups of capacitors, the voltage reduction circuit comprises a voltage reduction chip AMS 1117-33, and two sides of the voltage reduction chip AMS 1117-33 are electrically connected with two groups of capacitors, one group of electrolytic capacitors and one group of resistors.
4. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the communication chip is provided with six groups, capacitors are respectively and electrically connected to one pin and twenty-four pins on two sides of the communication chip, two pins of the four groups of communication chips are electrically connected with the capacitors on the pins through resistors, and the twenty-four pins are electrically connected with the twenty-three pins.
5. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the power output measuring circuit comprises a TP1C6B273 chip, wherein resistors and two sets of resistors are electrically connected to CLK and CLR pins of the TP1C6B273 chip respectively, a capacitor is electrically connected to the CLR pins, and a capacitor is also electrically connected to the VCC pins of the TP1C6B273 chip.
6. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the voltage and current output circuit comprises an INA105U gain differential amplifier chip and a plurality of operational amplifiers, wherein three operational amplifiers are respectively and electrically connected to two sides of the INA105U gain differential amplifier chip, and one operational amplifier is connected in series with one operational amplifier.
7. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the output current sampling circuit comprises an INA149AIDR differential operational amplifier chip and a plurality of operational amplifiers, wherein two sides of the INA149AIDR differential operational amplifier chip are respectively and electrically connected with three operational amplifiers.
8. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the current feedback circuit and the voltage feedback circuit adopt ADG453BRZ multiplexers.
9. The multi-channel power panel used in the chip testing field according to claim 1, wherein: the test device also comprises a program control time sequence of the board card, wherein the program control time sequence comprises a read-write command of the test machine, the read-write command of the test machine is transmitted to the FPGA chip, and the FPGA chip decodes the read-write command of the test machine through an address.
10. The multi-channel power panel for the chip testing field as claimed in claim 9, wherein: the reading and writing commands of the decoding tester comprise a query board card command, a mode setting command, a voltage applying command, a clamping voltage command, a measurement selection command, a measurement command, a reading and writing data command, a ROM (read only memory) data writing command and a ROM data reading command.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110946570.XA CN113589148B (en) | 2021-08-18 | 2021-08-18 | A multichannel power strip for chip test field |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110946570.XA CN113589148B (en) | 2021-08-18 | 2021-08-18 | A multichannel power strip for chip test field |
Publications (2)
| Publication Number | Publication Date |
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| CN113589148A true CN113589148A (en) | 2021-11-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999421A (en) * | 1999-03-31 | 1999-12-07 | Liu; Kwang H. | Dual-channel power system with an eight-pin PWM control chip |
| US20190353698A1 (en) * | 2018-05-21 | 2019-11-21 | National Instruments Corporation | Over-the-Air Testing of Millimeter Wave Integrated Circuits with Integrated Antennas |
| CN110857959A (en) * | 2018-08-24 | 2020-03-03 | 西安恩狄集成电路有限公司 | Chip reset test board and test method |
| CN211239813U (en) * | 2020-01-21 | 2020-08-11 | 合肥本源量子计算科技有限责任公司 | Multi-channel voltage source |
| CN112114246A (en) * | 2020-09-22 | 2020-12-22 | 杭州长川科技股份有限公司 | Adjustable power supply of integrated circuit test board and integrated circuit test board |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999421A (en) * | 1999-03-31 | 1999-12-07 | Liu; Kwang H. | Dual-channel power system with an eight-pin PWM control chip |
| US20190353698A1 (en) * | 2018-05-21 | 2019-11-21 | National Instruments Corporation | Over-the-Air Testing of Millimeter Wave Integrated Circuits with Integrated Antennas |
| CN110857959A (en) * | 2018-08-24 | 2020-03-03 | 西安恩狄集成电路有限公司 | Chip reset test board and test method |
| CN211239813U (en) * | 2020-01-21 | 2020-08-11 | 合肥本源量子计算科技有限责任公司 | Multi-channel voltage source |
| CN112114246A (en) * | 2020-09-22 | 2020-12-22 | 杭州长川科技股份有限公司 | Adjustable power supply of integrated circuit test board and integrated circuit test board |
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