CN113582130A - Method for preparing MEMS device based on wafer - Google Patents
Method for preparing MEMS device based on wafer Download PDFInfo
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- CN113582130A CN113582130A CN202110851379.7A CN202110851379A CN113582130A CN 113582130 A CN113582130 A CN 113582130A CN 202110851379 A CN202110851379 A CN 202110851379A CN 113582130 A CN113582130 A CN 113582130A
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000010410 layer Substances 0.000 claims abstract description 282
- 238000005530 etching Methods 0.000 claims abstract description 61
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000011241 protective layer Substances 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims description 69
- 239000000463 material Substances 0.000 claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000012528 membrane Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 87
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0128—Processes for removing material
- B81C2201/013—Etching
Abstract
The invention provides a method for preparing an MEMS device based on a wafer. By arranging the protective layer between the mask layer and the second surface of the wafer, the protective layer can be used for protecting the wafer from etching attack of xenon fluoride gas after the mask layer is consumed, the phenomenon that the edge of the wafer is exposed prematurely and corroded by the xenon fluoride gas is avoided, the integrity of the MEMS device located at the edge of the wafer is effectively guaranteed, and the yield of the MEMS device on the wafer is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for preparing an MEMS device based on a wafer.
Background
In the semiconductor field, wafer-based device processing is a common process, such as performing processing of MEMS devices based on wafers. In the wafer processing process of the MEMS device, a plurality of etching processes are often performed to form a cavity and a back cavity of the MEMS device, but in each etching process, the edge of the wafer is particularly vulnerable to a large etching attack, so that the edge of the wafer is easily damaged, and at this time, the MEMS device at the edge of the wafer is correspondingly affected, which greatly affects the yield of the finished product of the MEMS device in the wafer.
Disclosure of Invention
The invention aims to provide a method for preparing an MEMS device based on a wafer, which aims to solve the problem that the edge of the wafer is easily lost in the existing preparation process.
In order to solve the above technical problem, the present invention provides a method for manufacturing an MEMS device based on a wafer, comprising: providing a wafer, wherein a plurality of device areas are defined on the wafer, a first sacrificial layer, a vibrating membrane, a second sacrificial layer and a back plate are sequentially formed on the first surface of the wafer of at least part of the device areas, and a polycrystalline silicon barrier layer is arranged between the first sacrificial layer and the vibrating membrane; forming a protective layer and a mask layer on the second surface of the wafer in at least part of the device area, wherein the mask layer covers the protective layer and defines a back cavity area of the MEMS device, and the wafer is etched by taking the mask layer as a mask to form a back cavity which exposes the first sacrificial layer; executing a first sacrificial layer release process to remove the exposed first sacrificial layer and further expose the polysilicon barrier layer; etching the polysilicon barrier layer by using an etching gas containing xenon fluoride, wherein the etching gas containing xenon fluoride also completely consumes the mask layer and exposes the protective layer; a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer, and also to remove the protective layer.
In the method for preparing the MEMS device based on the wafer, provided by the invention, a protective layer is also arranged between the mask layer and the second surface of the wafer, and the protective layer can be still maintained after the mask layer is consumed so as to protect the wafer from the etching attack of the xenon fluoride gas. Particularly, when the mask layer is consumed a lot at the edge of the wafer due to the poor etching uniformity of the previous etching process (e.g., the first sacrificial layer release process), the mask layer is allowed to be consumed a lot at the edge of the wafer due to the protection layer laid in the invention, and the wafer can be prevented from being exposed prematurely and corroded by the xenon fluoride gas. Therefore, the integrity of the MEMS device at the edge position of the wafer is guaranteed, and the yield of the MEMS device on the wafer is improved.
Drawings
Fig. 1-4 are schematic structural diagrams of a process for manufacturing a MEMS device based on a wafer.
Fig. 5 is a flow chart illustrating a method for wafer-based fabrication of MEMS devices in an embodiment of the invention.
Fig. 6-10 are schematic structural diagrams illustrating a process for fabricating a MEMS device based on a wafer according to an embodiment of the present invention.
Wherein the reference numbers are as follows: 10/100-wafer; 20/200-a diaphragm; 210-a first insulating layer; 220-a first conductive layer; 230-a second insulating layer; 30/300-back plate; 310-a second conductive layer; 320-a third insulating layer; 400-a protective layer; 51/510-first sacrificial layer; 52/520-second sacrificial layer; 60/600-mask layer; 70-a barrier layer; 710-a first barrier layer; 720-a second barrier layer; 730-third barrier layer.
Detailed Description
As described in the background, when MEMS devices are fabricated on a wafer, a lot of wear of the edge of the wafer often occurs, and the performance of the MEMS devices on the edge of the wafer is affected. For example, referring to fig. 1-4, a specific process of damaging the edge of a wafer during its processing is explained as follows.
Referring first to fig. 1, a wafer 10 is provided, and a first sacrificial layer 51, a diaphragm 20, a second sacrificial layer 52 and a back plate 30 are sequentially formed on a first surface of at least a part of a device region of the wafer 10.
With continued reference to fig. 1, a mask layer 60 is formed on the second surface of the wafer 10, the mask layer 60 defining a back cavity region in the device region. And etching the wafer 10 from the back side of the wafer 10 with the mask layer 60 as a mask to form a back cavity exposing the first sacrificial layer 51.
Next, referring to fig. 2, a first sacrificial layer release process is performed to remove the first sacrificial layer 51. As shown in fig. 2, a barrier layer 70 is further disposed between the first sacrificial layer 51 and the diaphragm 20 for preventing the diaphragm 20 from being corroded when the first sacrificial layer 51 is etched. Therefore, after the first sacrificial layer 51 is removed, the barrier layer 70 is exposed.
It should be noted that, in the first sacrificial layer releasing process, the etchant may also slightly attack the mask layer 60, and in the case that the etching uniformity in the first sacrificial layer releasing process is poor, the etchant may consume the mask layer 60 unevenly. In particular, the wafer 10 is typically more strongly attacked by the etch in its edge region, resulting in greater consumption of the mask layer 60 in the edge region of the wafer.
Referring next to fig. 3, the barrier layer 70 is removed using an etching gas comprising xenon fluoride. This etching process adds to the loss of the mask layer 60 and the edge region of the wafer prematurely exposes the wafer 10, and the exposed wafer 10 is substantially eroded by the xenon fluoride-containing etching gas, resulting in the missing bottom corner of the wafer edge and the formation of a pit.
Referring next to fig. 4, a second sacrificial layer releasing process is performed to remove the second sacrificial layer 52 between the diaphragm 20 and the backplate 30, so that the diaphragm 20 can be released to perform its vibration function.
It will be appreciated that the etchant from the second sacrificial layer release process tends to collect in the pits at the bottom corner locations of the wafer edge, thereby exacerbating the problem of missing bottom corners at the wafer edge with a corresponding impact on the MEMS devices at the edge locations.
Therefore, the invention provides an improved scheme for preventing the edge of the wafer from being corroded to influence the device yield of the edge position. Referring specifically to fig. 5, a method for fabricating a MEMS device based on a wafer according to the present invention includes the following steps.
Step S100, providing a wafer, and sequentially forming a first sacrificial layer, a vibrating membrane, a second sacrificial layer and a back plate on the first surface of the wafer in at least part of the device area, wherein a polycrystalline silicon barrier layer is further arranged between the first sacrificial layer and the vibrating membrane.
Step S200, forming a protective layer and a mask layer on the second surface of the wafer in at least part of the device area, wherein the mask layer covers the protective layer and defines a back cavity area of the MEMS device, and etching the wafer by taking the mask layer as a mask to form a back cavity which exposes the first sacrificial layer.
Step S300, a first sacrificial layer release process is performed to remove the exposed first sacrificial layer and further expose the polysilicon barrier layer.
Step S400, etching the polysilicon barrier layer by using etching gas containing xenon fluoride, wherein the mask layer is completely consumed by the etching gas containing xenon fluoride, and the protective layer is exposed.
Step S500, a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer, and also to remove the protective layer.
The method for fabricating a MEMS device based on a wafer according to the present invention is further described in detail with reference to fig. 6-10 and the specific embodiment. Fig. 6-10 are schematic structural diagrams of a process for manufacturing a MEMS device based on a wafer according to an embodiment of the present invention, and it should be understood that the drawings only schematically show an edge portion of the wafer. It is also to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. And relative terms such as "above," "below," "top," "bottom," "above," and "below" as may be used in the figures, may be used to describe various elements' relationships to each other. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
In step S100, referring to fig. 6 in particular, a wafer 100 is provided, where a plurality of device regions are defined on the wafer 100, and at least some of the device regions are used for forming a MEMS device. The wafer 100 is, for example, a silicon wafer. And, the MEMS device may specifically be a MEMS microphone device.
With continued reference to fig. 6, in at least a portion of the device region, a first sacrificial layer 510, a diaphragm 200, a second sacrificial layer 520, and a back plate 300 are sequentially formed on the first surface of the wafer 100. Wherein the first sacrificial layer 110 and the second sacrificial layer 520 are removed in a subsequent process to release the vibration space of the vibration film 200. And, the material of the first sacrificial layer 510 and the second sacrificial layer 520 may each include silicon oxide. Further, the diaphragm 200 may specifically include a first conductive layer 220, and a first insulating layer 210 and a second insulating layer 230 located on upper and lower sides of the first conductive layer 220. The material of the first conductive layer 220 may include polysilicon, and the material of the first insulating layer 210 and the second insulating layer 230 may include silicon nitride. And the back plate 300 comprises a second conductive layer 310 and a third insulating layer 320, wherein the third insulating layer 320 is positioned on one side of the second conductive layer 310 close to the second sacrificial layer 520. The material of the second conductive layer 310 of the back plate 300 may also include polysilicon, and the material of the third insulating layer 320 may include silicon nitride.
With continued reference to fig. 6, the end of the diaphragm 200 is further formed with a support, and the support of the diaphragm 200 penetrates the first sacrificial layer 510 to abut to the first surface of the wafer 100 for supporting the diaphragm 200 after releasing the first sacrificial layer 510. In this embodiment, the end of the diaphragm 200 is bent toward the wafer 100 to penetrate the first sacrificial layer 510 and abut on the surface of the film layer under the first sacrificial layer 510.
Similar to the diaphragm 200, the end of the backplate 300 is also formed with a support, and the support of the backplate 300 penetrates the second sacrificial layer 520 to abut on the surface of the diaphragm 200 for supporting the backplate 300 after releasing the second sacrificial layer 520. In this embodiment, the end of the back plate 300 is bent toward the diaphragm 200 to penetrate the second sacrificial layer 520 and abut on the surface of the film layer below the second sacrificial layer 520. The back plate 300 is bent to the support of the vibrating membrane 200, and the third insulating layer 320 of the back plate 300 is in contact with the second insulating layer 230 of the vibrating membrane 200, so that the problem of electrical connection between the back plate 300 and the vibrating membrane 200 can be avoided.
Further, a first barrier layer 710 is further formed between the first surface of the wafer 100 and the first sacrificial layer 510, and the first barrier layer 710 may realize an etching barrier when the wafer 100 is etched to form a back cavity. The material of the first barrier layer 710 may include silicon nitride.
Furthermore, a second barrier layer 720 is formed between the first sacrificial layer 510 and the diaphragm 200, and the second barrier layer 720 can realize an etching barrier in the process of etching the first sacrificial layer 510. In this embodiment, the second barrier layer 720 is formed at least in the area of the back cavity. And the second barrier layer 720 is specifically a polysilicon barrier layer (i.e., the second barrier layer 720 of a polysilicon material), so that a larger etching selection ratio can be achieved when the first sacrificial layer 510 is etched by using a solution containing hydrofluoric acid.
In this embodiment, a third barrier layer 730 (e.g., a silicon oxide barrier layer) is further formed between the second barrier layer 720 and the diaphragm 200, and the third barrier layer 730 is used for isolating and protecting the diaphragm 200 when the second barrier layer 720 is removed. As described above, although the second barrier layer 720 formed by using polysilicon material has a larger etching selectivity with the first sacrificial layer 510 of silicon oxide material, the first insulating layer 210 of silicon nitride material is usually consumed when the second barrier layer 720 is removed by etching (for example, when the polysilicon material is etched by using xenon fluoride, silicon nitride material is also consumed), and thus, the third barrier layer 730 is provided in this embodiment. The material of the third barrier layer 730 may be the same as the material of the second sacrificial layer 520, and the third barrier layer 730 is removed at the same time as the second sacrificial layer 520 is removed.
In a specific embodiment, the third blocking layer 730 is also formed at least in the region of the back cavity, and the third blocking layer 730 further covers the sidewall of the second blocking layer 720, so that the sidewall of the second blocking layer 720 is also isolated from the diaphragm 200.
In addition, the thickness of the second barrier layer 720 and the third barrier layer 730 is much smaller than that of the first sacrificial layer 510, so that less etching is required to remove the second barrier layer 720 and the third barrier layer 730. For example, the thickness of the second barrier layer 720 is between 1000 angstroms and 1500 angstroms, and the thickness of the third barrier layer 730 is between 500 angstroms and 1000 angstroms.
In step S200, as shown in fig. 6 and 7, a protection layer 400 and a mask layer 600 are formed on the second surface of the wafer in the at least part of the device region, the mask layer 600 covers the protection layer 400 and defines a back cavity region of the MEMS device, and then the wafer is etched using the mask layer 600 as a mask to form a back cavity, where the first sacrificial layer 510 is exposed. Wherein the material of the mask layer 600 comprises silicon nitride.
It should be noted that the protection layer 400 can be used to stop etching on the protection layer 400 when the mask layer 600 is consumed during the subsequent xenon fluoride etching, so as to prevent the wafer 100 from being exposed in advance and being eroded by the xenon fluoride etchant. Based on this, the material of the protection layer 400 may be selected according to the etching rate of xenon fluoride, in this embodiment, the material of the mask layer 600 may include silicon nitride, and the material of the protection layer 400 includes silicon oxide.
Specifically, the protection layer 400 is correspondingly provided with an opening region, and the range of the opening region is greater than or equal to the range of the back cavity region. For example, when the opening region of the protection layer 400 is formed by etching under a mask based on the mask layer 600, the range of the opening region of the protection layer 400 corresponds to the range of the back cavity region; alternatively, the open region of the protection layer 400 is formed before the mask layer 600, so that the open region of the protection layer 400 may be larger than the range of the back cavity region (i.e., the boundary of the open region of the protection layer 400 is extended by a predetermined distance with respect to the boundary of the back cavity region), and thus, when the patterned mask layer 600 is formed subsequently, the mask layer 600 may also cover the side wall of the opening of the protection layer 400. The boundary of the opening region of the protection layer 400 may be extended by about 4 μm to 5 μm relative to the boundary of the back cavity region, so as to consider the alignment offset existing in the photolithography process, and ensure that the mask layer 600 does not shrink the back cavity region when covering the sidewall of the opening of the protection layer 400.
Referring next to fig. 7, the process of etching the wafer 100 to form a back cavity by using the mask layer 600 as a mask includes: firstly, a plasma etching process can be adopted to etch the exposed silicon wafer, and the etching is stopped at the first barrier layer 710; then, the exposed first barrier layer 710 is etched to further expose the first sacrificial layer 510. It should be noted that the first barrier layer 710 is formed by using a silicon nitride material, so that the mask layer 600 of the silicon nitride material is also consumed a small amount when the first barrier layer 710 is etched.
Because the first barrier layer 710 of silicon nitride material and the first sacrificial layer 510 of silicon oxide material have a larger etching selection ratio when the first barrier layer 710 is etched, the exposed first sacrificial layer 510 can be prevented from being consumed in a large amount, and the problem that the etching amount is difficult to control when the first sacrificial layer 510 is removed later is prevented.
In step S300, referring specifically to fig. 8, a first sacrificial layer release process is performed to remove the exposed first sacrificial layer 510 and further expose the second barrier layer 720 (i.e., polysilicon barrier layer). In this embodiment, at least the first sacrificial layer corresponding to the cavity back region is removed.
Specifically, the material of the first sacrificial layer 510 includes silicon oxide, and the first sacrificial layer release process may be a wet etching process (for example, buffered oxide etching solution BOE) using a hydrofluoric acid-containing solution, that is, wet etching the first sacrificial layer 510 using the hydrofluoric acid-containing etching solution. However, the etching solution containing hydrofluoric acid generally consumes the mask layer 600 (for example, the mask layer that erodes silicon nitride material) while etching the first sacrificial layer 510, and especially, the edge of the wafer 100 is more vulnerable to the high-intensity attack of the etching solution, so that the consumption of the mask layer 600 at the edge of the wafer is relatively large. That is, the consumption of the mask layer 600 is greater in the edge region of the wafer than in the middle region of the wafer.
In step S400, and with particular reference to fig. 9, the second barrier layer 720 (i.e., the polysilicon barrier layer) is etched using an etching gas containing xenon fluoride (XeF), and the etching gas containing xenon fluoride also completely consumes the mask layer 600 and exposes the protection layer 400.
In this embodiment, the polysilicon barrier layer is etched and the etching is stopped at the third barrier layer 730. And the etching gas containing the xenon fluoride also consumes the remaining mask layer 600 (e.g., the mask layer of the silicon nitride material) at the same time, so as to expose the protection layer 400, at this time, since the etching selectivity ratio of the etching gas containing the xenon fluoride to the mask layer 600 (e.g., the silicon nitride material) and the protection layer 400 (e.g., the silicon oxide material) is greater than or equal to 200:1, the protection layer 400 can still be remained on the second surface of the wafer 100. Of course, the etching gas containing xenon fluoride also has a larger etching selectivity ratio to silicon oxide materials and silicon materials, so the protective layer 400 of silicon oxide materials can better protect the silicon wafer in an isolated manner.
That is, although the mask layer 600 is consumed (especially, the mask layer 600 at the edge of the wafer is consumed earlier) by the first sacrificial layer release process and the etching gas containing xenon fluoride, the silicon wafer is not exposed after the mask layer is completely consumed, and the problem that the etching agent containing xenon fluoride further erodes the silicon wafer is avoided.
It should be noted that the mask layer 600 in this embodiment also covers the opening sidewall of the protection layer 400, and at this time, a portion of the mask layer 600 covering the opening sidewall generally has a maximum thickness in the thickness direction of the wafer, so that when the second mask layer 600 is removed by the second etching process, the mask material is generally consumed at the position of the opening sidewall. That is, the silicon wafer exposed from the sidewall of the opening of the protection layer 400 is generally exposed at or near the end of the etching process, and thus the exposed silicon wafer is not consumed.
In step S500, referring specifically to fig. 10, a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer 520 between the diaphragm 200 and the backplate 300, and also to remove the protection layer 400.
Specifically, a plurality of openings are formed in the back plate 300, and the second sacrificial layer 520 is exposed by the openings, so that the second sacrificial layer 520 can be etched by the etchant through the openings in the second sacrificial layer release process. The opening in the back plate 300 may be prepared before etching the wafer to form the back cavity, and the back plate 300 may be covered and protected during the process of sequentially etching the wafer 100, the first barrier layer 710, the first sacrificial layer 510, and the second barrier layer 720.
The second sacrificial layer release process is a dry etching process (VHF) using a hydrogen fluoride-containing gas. Compared with the wet etching process for removing the second sacrificial layer 520, the dry etching process used in the present embodiment is beneficial to overcoming the problem that the etching residues are difficult to remove.
Further, the material of the second sacrificial layer 520 may be the same as that of the protection layer 400, i.e., both may include silicon oxide, so that the second sacrificial layer 520 and the protection layer 400 may be removed simultaneously in the second sacrificial layer release process. In addition, the material of the third barrier layer 730 may also include silicon oxide, so the third barrier layer 730 may also be removed simultaneously in the second sacrificial layer release process to release the diaphragm 200.
With continued reference to fig. 10, for the device region for forming the MEMS device, the portions of the first sacrificial layer 510 and the second sacrificial layer 520 corresponding to the back cavity region are removed, and the portions of the first sacrificial layer 510 and the second sacrificial layer 520 located at the periphery of the back cavity may be remained to assist in supporting the diaphragm 200 and the backplate 300.
In summary, in the method for manufacturing a MEMS device based on a wafer as described above, even if the previous etching process (e.g., the first sacrificial layer release process) before the xenon fluoride etching is performed may cause the loss of the mask layer on the second surface of the wafer, especially, the uneven consumption of the mask layer 600 may cause the premature consumption of the mask layer 600 at the edge position of the wafer, and at this time, the wafer may not be exposed prematurely due to the existence of the protection layer, so that the great consumption of the wafer by the xenon fluoride etching gas is realized. In addition, the protective layer can be removed in the second sacrificial layer releasing process at the same time, and the process is simple.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method for preparing a MEMS device based on a wafer is characterized by comprising the following steps:
providing a wafer, wherein a plurality of device areas are defined on the wafer, a first sacrificial layer, a vibrating membrane, a second sacrificial layer and a back plate are sequentially formed on the first surface of the wafer of at least part of the device areas, and a polycrystalline silicon barrier layer is arranged between the first sacrificial layer and the vibrating membrane;
forming a protective layer and a mask layer on the second surface of the wafer in the at least partial device area, wherein the mask layer covers the protective layer and defines a back cavity area of the MEMS device, the protective layer is formed before the mask layer, so that the mask layer also covers the side wall of the protective layer close to the back cavity area, the wafer is etched by taking the mask layer as a mask to form a back cavity, and the back cavity exposes the first sacrificial layer;
executing a first sacrificial layer release process to remove the exposed first sacrificial layer and further expose the polysilicon barrier layer;
etching the polysilicon barrier layer by using an etching gas containing xenon fluoride, wherein the etching gas containing xenon fluoride also completely consumes the mask layer and exposes the protective layer;
a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer, and also to remove the protective layer.
2. The wafer-based method of fabricating a MEMS device of claim 1 wherein the first sacrificial layer release process is a wet etch process using a hydrofluoric acid containing solution.
3. The wafer-based method for fabricating a MEMS device according to claim 2, wherein the material of the mask layer comprises silicon nitride, and the mask layer is also partially consumed in the first sacrificial layer release process, and a consumption amount of the mask layer is greater in a wafer edge region than in a wafer middle region.
4. The wafer-based method for fabricating a MEMS device according to claim 1, wherein an etch selectivity of the xenon fluoride-containing etching gas to the mask layer and the protective layer is 200:1 or greater.
5. The wafer-based method of fabricating a MEMS device of claim 4, wherein the material of the mask layer comprises silicon nitride and the material of the protective layer comprises silicon oxide.
6. The wafer-based method for fabricating a MEMS device according to claim 1, wherein the second sacrificial layer releasing process is a dry etching process using a hydrogen fluoride-containing gas.
7. The wafer-based method for fabricating a MEMS device according to claim 1, wherein the material of the second sacrificial layer comprises silicon oxide, and a silicon oxide barrier layer is further formed between the polysilicon barrier layer and the diaphragm;
and exposing the silicon oxide barrier layer after removing the polysilicon barrier layer, and simultaneously removing the silicon oxide barrier layer in the second sacrificial layer release process.
8. The wafer-based method of fabricating a MEMS device of claim 7, wherein the polysilicon barrier layer is formed within the back cavity region, the silicon oxide barrier layer covering the polysilicon barrier layer proximate to the top surface of the diaphragm and also covering sidewalls of the polysilicon barrier layer.
9. The wafer-based method of fabricating a MEMS device of claim 1 wherein the polysilicon barrier layer has a thickness of 1000 to 1500 angstroms.
10. The wafer-based method of fabricating a MEMS device of claim 1, wherein the MEMS device comprises a MEMS microphone.
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