CN113555337A - Semiconductor substrate structure and forming method thereof - Google Patents

Semiconductor substrate structure and forming method thereof Download PDF

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Publication number
CN113555337A
CN113555337A CN202110587168.7A CN202110587168A CN113555337A CN 113555337 A CN113555337 A CN 113555337A CN 202110587168 A CN202110587168 A CN 202110587168A CN 113555337 A CN113555337 A CN 113555337A
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China
Prior art keywords
capacitor
input
semiconductor substrate
substrate structure
output
Prior art date
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Pending
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CN202110587168.7A
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Chinese (zh)
Inventor
黄文宏
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN202110587168.7A priority Critical patent/CN113555337A/en
Publication of CN113555337A publication Critical patent/CN113555337A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers

Abstract

The invention discloses a semiconductor substrate structure and a forming method thereof. The semiconductor substrate structure includes: a capacitor having a plurality of input-output parts extending in the same direction; and a wiring layer located over opposite ends of the plurality of input-output components, the wiring in the wiring layer being in direct contact and electrical connection with the plurality of input-output components to form a conductive path.

Description

Semiconductor substrate structure and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor substrate structure and a forming method thereof.
Background
With the development of packaging technology, various packaging structures are also developed, the overall package size is smaller and smaller, the functions are more and more, and the demand for passive devices is higher and higher.
Most of the conventional passive devices are designed by using embedded passive devices, and most of the conventional passive devices are constructed layer by using a substrate, the position of the embedded passive device is removed by using a molding technique to form a cavity, the passive device is placed in the cavity, and finally hole sealing materials are used for filling holes. This wastes engineering resources and also causes a loss of process yield. In addition, the embedded capacitors and inductors in the prior art require additional processes, so that the thickness cannot be reduced and the electrical performance is not good.
Disclosure of Invention
To address the problems in the related art, the present invention provides a semiconductor substrate structure and a method for forming the same.
The technical scheme of the invention is realized as follows:
according to an aspect of the present invention, there is provided a semiconductor substrate structure comprising: a capacitor having a plurality of input-output parts extending in the same direction; and a wiring layer located over opposite ends of the plurality of input-output components, the wiring in the wiring layer being in direct contact and electrical connection with the plurality of input-output components to form a conductive path.
In the semiconductor substrate structure, the plurality of input/output components are a plurality of conductive pillars.
In the semiconductor substrate structure, the plurality of input/output components penetrate the capacitor.
In the above semiconductor substrate structure, the wiring layer covers the capacitor.
In the above semiconductor substrate structure, the capacitor has a center line perpendicular to an extending direction of the plurality of input-output parts, and the wirings in the wiring layer are arranged symmetrically with respect to the center line of the capacitor.
In the semiconductor substrate structure, the conductive path is an inductor.
In the semiconductor substrate structure, the capacitor includes a metal core layer, and the plurality of input/output members penetrate the metal core layer.
In the above semiconductor substrate structure, the capacitor further includes electrode material layers covering opposite sides of the metal core layer.
In the above semiconductor substrate structure, a magnetic conduction layer is further included and disposed above the capacitor.
In the above semiconductor substrate structure, the capacitor further includes an additional input-output part, and the additional input-output part is a through hole.
According to an aspect of the present invention, there is also provided a method of forming a semiconductor substrate structure, comprising: forming a capacitor having a plurality of input-output components; conductive lines are plated on both ends of a plurality of input-output parts of the capacitor, and the conductive lines connect the plurality of input-output parts to form a conductive path through the capacitor.
In the above method, the capacitor is a thin film type capacitor.
In the above method, forming the capacitor includes: providing a metal core layer; a layer of electrode material is overlaid on the opposite side of the metallic core layer.
In the above method, forming the capacitor includes: a plurality of through holes are formed through the core layer and the electrode material layer.
In the above method, forming the capacitor further comprises: and forming the conductive columns in the through holes to form a plurality of input and output components.
In the above method, the capacitor has a center line perpendicular to an extending direction of the plurality of input-output parts, and the conductive lines are symmetrically arranged with respect to the center line of the capacitor.
In the above method, the conductive path is an inductor.
In the above method, forming the capacitor includes: and forming an additional input and output part which is a through hole.
In the above method, further comprising: a magnetically permeable layer is formed over the capacitor.
In the above method, after electroplating the conductive line, the method further includes: a rewiring layer is formed over the conductive lines.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present invention.
Fig. 2A shows a schematic top view of a semiconductor substrate structure according to an embodiment of the invention.
Fig. 2B is a schematic structural diagram of an inductor coil formed by a conductive path according to an embodiment of the present invention.
Fig. 3A-3F are flow diagrams of various stages of a method of forming a semiconductor substrate structure according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present invention. The semiconductor substrate structure shown in fig. 1 includes a capacitor 110. The capacitor 110 has a plurality of input-output sections 112, and the plurality of input-output sections 112 extend in the same direction (e.g., vertical direction). In some embodiments, the plurality of input-output components 112 is a plurality of conductive pillars. In other embodiments, the input-output component 112 may be any other suitable structure. The plurality of input/output parts 112 are also provided with a wiring layer 120 on opposite ends thereof, respectively. In some embodiments, the wiring layer 120 covers the capacitor 110. The wiring 122 in the wiring layer 120 is in direct contact with and electrically connected to the plurality of input-output components 112, and a conductive path may be formed through the wiring 122 in the wiring layer 120 and the plurality of input-output components 112. Therefore, the function of a passive element can be formed by electrically connecting the wiring 122 in the wiring layer 120 and the plurality of input-output parts 112.
Compared with the prior art that the passive element of the single package is embedded in the substrate, the input-output component 112 and the line 122 in the substrate are utilized to form the function of the passive element in an integrated molding manner of direct contact and electric connection, and the passive element of the single package does not exist in the substrate. The invention completes the construction of the passive element in the process of manufacturing the substrate without embedding the passive element of a single package into the substrate after the substrate is manufactured. Therefore, the process yield can be relatively high. Compared with the traditional embedded substrate, the invention saves the manufacturing process, can save the cost and increase the yield.
Fig. 2A shows a schematic top view of a semiconductor substrate structure according to an embodiment of the invention. Fig. 2B is a schematic structural diagram of an inductor coil formed by a conductive path according to an embodiment of the present invention. In some embodiments, the conductive path formed by the electrical connection of the lines 122 in the line layer 120 with the plurality of input-output components 112 may be an inductive coil of an inductor 180 (fig. 2B). Among them, the wiring 122 in the wiring layer 120 at the upper end of the input-output component 112 connects the upper ends of the adjacent input-output components 112, and the wiring 122 in the wiring layer 120 at the lower end of the input-output component 112 connects the lower ends of the adjacent input-output components 112, so that the conductive path is formed as an inductor coil of the inductor 180.
For example, in applications where filters are formed by capacitors and inductors, by integrating the capacitors and 3D inductors, better electrical performance is achieved than with conventional techniques at the same package size. In addition, since the input/output components 112 of the capacitor 110 can be electrically connected by way of the plating lines 122 to form the inductor coil required by the inductor 180, and there are no other electrical connection elements (such as Solder balls) between the input/output components 112, the problem of poor electrical performance can be effectively improved.
In some embodiments, the capacitor 110 may be a thin film type capacitor. A plurality of input-output components 112 may extend through the capacitor 110. In the embodiment where the capacitor 110 is a thin film capacitor, since the capacitor itself needs to be fabricated with the input/output component 112 penetrating through the capacitor 110, such input/output component 112 can also be used as a part of the 3D inductor 180, thereby further improving the integration effect.
In the embodiment shown in fig. 1, the capacitor 110 further includes an additional input-output part 1121, and the additional input-output part 1121 is a through hole. The additional input-output part 1121 may function as a cathode of the capacitor 110. One of the input-output components 1122 of the input-output components 112 may serve as an anode of the capacitor 110, and one of the input-output components 1122 of the input-output components 112 may be shared by the capacitor 110 and the inductor 180.
In an embodiment where the capacitor 110 is a film type capacitor, the capacitor 110 may include a metal core layer through which the plurality of input and output parts 112 penetrate. The capacitor 110 also includes a layer of electrode material overlying the opposite side of the metallic core layer. Since the capacitor 110 has a metal core layer, the inductance value of the 3D inductor 180 may be increased to some extent.
In some embodiments, the capacitor 110 has a center line 115 perpendicular to an extending direction of the plurality of input and output parts 112, and the lines 122 in the line layer 120 are symmetrically disposed with respect to the center line 115 of the capacitor 110. Since the 3D inductor 180 is surrounded by the capacitor 110 as a center, the thickness and volume of the substrate can be effectively used, and the size in the thickness direction can be greatly reduced. It should be understood that in other embodiments, any other suitable configuration of the capacitor 110 and the inductor 180 may be implemented for the position components, and the invention is not limited in this regard.
In some embodiments, a redistribution layer 130 is disposed on a side of the line layer 120 away from the capacitor 110. Either side of the capacitor 110 may also be provided with a magnetically permeable layer 140. In the illustrated embodiment, the magnetically permeable layer 140 is specifically disposed on the redistribution layer 130 on both sides of the capacitor 110. The inductance value of the inductor can be further improved by providing the magnetically conductive layer 140.
Fig. 3A-3F are flow diagrams of various stages of a method of forming a semiconductor substrate structure according to an embodiment of the invention. First, as shown in fig. 3A, the material of the capacitor 110 is formed. In embodiments where the capacitor 110 is a film-type capacitor, the material of the capacitor 10 may be formed by providing a metallic core layer and overlaying a layer of electrode material on the opposite side of the metallic core layer.
As shown in fig. 3B, a first dielectric layer 121 is formed on the opposite side of the capacitor 110. Then, as shown in fig. 3C, a plurality of input-output parts 112 are formed through the material of the capacitor 110 and the first dielectric layer 121 to form the capacitor 110 having the plurality of input-output parts 112. In some embodiments, the step of forming the input-output component 112 may include: forming a plurality of vias through the core layer and the electrode material layer of the capacitor material and the first dielectric layer using a mechanical drilling process; conductive pillars are formed in the through holes to form a plurality of input-output components 112. In some embodiments, during this step, additional input and output components 1121 may also be formed, the additional input and output components 1121 being through holes. Among them, at least one of the input-output parts 112 may function as a cathode of the capacitor 110, and at least one of the input-output parts 112 may function as a cathode of the capacitor 110. In some embodiments, at least one of the input-output components 112 (e.g., input-output component 1122 of fig. 1) may be shared by the capacitor 110 and subsequently formed inductor.
With continued reference to fig. 3C, conductive lines (which may also be simply referred to as lines) 122 are plated on the first dielectric layer 121 at both ends of the plurality of input-output parts 112 of the capacitor 110. A first dielectric layer 121. The wiring 122 connects the plurality of input-output components 112 to form a conductive path through the capacitor 110.
As shown in fig. 3D, a second dielectric layer 131 and additional lines 139 located on the second dielectric layer 131 and interconnected with the lines 122 through vias 138 in the second dielectric layer 131 are formed over the first dielectric layer 121 and the lines 122. As shown in fig. 3E, a third dielectric layer 132 and additional lines 139 located on the third dielectric layer 132 and interconnected with the lines 139 in the second dielectric layer 131 by vias 138 in the third dielectric layer are formed over the second dielectric layer 131 and the lines. The steps shown in fig. 3D and 3E may be repeated to form a fourth dielectric layer 133 over the third dielectric layer 132 and lines and additional lines 139 on the fourth dielectric layer 133 and interconnected with the lines 139 in the third dielectric layer 132 by vias 138 in the fourth dielectric layer 133. Until a redistribution layer 130 having a predetermined number of layers is formed, as shown in fig. 3F. The redistribution layer 130 includes second to fourth dielectric layers 131, 132 and 133, and a via 133 in the second to fourth dielectric layers 131, 132 and 133 and a line 139 on the second to fourth dielectric layers 131, 132 and 133. The number of layers of the redistribution layer 130 shown in fig. 3F is merely exemplary, and any suitable configuration may be made according to the number of layers of the redistribution layer 130 in actual use.
Then, a magnetically permeable layer 140 is formed over either or both sides of the capacitor 110. The semiconductor substrate structure 100 shown in fig. 1 is formed. The resulting semiconductor substrate structure may have the beneficial effects as discussed above with respect to fig. 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A semiconductor substrate structure, comprising:
a capacitor having a plurality of input-output parts extending in the same direction;
a wiring layer over opposite ends of the plurality of input-output components, the wiring in the wiring layer in direct contact and electrical connection with the plurality of input-output components to form a conductive path.
2. The semiconductor substrate structure of claim 1, wherein the plurality of input-output features are a plurality of conductive pillars.
3. The semiconductor substrate structure of claim 1, wherein the plurality of input-output components extend through the capacitor.
4. The semiconductor substrate structure of claim 1, wherein the wiring layer covers the capacitor.
5. The semiconductor substrate structure according to claim 1, wherein the capacitor has a center line perpendicular to an extending direction of the plurality of input-output components, and the lines in the line layer are symmetrically arranged with respect to the center line of the capacitor.
6. The semiconductor substrate structure of claim 1, wherein the conductive path is an inductive coil.
7. The semiconductor substrate structure of claim 1, wherein the capacitor comprises a metallic core layer through which the plurality of input-output components extend.
8. The semiconductor substrate structure of claim 7, wherein the capacitor further comprises a layer of electrode material overlying opposite sides of the metallic core layer.
9. The semiconductor substrate structure of claim 1, further comprising a magnetically permeable layer disposed over the capacitor.
10. The semiconductor substrate structure of claim 1, wherein the capacitor further comprises an additional input-output feature, the additional input-output feature being a via.
CN202110587168.7A 2021-05-27 2021-05-27 Semiconductor substrate structure and forming method thereof Pending CN113555337A (en)

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Application Number Priority Date Filing Date Title
CN202110587168.7A CN113555337A (en) 2021-05-27 2021-05-27 Semiconductor substrate structure and forming method thereof

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CN202110587168.7A CN113555337A (en) 2021-05-27 2021-05-27 Semiconductor substrate structure and forming method thereof

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009970A (en) * 2006-01-24 2007-08-01 财团法人工业技术研究院 Multi-functional compound substrate structure
JP2008078301A (en) * 2006-09-20 2008-04-03 Fujitsu Ltd Capacitor built-in wiring board and manufacturing method thereof
CN206282838U (en) * 2016-11-07 2017-06-27 无锡吉迈微电子有限公司 The integrated encapsulation structure of passive device and active device
CN109478545A (en) * 2016-07-21 2019-03-15 高通股份有限公司 Glass substrate including passive glass equipment and semiconductor bare chip
CN112599490A (en) * 2019-10-01 2021-04-02 日月光半导体制造股份有限公司 Device structure and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009970A (en) * 2006-01-24 2007-08-01 财团法人工业技术研究院 Multi-functional compound substrate structure
JP2008078301A (en) * 2006-09-20 2008-04-03 Fujitsu Ltd Capacitor built-in wiring board and manufacturing method thereof
CN109478545A (en) * 2016-07-21 2019-03-15 高通股份有限公司 Glass substrate including passive glass equipment and semiconductor bare chip
CN206282838U (en) * 2016-11-07 2017-06-27 无锡吉迈微电子有限公司 The integrated encapsulation structure of passive device and active device
CN112599490A (en) * 2019-10-01 2021-04-02 日月光半导体制造股份有限公司 Device structure and method of manufacturing the same

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