JP2008078301A - Capacitor built-in wiring board and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost and large capacitance capacitor built-in wiring board. <P>SOLUTION: This capacitor built-in wiring board comprises a plane-type capacitor 22 constructed of a sheet base 11 located within the wiring board and whose at least one surface is metal, a dielectric layer 12 located on the metal surface of the sheet base, and a capacitor electrode layer 14 located on the dielectric layer, and has a first conductor 18 insulated from the capacitor electrode layer and reaching the metal surface of the sheet base from the surface of the wiring board, a first electrode pad 21V connected to the first conductor and located on the wiring board, a second conductor 17 passing through the sheet base and insulated from the sheet base, and a second electrode pad 21G connected to the second conductor and the capacitor electrode layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring board incorporating a capacitor, and more particularly to an interposer board including a decoupling capacitor that efficiently absorbs noise generated from an LSI operating at a high frequency, and a method for manufacturing the same.

  In an LSI operating at a high frequency, such as a computer or a communication device, in order to prevent malfunction due to switching noise, a so-called decoupling capacitor that absorbs noise is inserted in parallel to the power supply system to lower the impedance of the power supply system. The power source impedance Z is expressed by the formula (1).

Z∝V / (n * i * f) (1)
here,
Z: power supply impedance V: drive voltage n: number of elements per LSI i: switching current f: drive frequency The required impedance is drastically reduced due to the progress of low voltage LSI, high integration of elements, and high frequency. Further, the impedance of the decoupling capacitor is expressed by Expression (2).

Z = 2πfL + 1 / (2πfC) + R (2)
here,
L: Inductance of capacitor C: Capacitance of capacitor R: DC resistance of capacitor

In order to obtain a low impedance, it is necessary to reduce the inductance and increase the capacity of the decoupling capacitor. As described above, a reduction in impedance is required, and due to the progress of higher frequency devices, decoupling capacitors are also required to have a large capacity and low inductance. In particular, a decoupling capacitor at a high frequency of 100 MHz or higher is becoming a serious situation. Usually, as a decoupling capacitor, a method of arranging a multilayer ceramic capacitor around an LSI is generally used. However, when the operating frequency is increased to several hundreds of MHz, the multilayer ceramic capacitor has a large inductance and cannot cope with it.
Under such circumstances, a capacitor in which a ceramic thin film having a high dielectric constant is formed on an insulating substrate has been proposed in order to reduce the inductance of the bypass capacitor (see, for example, Patent Document 1). The thin film capacitor can use a semiconductor process and can be surface-mounted by solder bumps. Therefore, the bump pitch can be shortened and the inductance can be reduced. Moreover, a large capacity can be obtained by using a high dielectric constant ceramic thin film.
Furthermore, in order to minimize the wiring between the LSI and the capacitor, a method has been proposed in which a capacitor interposer in which a thin film capacitor is formed on an interposer having a through via is disposed between the LSI and the circuit board. In particular, a Si capacitor interposer using the same silicon (Si) as the LSI for the interposer substrate does not have a thermal expansion mismatch with the LSI (see, for example, Patent Document 2). This method is extremely effective in high-performance LSIs because it can cope with an increase in LSI size, fine pitch, and a decrease in strength due to Low-K LSI wiring insulating film.

In addition, as a thin printed wiring board with a large capacitance, a part of the surface is roughened and the surface of a metal plate having an uneven surface is covered with a dielectric film, and a conductive film is formed on the dielectric film. Layer
JP-A-11-97289 JP 2002-8942 A

  However, conventional Si capacitor interposers have problems of high manufacturing costs (particularly, formation of through vias in Si) and a smaller capacity than multilayer ceramic capacitors.

  Accordingly, an object of the present invention is to solve the above problems and provide a low-cost, large-capacity capacitor interposer and a method for manufacturing the same.

  In order to solve the above problems, according to a first aspect of the present invention, a capacitor built-in wiring board is provided. This wiring board has a planar capacitor located inside the board, and the capacitor has a sheet base material in which at least one surface is metal, a dielectric layer located on the metal surface of the sheet base material, and a dielectric And a capacitor electrode layer located on the body layer. The capacitor-embedded wiring board is also insulated from the capacitor electrode layer, connected to the first conductor from the surface of the substrate and reaching the metal surface of the sheet base, and connected to the surface of the substrate. A first electrode pad (power supply pad) located; a second conductor penetrating the sheet base material and insulated from the sheet base material; and a second conductor connected to the second conductor and the capacitor electrode 2 electrode pads (ground pads).

  In a favorable configuration example, the capacitor built-in wiring board further penetrates the wiring board, is connected to the third conductor insulated from the capacitor, and is connected to the surface of the wiring board. And a third electrode pad (signal pad) located.

  In a more preferable configuration example, an insulating layer made of an inorganic material is inserted between the capacitor electrode layer and the resin layer. With this configuration, moisture resistance can be improved.

  Large capacity at low cost with a structure that provides a conductor that penetrates the substrate containing a planar capacitor (solid electrolytic capacitor), electrically connects the front and back of the wiring board, and has pads for external connection on both sides of the through conductor. The capacitor built-in wiring board is realized.

In a second aspect of the present invention, a method for manufacturing a capacitor-embedded wiring board is provided. This manufacturing method is
(A) a step of forming a through hole at a predetermined portion of a sheet base material having a metal layer on at least one surface;
(B) forming at least a part of the metal layer of the sheet base material and then anodizing it to form a dielectric layer;
(C) forming a capacitor electrode layer on the dielectric layer to form a capacitor structure;
(D) covering the capacitor structure with a resin layer;
(E) forming a through hole, a first hole reaching the metal layer of the sheet base material, and a second hole reaching the capacitor electrode layer in the resin layer;
(F) filling the through hole, the first hole, and the second hole with a conductor;
(G) forming a first electrode pad connected to the conductor filling the first hole and a second electrode pad connected to the conductor filling the through hole and the second hole;
including.

  A low-cost and large-capacity capacitor interposer is realized.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 shows a configuration of a capacitor interposer according to an embodiment of the present invention. 1A is a top view, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. On the surface of the capacitor interposer 10, a signal pad 21S, a power supply pad 21V, and a ground pad 21G are arranged at predetermined positions.

  The capacitor interposer 10 includes a capacitor 22. The capacitor 22 includes an aluminum sheet 11 that is a sheet base material located inside the interposer 10, a dielectric layer 12 located on the surface of the aluminum sheet 11, and a conductive polymer layer 13 located on the dielectric layer 12. , A planar capacitor (solid electrolytic capacitor) composed of the electrode layer 14. The conductive polymer layer 13 and the electrode layer 14 constitute a capacitor electrode. The surface of the aluminum sheet 11 is partially or entirely roughened to increase the surface area.

  Capacitor interposer 10 also reaches first aluminum sheet 11 from the surface of capacitor interposer 10 and is insulated from electrode layer 14 and conductive polymer layer 13, and is connected to first conductor 18. The power supply pad 21V is located on the surface of the capacitor interposer 10.

  In addition, it has a second conductor 17 that penetrates the aluminum sheet 11 and is insulated from the aluminum sheet 11, and a ground pad 21 </ b> G connected to the second conductor 17 and the capacitor electrode layer 14.

  Furthermore, a via conductor (third conductor) 19 that penetrates the aluminum sheet 11 and is insulated from the capacitor 22, and a signal pad 21 </ b> S connected to the via conductor 19 and positioned on the surface of the capacitor interposer 10 are provided.

The planar capacitor 22 is embedded in the resin layer 16 in a state of being entirely covered with the inorganic insulating protective film 15. The resin layer 16 including the aluminum sheet 11 constitutes an interposer substrate. A through hole for arranging the second conductor 17 and the third conductor (via conductor) 19 is also embedded in the resin layer 16, and the second conductor 17 and the third conductor 19 penetrate the resin layer 16. Thus, it is insulated from the aluminum sheet 11 or the capacitor 22. Similarly, the first conductor 18 is also insulated from the capacitor electrode layer 14 by the resin layer 16 embedded in the through hole reaching the aluminum sheet 11.
In the example of FIG. (B), capacitors 22 are formed on both sides of the aluminum sheet 11. Electrode pads 21 are disposed on both sides of the substrate (resin layer 16) to form a double-sided interposer.

  A large number of power supply pads 21V and ground pads 21G are alternately arranged at a narrow pitch. Further, as is apparent from FIG. 1B, both are highly symmetric structures, and an extremely low inductance can be realized. Further, all of the power supply line (first conductor) 18, the ground line (second conductor) 17, and the signal line (third conductor) 19 are through vias, and a direct current resistance component when passing through the capacitor interposer 10. Is extremely low.

  Normally, in such an interposer, the signal via 19 passes close to a high dielectric constant body or conductor, so that the signal characteristics deteriorate. In the example of FIG. 1, the signal via 19 has a low dielectric constant and high insulation. The structure passes through the resin layer 16 and has little signal degradation.

  In addition, in the example of FIG. 1, although the aluminum sheet 11 is used, the arbitrary sheet base materials which have a metal layer in at least one surface can be used. In this case, the metal layer is a layer mainly composed of, for example, aluminum (Al), niobium (Nb), tantalum (Ta), or the like. Furthermore, the sheet base material may be a metal foil composed of a single layer or a plurality of metal layers. For example, a laminate of aluminum (Al) foil and copper (Cu) foil (copper is used as a core agent and aluminum is bonded to the surface) can be used as the sheet base material.

  FIG. 2 is a schematic diagram showing an example in which the capacitor interposer 10 of FIG. 1 is applied to the semiconductor device 1. The semiconductor device 1 includes a circuit board 20, an LSI chip 30, and a capacitor interposer 10 inserted therebetween. The capacitor interposer 10 is inserted between the circuit board 20 and the LSI chip 30 by the bumps 25. The bump 25 is connected to the electrode pad 21 formed on the surface of the capacitor interposer 10.

  3 and 4 are manufacturing process diagrams of the capacitor interposer 10 of FIG. First, as shown in FIG. 3A, through holes 31 having a diameter of 200 μm are formed by punching in an aluminum foil 11 having a thickness of 100 μm at a pitch of 400 μm.

  Next, as shown in FIG. 3B, the aluminum foil 11 is electrolytically etched in a hydrochloric acid aqueous solution to roughen the surface of the aluminum foil 11. Furthermore, it is anodized in an aqueous solution of ammonium adipate to form an oxide film on the surface of the aluminum foil. This oxide film becomes the dielectric layer 12 constituting the capacitor. Since the dielectric layer 12 is formed by anodizing the surface of the roughened aluminum foil 11, the dielectric layer (alumina film) 12 having a large specific surface area is formed. The dielectric layer 12 is also formed on the side wall of the through hole 31.

  Next, as shown in FIG. 3C, a conductive polymer layer 13 is formed on the dielectric layer 12 by inkjet, screen printing, or the like. For example, the conductive polymer layer 13 made of polypyrrole can be formed in a predetermined pattern by repeating an application, polymerization, and drying of an aqueous solution containing a pyrrole monomer only to a necessary portion several times by an inkjet method.

  Next, as shown in FIG. 3D, a silver paste electrode layer 14 is formed on the surface of the conductive polymer layer 13 by screen printing. The conductive polymer layer 13 and the electrode layer 14 constitute a capacitor electrode layer. By applying the conductive polymer layer 13 to the interface with the dielectric layer 11, poor insulation at the electrode end is unlikely to occur.

  Next, as shown in FIG. 4E, a water-resistant insulating protective film 15 made of SiN is formed on the entire structure by sputtering, CVD, or the like. The electrolytic capacitor has a problem of deterioration due to moisture, but the formation of the water-resistant inorganic insulating protective film 15 after the formation of the capacitor (electrolytic capacitor) 22 solves the problem of moisture deterioration. As the insulating protective film 15, in addition to SiN, SiO2, Al2O3, DLC (diamond-like carbon), or the like may be used.

  Next, as shown in FIG. 4 (f), a laminate film made of a thermoplastic resin is laminated on both surfaces of the structure and heat-pressed to form a resin layer 16 on the entire surface. The through hole 31 is also filled with the resin layer 16.

  Next, as shown in FIG. 4G, through holes 32 for signal vias and ground vias are formed by laser processing. Further, a via hole 33 reaching the aluminum foil 11 and a hole 34 reaching the electrode layer 14 for connecting the ground via are formed for the power supply via.

Next, as shown in FIG. 4 (h), via holes (through holes) 32, 33, 34 are filled by electroless Cu plating and electrolytic Cu plating to form conductors 17, 18, 19, Furthermore, electrode pads 21G, 21V, and 21S connected to these conductors are formed.
(Example 1)
The 20 mm square capacitor thus formed was mounted by solder bumps on a substrate for evaluating electrical characteristics, and the electrical characteristics were evaluated using a network analyzer. As a result, the following characteristics were obtained.

Capacitance: 600μF
ESR: 1mΩ
ESL: 0.1 pH or less Leakage current: 100 μA or less In addition, the capacitance change after a high temperature and high humidity addition test at 85 ° C., 85% RH, 2.5 V, 500 h is 10% or less, and the leakage current is 10 μA or less. there were.
For comparison, a capacitor without the SiN insulating protective film 15 was produced, and the leakage current after the same high-temperature and high-humidity addition test was measured. As a result, it was deteriorated to 1,000 μA or more.

The value of the sample capacitance of 600 μF / 20 × 20 mm 2 described above results in a capacitance density of 150 μF / cm 2. A reported example of the capacitance density of a capacitor using a conventional high dielectric constant thin film is about several μF / cm 2, and the present invention achieves a value several tens of times higher.
In the process described above, the steps (b), (c), and (d) for forming the solid electrolytic capacitor (capacitor) are basically the same as the manufacturing steps of a normal solid electrolytic capacitor. Further, since most of the steps can be performed as a sheet process, the manufacturing cost is very low. Furthermore, since an electrode layer made of a conductive polymer or the like is formed by patterning, insulation failure at the end of the electrode layer is unlikely to occur.
(Example 2)
A capacitor was prototyped and evaluated according to the following procedure.
1) The conductive polymer layer 13 is formed in the same manner as in Example 1.
2) A multilayer electrode layer 14 made of carbon paste and silver paste is formed.
3) As in the first embodiment, the processes after the SiN insulating protective film 15 are performed.
4) The 20 mm square capacitor thus formed was solder bump mounted on a substrate for electrical property evaluation, and the electrical property was evaluated using a network analyzer. As a result, the following property was obtained.

Capacitance: 600μF
ESR: 0.5mΩ
ESL: 0.1 pH or less Leakage current: 10 μA or less (Example 3)
A capacitor was prototyped and evaluated according to the following procedure.
1) Holes having a diameter of 200 μm are formed at a pitch of 400 μm by punching using a sheet base material in which an aluminum foil having a thickness of 30 μm is bonded to a polyimide heat-resistant film having a thickness of 30 μm.
2) Thereafter, a capacitor is formed in the same manner as in the first embodiment. However, the capacitor (electrolytic capacitor) 22 and the insulating protective film 15 are formed only on the surface on the aluminum side. That is, it is similar to the configuration of FIG. In the sample, the film laminate is also on the aluminum side only.
3) The 20 mm square capacitor thus formed was mounted on a board for evaluating electrical characteristics by solder bumps, and the electrical characteristics were evaluated using a network analyzer. The following characteristics were obtained.

Capacitance: 300μF
ESR: 1mΩ
ESL: 0.1 pH or less Leakage current: 10 μA or less FIG. 5 shows a modification of the capacitor interposer. In the example of FIG. 1, capacitors (electrolytic capacitors) are formed on both surfaces of the aluminum sheet 10, but the capacitor interposer 50 in FIG. 5 forms capacitors only on one surface of the aluminum sheet 11. Also in this case, a planar large capacity capacitor is formed. As in FIG. 1, a conductor 18 reaching the aluminum sheet 11 and a power supply pad 21V connected thereto are formed, and the conductor 17 penetrating the capacitor is connected to the conductor 18 and the electrode layer 14 of the capacitor. It has a ground pad 21G, a conductor 19 that penetrates the capacitor and is insulated from the capacitor, and a signal pad 21S connected thereto.

  FIG. 6 shows still another modification of the capacitor interposer. In the capacitor interposer 60 of FIG. 6, the capacitor (electrolytic capacitor) 22 is formed only on a part of the resin layer 16. In this case, the through via of the electrolytic capacitor unit may be only the power supply and the ground, and the signal via may be formed in a resin region where the capacitor 22 does not exist.

  FIG. 7 shows still another modification of the capacitor interposer. In the capacitor interposer 70 of FIG. 7, the capacitor electrode composed of the conductive polymer layer 13 and the capacitor electrode layer 14 is continuously formed on both sides of the aluminum sheet 11 on the through conductors 17 and 19 side.

  FIG. 8 is a diagram showing a configuration example of a semiconductor device using a plurality of capacitor interposers 10, 50, 60 or 70 of FIG. 1, FIG. 5, FIG. 6 or FIG. 8A, a plurality of capacitor interposers 10 (which may be 50, 60, or 70) are stacked on the circuit board 20 via the solder bumps 25, and the LSI chip 30 is mounted thereon, FIG. ) Is a form in which a plurality of LSI chips 30 are mounted on one capacitor interposer, and FIG. 7C is a form in which a plurality of capacitor interposers are mounted on one LSI chip. In FIG. 7B, columnar bumps 26 are used to connect the electrode pads on the circuit board 20 side, but spherical bumps 25 may be used, or columnar bumps may be used to connect the electrode pads on the LSI chip 30 side. It may be used.

Although the present invention has been described based on the specific embodiments, various modifications and substitutions are possible within the scope of the present invention. The sheet base material (metal sheet) 11 may be any metal that can form a roughening treatment and an anodized film in addition to aluminum, and may be tantalum, niobium, or various alloys. For the conductive polymer 13, various materials used for electrolytic capacitors can be used, and examples thereof include polypyrrole, polyethylenedioxythiophene (PEDT), polythiophene, and polyaniline.
The electrode layer 14 formed on the conductive polymer 13 is a single layer or a laminate of carbon paste, silver paste, gold paste, and plating, vapor deposition or sputtering film of metal such as Cu, Ni, Au, etc. Is also possible.
As for the manufacturing process, as shown in FIG. 3, the punch holes may be made first, but the punch holes may be made after anodization or after the electrode layer is formed.

  Thus, the structure in which the through via is formed in the planar solid electrolytic capacitor according to the present invention and the pads for external connection are formed at both ends of the through via can provide a large-capacity capacitor interposer at low cost.

Finally, the following notes are disclosed for the above explanation.
(Appendix 1) A capacitor-embedded wiring board,
A sheet base material that is located inside the wiring board and has at least one surface made of metal, a dielectric layer that is located on the metal surface of the sheet base material, and a capacitor electrode layer that is located on the dielectric layer. A planar capacitor
A first conductor insulated from the capacitor electrode layer and reaching the metal surface of the sheet base material from the surface of the wiring board;
A first electrode pad (electrode pad) connected to the first conductor and located on the surface of the wiring board;
A second conductor that penetrates through the sheet substrate and is insulated from the sheet substrate;
A second electrode pad (ground pad) connected to the second conductor and the capacitor electrode layer;
A wiring board comprising:
(Additional remark 2) The 3rd conductor which penetrates the said wiring board and is insulated from the said capacitor,
The wiring board according to appendix 1, further comprising a third electrode pad (signal pad) connected to the third conductor and positioned on a surface of the wiring board.
(Supplementary note 3) The wiring board according to supplementary note 1, wherein the planar capacitor further includes a conductive polymer layer disposed between the dielectric layer and the capacitor electrode layer.
(Supplementary note 4) The wiring board according to supplementary note 1, wherein at least a part of the metal surface of the sheet material of the planar capacitor is made porous.
(Appendix 5) a resin layer covering the planar capacitor;
A third conductor that penetrates the resin layer in a region where the planar capacitor does not exist;
The wiring board according to appendix 1, further comprising a third electrode pad (signal pad) connected to the third conductor and positioned on a surface of the resin layer.
(Additional remark 6) It has further the resin layer which covers the said planar capacitor, and the said resin layer embeds between the 2nd conductor which penetrates the said sheet base material, and the said sheet base material. The wiring board described.
(Additional remark 7) The wiring board of Additional remark 1 characterized by further having the insulation protective film of the inorganic material which covers the said planar capacitor.
(Supplementary note 8) The wiring board according to supplementary note 7, wherein the insulating protective film is formed of a single layer or a laminate mainly composed of silicon oxide, silicon nitride, alumina, and diamond-like carbon.
(Additional remark 9) The said dielectric material layer is an anodized film of the said sheet | seat base material, The wiring board of Additional remark 1 characterized by the above-mentioned.
(Appendix 10) At least a part of the metal surface of the sheet base material of the planar capacitor is made porous,
The planar capacitor further includes the dielectric layer formed on the porous metal surface and a conductive polymer layer disposed between the capacitor electrode layers. Wiring board as described in.
(Appendix 11) Circuit board,
A semiconductor chip mounted on the circuit board;
A semiconductor device including a planar capacitor built-in interposer inserted between the circuit board and a semiconductor chip,
The capacitor built-in interposer is
A sheet base material which is located inside the interposer substrate and has at least one surface made of metal, a dielectric layer located on the metal surface of the sheet base material, and a capacitor electrode layer located on the dielectric layer With a planar capacitor,
A first conductor insulated from the capacitor electrode layer and reaching the metal surface of the sheet base material from the surface of the interposer substrate;
A first electrode pad (electrode pad) connected to the first conductor and located on the surface of the interposer substrate;
A second conductor that penetrates through the sheet substrate and is insulated from the sheet substrate;
A second electrode pad (ground pad) connected to the second conductor and the capacitor electrode layer;
A semiconductor device comprising:
(Supplementary note 12) The interposer further includes a third conductor that penetrates the sheet base material and is insulated from the planar capacitor, and a third electrode pad connected to the third conductor. The semiconductor device according to appendix 11, wherein:
(Additional remark 13) The said interposer further includes the insulating film comprised with the inorganic material which covers the said planar capacitor, The semiconductor device of Additional remark 11 characterized by the above-mentioned.
(Supplementary note 14) The semiconductor device according to supplementary note 11, wherein at least a part of the metal surface of the sheet base material of the interposer is made porous.
(Supplementary note 15) The semiconductor device according to supplementary note 11, wherein the planar capacitor of the interposer further includes a conductive polymer layer between the dielectric layer and the capacitor electrode layer.
(Additional remark 16) The process of forming a through-hole in the predetermined location of the sheet base material which has a metal layer in at least one surface,
Forming a dielectric layer by anodizing after at least part of the metal layer of the sheet substrate is made porous; and
Forming a capacitor electrode layer on the dielectric layer to form a capacitor structure;
Covering the capacitor structure with a resin layer;
Forming a through hole, a first hole reaching the metal layer of the sheet base material, and a second hole reaching the capacitor electrode layer in the resin layer;
Filling the through hole, the first hole, and the second hole with a conductor;
Forming a first electrode pad connected to the conductor filling the first hole and a second electrode pad connected to the conductor filling the through hole and the second hole;
A method of manufacturing a wiring board with a built-in capacitor, comprising:
(Supplementary Note 17) In the electrode pad forming step, a third electrode pad connected to a conductor filling the through hole and insulated from the conductor filling the first and second holes is formed.
The method for manufacturing a capacitor-embedded wiring board according to appendix 16, further comprising:
(Additional remark 18) The manufacturing method of the capacitor built-in wiring board of additional remark 16 characterized by further including the process of forming the insulating protective film which covers the said capacitor structure with an inorganic material before the said resin layer formation.
(Supplementary note 19) The supplementary note 16, further comprising a step of forming an inorganic insulating layer on the capacitor structure between the step of forming the capacitor structure and the step of forming the resin layer. A method for manufacturing a capacitor-embedded wiring board as described in 1.
(Supplementary note 20) The supplementary note 16, further comprising a step of forming a conductive polymer film on the dielectric layer, wherein the capacitor electrode layer is formed on the conductive polymer film. Method for manufacturing a capacitor-embedded wiring board.

It is a figure which shows the structure of the capacitor interposer which concerns on one Embodiment of this invention, Fig.1 (a) is a top view, FIG.1 (b) is AA 'sectional drawing. It is a schematic block diagram of the semiconductor device to which the capacitor interposer of FIG. 1 is applied. It is a manufacturing process figure (the 1) of a capacitor interposer concerning one embodiment of the present invention. It is a manufacturing process figure (the 2) of the capacitor interposer concerning one embodiment of the present invention, and is a figure moistening the process following Drawing 3 (d). It is modification 1 of a capacitor interposer. It is modification 2 of a capacitor interposer. It is the modification 3 of a capacitor interposer. It is a figure which shows another structural example of the semiconductor device which mounted the capacitor interposer of embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10, 50, 60, 70 Capacitor interposer 11 Aluminum sheet (sheet base material)
12 Dielectric layer 13 Conductive polymer film 14 Capacitor electrode layer 17 Ground line (second conductor)
18 Power line (first conductor)
19 Signal line (third conductor)
21V, 21G, 21S Electrode pad 22 Capacitor (electrolytic capacitor)
25 Bump 30 LSI chip

Claims (5)

A wiring board with a built-in capacitor,
A sheet base material that is located inside the wiring board and has at least one surface made of metal, a dielectric layer that is located on the metal surface of the sheet base material, and a capacitor electrode layer that is located on the dielectric layer. A planar capacitor
A first conductor insulated from the capacitor electrode layer and reaching the metal surface of the sheet base material from the surface of the wiring board;
A first electrode pad connected to the first conductor and located on a surface of the wiring board;
A second conductor that penetrates through the sheet substrate and is insulated from the sheet substrate;
A second electrode pad connected to the second conductor and the capacitor electrode layer;
A wiring board comprising: A circuit board;
A semiconductor chip mounted on the circuit board;
A semiconductor device including a planar capacitor built-in interposer inserted between the circuit board and a semiconductor chip,
The capacitor built-in interposer is
A sheet base material which is located inside the interposer substrate and has at least one surface made of metal, a dielectric layer located on the metal surface of the sheet base material, and a capacitor electrode layer located on the dielectric layer With a planar capacitor,
A first conductor insulated from the capacitor electrode layer and reaching the metal surface of the sheet base material from the surface of the interposer substrate;
A first electrode pad connected to the first conductor and located on a surface of the interposer substrate;
A second conductor that penetrates through the sheet substrate and is insulated from the sheet substrate;
A second electrode pad connected to the second conductor and the capacitor electrode layer;
A semiconductor device comprising: The metal surface of the sheet substrate is made porous,
The planar capacitor further comprises a conductive polymer layer between the dielectric layer located on the porous metal surface and the capacitor electrode layer. Or a semiconductor device according to claim 2. Forming a through hole at a predetermined position of a sheet base material having a metal layer on at least one surface;
Forming a dielectric layer by anodizing after at least part of the metal layer of the sheet base material is made porous; and
Forming a capacitor structure including a conductive polymer on the dielectric layer to form a capacitor structure;
Covering the capacitor structure with a resin layer;
Forming a through hole, a first hole reaching the metal layer of the sheet base material, and a second hole reaching the capacitor electrode layer in the resin layer;
Filling the through hole, the first hole, and the second hole with a conductor;
Forming a first electrode pad connected to the conductor filling the first hole and a second electrode pad connected to the conductor filling the through hole and the second hole;
A method of manufacturing a wiring board with a built-in capacitor, comprising: The electrode pad forming step includes forming a third electrode pad connected to a conductor filling the through hole and insulated from the conductor filling the first and second holes;
The method of manufacturing a wiring board with a built-in capacitor according to claim 4, further comprising:

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