CN103972217A - Integrated passive capacitance fan-out-type wafer-level packaging structure and manufacturing method thereof - Google Patents
Integrated passive capacitance fan-out-type wafer-level packaging structure and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention relates to an integrated passive capacitance fan-out-type wafer-level packaging structure and a manufacturing method of the integrated passive capacitance fan-out-type wafer-level packaging structure. The integrated passive capacitance fan-out-type wafer-level packaging structure comprises a plastic packaging body and a chip, and is characterized in that a first metal post, a second metal post, a third metal post and a fourth metal post are arranged in the plastic packaging body, the first metal post and the second metal post are located on one side of the chip, the third metal post and the fourth metal post are located on the other side of the chip, an insulating layer is arranged on the front surface of the plastic packaging body, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer are arranged in the insulating layer, the first metal layer is connected with the first metal post, the second metal layer is connected with the second metal post and a first electrode, the third metal layer is connected with the third metal post and a second electrode, and the fourth metal layer is connected with the fourth metal post. The four metal layers are respectively provided with a protruding point lower metal layer, and a welding ball is arranged on the outer surface of each protruding point lower metal layer. The integrated passive capacitance fan-out-type wafer-level packaging structure and the manufacturing method of the integrated passive capacitance fan-out-type wafer-level packaging structure achieve integration of fan-out-type chip packaging and a thin film integrated passive device, and improve electric quality.
Description
Technical field
The present invention relates to a kind of integrating passive electric capacity fan-out-type wafer level packaging structure and manufacture method, belong to fan-out-type Wafer level packaging field.
Background technology
Wafer scale fan-out-type chip package can substitute current bonding wire BGA(Ball Grid Array, the PCB of ball grid array structure) and flip-chip BGA encapsulation, be a kind of low cost, high performance integration packaging mode.Wafer scale RDL(wiring layer is more directly passed through in the wiring of signal, electric power and the ground wire of wafer scale fan-out-type chip package) technique realization, no longer need wafer convex point preparation and base plate for packaging, thereby reduction packaging cost, and can provide the electrical functions that is better than traditional bonding wire BGA and flip-chip BGA encapsulation.Film integrating passive technology can provide the best functional density conventionally, and maximum set Cheng Du and the lightest volume.Yet, single from price, the price of the passive device of film integrating passive until today still higher; And thicker metal is deposited on Silicon Wafer, be also difficult to improve its electrical quality factor, as inductance.The passive device Integrated Solution of wafer scale fan-out-type chip package and film integrating passive, that electronic product continues minification, increases one of very few method of function, the trend that meets portable type electronic product " sooner, less, lighter ", and cost performance improves constantly.
The low integrated level of wafer scale fan-out-type chip package and the passive device of film integrating passive and higher cost are the weak points of prior art maximum.Existing integrating passive electric capacity, is limited by the semi-conducting material attribute of silicon materials, cannot promote the quality factor of its circuit.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of integrating passive electric capacity fan-out-type wafer level packaging structure and manufacture method are provided, realize the integrated of wafer scale fan-out-type chip package and the passive device of film integrating passive, promoted electrical qualities.
According to technical scheme provided by the invention, described integrating passive electric capacity fan-out-type wafer level packaging structure, comprise fan-out-type packaging body, fan-out-type packaging body comprises plastic-sealed body and the plastic packaging chip in plastic-sealed body, the front of chip has the first electrode and the second electrode, and the front of chip is concordant with the front of plastic-sealed body; It is characterized in that: two groups of electric capacity are set in described plastic-sealed body, be respectively the first metal column, the second metal column, the 3rd metal column and the 4th metal column, the first metal column and the second metal column are positioned at a side of chip, and the 3rd metal column and the 4th metal column are positioned at the opposite side of chip; Front at described plastic-sealed body arranges insulating barrier, in insulating barrier, arrange the first metal layer, the second metal level, the 3rd metal level and the 4th metal level, the first metal layer is connected with the first metal column, the second metal level is connected with the first electrode of the second metal column and chip, the 3rd metal level is connected with the second electrode of the 3rd metal column and chip, and the 4th metal level is connected with the 4th metal column; The first ubm layer, the second ubm layer, the 3rd ubm layer and the 4th ubm layer are set respectively on described the first metal layer, the second metal level, the 3rd metal level and the 4th metal level, the outer surface of the first ubm layer, the second ubm layer, the 3rd ubm layer and the 4th ubm layer exposes the outer surface of insulating barrier, at the outer surface of the first ubm layer, the second ubm layer, the 3rd ubm layer and the 4th ubm layer, soldered ball is set respectively.
Between described the first metal column and the second metal column, fill capsulation material; Between described the 3rd metal column and the 4th metal column, fill capsulation material.
Described the first metal layer, the second metal level, the 3rd metal level and the 4th metal level are realized insulation by insulating barrier each other.
The manufacture method of described integrating passive electric capacity fan-out-type wafer level packaging structure, is characterized in that, comprises the following steps:
(1) chip fan-out-type is packaged in plastic-sealed body, obtains fan-out-type packaging body, the front of chip is concordant with the front of plastic-sealed body;
(2) on plastic-sealed body, open two groups of electric capacity grooves, two groups of grooves lay respectively at the both sides of chip, and every group of electric capacity groove is two cell bodies, between cell body, with capsulation material, separates;
(3) in above-mentioned electric capacity groove, fill metal, obtain respectively the first metal column, the second metal column, the 3rd metal column and the 4th metal column;
(4) at the front surface coated insulating material of plastic-sealed body, form insulating barrier; Insulating barrier is etched to figure opening, expose the surface of the first metal column, the second metal column, the 3rd metal column, the 4th metal column, the first electrode and the second electrode;
(5) at above-mentioned surface of insulating layer plated metal, form metal level, metal level connects the first metal column, the second metal column, the 3rd metal column, the 4th metal column, the first electrode and the second electrode;
(6) above-mentioned metal level is etched to figure opening, obtain the first metal layer, the second metal level, the 3rd metal level and the 4th metal level of mutually insulated;
(7) at the surface-coated insulating material of above-mentioned metal level, on the insulating material obtaining, etch four windows, expose respectively the surface of the first metal layer, the second metal level, the 3rd metal level and the 4th metal level;
(8) plated metal in above-mentioned window, obtains respectively the first ubm layer, the second ubm layer, the 3rd ubm layer and the 4th ubm layer; On the first ubm layer, the second ubm layer, the 3rd ubm layer and the 4th ubm layer surface, plant ball, obtain soldered ball.
The present invention is wafer scale fan-out-type chip package and the passive device of film integrating passive integratedly provides a set of efficient solution.The present invention makes full use of the moulding compound body that plays supportive protection effect in wafer scale fan-out-type chip packing-body, in moulding material, build thin film inductor, neither affect the area of whole packaging body, shorten again the electricity connecting length between chip and inductance, promoted electrical qualities; Meanwhile, on the moulding material surface of insulation, lay circuit, adopt semi-conducting material as silicon, promoted greatly the quality factor Q value of resonant circuit.
Accompanying drawing explanation
Fig. 1～Figure 10 is the schematic diagram of the manufacture process of encapsulating structure of the present invention.
Fig. 1 is the structural representation of described fan-out-type packaging body.
Fig. 2 for opening the schematic diagram of electric capacity groove on plastic-sealed body.
Fig. 3 is the schematic diagram that obtains two groups of electric capacity.
Fig. 4 is the schematic diagram at plastic-sealed body front surface coated insulating material.
Fig. 5 is the schematic diagram of needle drawing shape opening on insulating barrier.
Fig. 6 is the schematic diagram of electroplated metal layer on insulating barrier.
Fig. 7 for forming the schematic diagram of figure opening on metal level.
Fig. 8 applies the schematic diagram of insulating material at layer on surface of metal.
Fig. 9 for offering the schematic diagram of window on insulating barrier.
Figure 10 is structural representation of the present invention.
In figure, sequence number is: fan-out-type packaging body 1, plastic-sealed body 11, chip 12, the first electrode 13, the second electrode 14, the first metal column 21, the second metal column 22, the 3rd metal column 23, the 4th metal column 24, insulating barrier 3, the first metal layer 41, the second metal level 42, the 3rd metal level 43, the 4th metal level 44, the first ubm layer 51, the second ubm layer 52, the 3rd ubm layer 53, the 4th ubm layer 54, soldered ball 6.
Embodiment
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in figure 10: described integrating passive electric capacity fan-out-type wafer level packaging structure comprises fan-out-type packaging body 1, fan-out-type packaging body 1 comprises plastic-sealed body 11 and the plastic packaging chip 12 in plastic-sealed body 11, the front of chip 12 has the first electrode 13 and the second electrode 14, and the front of chip 12 is concordant with the front of plastic-sealed body 11, two groups of electric capacity are set in described plastic-sealed body 11, be respectively the first metal column 21, the second metal column 22, the 3rd metal column 23 and the 4th metal column 24, the first metal column 21 and the second metal column 22 are positioned at a side of chip 12, and the 3rd metal column 23 and the 4th metal column 24 are positioned at the opposite side of chip 12, in the front of described plastic-sealed body 11, insulating barrier 3 is set, in insulating barrier 3, arrange the first metal layer 41, the second metal level 42, the 3rd metal level 43 and the 4th metal level 44, the first metal layer 41 is connected with the first metal column 21, the second metal level 42 is connected with the first electrode 13 of the second metal column 21 and chip 12, the 3rd metal level 43 is connected with the second electrode 14 of the 3rd metal column 23 and chip 12, and the 4th metal level 44 is connected with the 4th metal column 24, at described the first metal layer 41, the second metal level 42, on the 3rd metal level 43 and the 4th metal level 44, the first ubm layer 51 is set respectively, the second ubm layer 52, the 3rd ubm layer 53 and the 4th ubm layer 54, the first ubm layer 51, the second ubm layer 52, the outer surface of the 3rd ubm layer 53 and the 4th ubm layer 54 exposes the outer surface of insulating barrier 3, at the first ubm layer 51, the second ubm layer 52, the outer surface of the 3rd ubm layer 53 and the 4th ubm layer 54 arranges respectively soldered ball 6, to realize, be connected with outside electricity,
Between described the first metal column 21 and the second metal column 22, fill capsulation material, form first group of electric capacity; Between described the 3rd metal column 23 and the 4th metal column 24, fill capsulation material, form second group of electric capacity;
Described the first metal layer 41, the second metal level 42, the 3rd metal level 43 and the 4th metal level 44 are realized insulation by insulating barrier 3 each other.
The manufacture method of described integrating passive electric capacity fan-out-type wafer level packaging structure, comprises the following steps:
(1) as shown in Figure 1, chip 12 is carried out to fan-out-type encapsulation, by chip 12 plastic packagings, in plastic-sealed body 11, the front of chip 12 is concordant with the front of plastic-sealed body 11;
(2) as shown in Figure 2, open two groups of electric capacity grooves on plastic-sealed body 11, two groups of grooves lay respectively at the both sides of chip 12, and every group of electric capacity groove is two cell bodies, between cell body, with capsulation material, separates;
(3) as shown in Figure 3, in above-mentioned electric capacity groove, fill metal, obtain respectively the first metal column 21, the second metal column 22, the 3rd metal column 23 and the 4th metal column 24, the first metal column 21 and the second metal column 22 form one group of electric capacity, and the 3rd metal column 23 and the 4th metal column 24 form another group electric capacity; The mode of described filling metal can adopt plated metal etc., and metal can adopt tin, copper or terne metal etc.;
(4) as shown in Figure 4, the front surface coated insulation organic media material at plastic-sealed body 11, forms insulating barrier, and thickness of insulating layer is 1～50 micron; Can adopt wafer whirl coating technique, insulation organic media material can adopt PI(polyimides), PBO(polybenzoxazoles) or liquid photopolymerizable solder resist (being commonly called as green oil) etc.;
(5) as shown in Figure 5, insulating barrier is carried out to chemical wet etching, form figure opening, the surface of exposing the first metal column 21, the second metal column 22, the 3rd metal column 23, the 4th metal column 24, the first electrode 13 and the second electrode 14;
(6) as shown in Figure 6, at surface of insulating layer plated metal, form metal level, metal layer thickness is 1～30 micron, and metal level connects the first metal column 21, the second metal column 22, the 3rd metal column 23, the 4th metal column 24, the first electrode 13 and the second electrode 14; Metal level can adopt tin, copper or terne metal etc.;
(7) as shown in Figure 7, metal level is carried out to photoetching or etching, form figure opening, obtain the first metal layer 41, the second metal level 42, the 3rd metal level 43 and the 4th metal level 44 of mutually insulated;
(8) as shown in Figure 8,, at the insulation organic media material of surface-coated 1～50 micron thickness of above-mentioned metal level, with passivated metal layer, realize defencive function; Can adopt wafer whirl coating technique, insulation organic media material can adopt PI(polyimides), PBO(polybenzoxazoles) or liquid photopolymerizable solder resist (being commonly called as green oil) etc.;
(9) as shown in Figure 9, on the insulating material obtaining in step (8), etching forms four windows, the surface of exposing respectively the first metal layer 41, the second metal level 42, the 3rd metal level 43 and the 4th metal level 44;
(10) as shown in figure 10, plated metal in the window obtaining in step (9), obtains respectively the first ubm layer 51, the second ubm layer 52, the 3rd ubm layer 53 and the 4th ubm layer 54; On the first ubm layer 51, the second ubm layer 52, the 3rd ubm layer 53 and the 4th ubm layer 54 surfaces, plant ball, obtain soldered ball 6, realize and being connected with outside electricity; Ubm layer adopts the alloy of aluminium, nickel, vanadium, copper or above-mentioned metal.
Claims (4)
1. an integrating passive electric capacity fan-out-type wafer level packaging structure, comprise fan-out-type packaging body (1), fan-out-type packaging body (1) comprises plastic-sealed body (11) and the plastic packaging chip (12) in plastic-sealed body (11), the front of chip (12) has the first electrode (13) and the second electrode (14), and the front of chip (12) is concordant with the front of plastic-sealed body (11), it is characterized in that: two groups of electric capacity are set in described plastic-sealed body (11), be respectively the first metal column (21), the second metal column (22), the 3rd metal column (23) and the 4th metal column (24), the first metal column (21) and the second metal column (22) are positioned at a side of chip (12), and the 3rd metal column (23) and the 4th metal column (24) are positioned at the opposite side of chip (12), in the front of described plastic-sealed body (11), insulating barrier (3) is set, in insulating barrier (3), arrange the first metal layer (41), the second metal level (42), the 3rd metal level (43) and the 4th metal level (44), the first metal layer (41) is connected with the first metal column (21), the second metal level (42) is connected with first electrode (13) of the second metal column (21) and chip (12), the 3rd metal level (43) is connected with second electrode (14) of the 3rd metal column (23) and chip (12), and the 4th metal level (44) is connected with the 4th metal column (24), in described the first metal layer (41), the second metal level (42), on the 3rd metal level (43) and the 4th metal level (44), the first ubm layer (51) is set respectively, the second ubm layer (52), the 3rd ubm layer (53) and the 4th ubm layer (54), the first ubm layer (51), the second ubm layer (52), the outer surface of the 3rd ubm layer (53) and the 4th ubm layer (54) exposes the outer surface of insulating barrier (3), in the first ubm layer (51), the second ubm layer (52), the outer surface of the 3rd ubm layer (53) and the 4th ubm layer (54) arranges respectively soldered ball (6).
2. integrating passive electric capacity fan-out-type wafer level packaging structure as claimed in claim 1, is characterized in that: between described the first metal column (21) and the second metal column (22), fill capsulation material; Between described the 3rd metal column (23) and the 4th metal column (24), fill capsulation material.
3. integrating passive electric capacity fan-out-type wafer level packaging structure as claimed in claim 1, is characterized in that: described the first metal layer (41), the second metal level (42), the 3rd metal level (43) and the 4th metal level (44) are realized insulation by insulating barrier (3) each other.
4. a manufacture method for integrating passive electric capacity fan-out-type wafer level packaging structure, is characterized in that, comprises the following steps:
(1) chip (12) fan-out-type is packaged in plastic-sealed body (11), obtains fan-out-type packaging body (1), the front of chip (12) is concordant with the front of plastic-sealed body (11);
(2) on plastic-sealed body (11), open two groups of electric capacity grooves, two groups of grooves lay respectively at the both sides of chip (12), and every group of electric capacity groove is two cell bodies, between cell body, with capsulation material, separates;
(3) in above-mentioned electric capacity groove, fill metal, obtain respectively the first metal column (21), the second metal column (22), the 3rd metal column (23) and the 4th metal column (24);
(4) at the front surface coated insulating material of plastic-sealed body (11), form insulating barrier; Insulating barrier is etched to figure opening, expose the surface of the first metal column (21), the second metal column (22), the 3rd metal column (23), the 4th metal column (24), the first electrode (13) and the second electrode (14);
(5) at above-mentioned surface of insulating layer plated metal, form metal level, metal level connects the first metal column (21), the second metal column (22), the 3rd metal column (23), the 4th metal column (24), the first electrode (13) and the second electrode (14);
(6) above-mentioned metal level is etched to figure opening, obtain the first metal layer (41), the second metal level (42), the 3rd metal level (43) and the 4th metal level (44) of mutually insulated;
(7) at the surface-coated insulating material of above-mentioned metal level, on the insulating material obtaining, etch four windows, expose respectively the surface of the first metal layer (41), the second metal level (42), the 3rd metal level (43) and the 4th metal level (44);
(8) plated metal in above-mentioned window, obtains respectively the first ubm layer (51), the second ubm layer (52), the 3rd ubm layer (53) and the 4th ubm layer (54); On the first ubm layer (51), the second ubm layer (52), the 3rd ubm layer (53) and the 4th ubm layer (54) surface, plant ball, obtain soldered ball (6).
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| CN113659053B (en) * | 2021-09-07 | 2024-02-27 | 中山市木林森电子有限公司 | CSP lamp bead packaging structure and manufacturing process thereof |
| CN115148724A (en) * | 2022-07-12 | 2022-10-04 | 奇异摩尔(上海)集成电路设计有限公司 | Fan-out system package and method for integrated MIM capacitor |
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Application publication date: 20140806 Assignee: Huajin semiconductor (Jiashan) Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2021980017402 Denomination of invention: Integrated passive capacitor fan out wafer level packaging structure and manufacturing method Granted publication date: 20160824 License type: Exclusive License Record date: 20220111 |