CN113270327B - Active and passive device vertical laminated embedded packaging structure and manufacturing method thereof - Google Patents
Active and passive device vertical laminated embedded packaging structure and manufacturing method thereof Download PDFInfo
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- CN113270327B CN113270327B CN202110816260.6A CN202110816260A CN113270327B CN 113270327 B CN113270327 B CN 113270327B CN 202110816260 A CN202110816260 A CN 202110816260A CN 113270327 B CN113270327 B CN 113270327B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
Abstract
The invention discloses a vertical lamination embedding packaging structure of an active and passive device and a manufacturing method thereof, wherein the vertical lamination embedding packaging structure comprises a substrate, the substrate is used as a former-stage structural body to process an intermediate layer and a packaging layer, and the intermediate layer is processed as follows: processing a middle pattern layer on the former stage of structure body, wherein the middle pattern layer comprises a characteristic metal block, a cavity part is arranged in the edge area of the characteristic metal block, a middle medium layer is obtained by laminating and thinning the middle pattern layer, and a supporting part is formed at the part of the middle medium layer, which is positioned in the cavity part; processing a packaging layer on the intermediate dielectric layer, wherein the packaging layer comprises a dielectric material and a sacrificial metal block; etching to obtain a packaging cavity and forming a flow guide groove between the supporting parts; mounting electronic components in the packaging cavity, wherein at least one electronic component is supported on the corresponding supporting part; and carrying out packaging treatment on the packaging cavity. The invention can encapsulate the active and passive devices in the encapsulation structure body, reduce the encapsulation space and is beneficial to realizing the miniaturization design.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a vertical lamination embedded packaging structure of an active device and a passive device and a manufacturing method thereof.
Background
With the application requirement of miniaturization of electronic products, the systematic packaging technology is very important in the new generation of electronic products. In order to match the development of the new generation of electronic products, especially the development of products such as smart phones, palm computers, super books and the like, the size of the chip is developed towards the directions of higher density, higher speed, smaller size, lower cost and the like. The systematic packaging structure of many devices needs to use different collocation of a plurality of chips to the cooperation is accomplished in coordination with passive devices such as different quantity and type electric capacity, resistance, inductance, and systematic packaging can satisfy the size of electronic product more frivolous, realize the functional requirement under the different scenes, can reach the requirement of material cost saving even.
However, in the systematic packaging scheme of the related art, the substrate to be packaged needs to be provided with an active device region and a passive device region, the active device is mounted on the substrate through wire bonding or flip-chip bonding, and the mounting of the passive device needs to be completed through solder reflow. Moreover, since passive devices such as inductors, capacitors, IPDs (integrated passive devices), etc. are bulky, they need to occupy more dimensional space.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides the vertical lamination embedded packaging structure of the active and passive devices and the manufacturing method thereof, which can package the active and passive devices in the packaging structure body, reduce the packaging space and facilitate the realization of miniaturization design.
In a first aspect, an active and passive device vertical stack embedded package structure according to an embodiment of the present invention includes:
providing a substrate used as a first packaging layer, wherein the substrate comprises a first dielectric material and a first sacrificial metal block embedded in the first dielectric material;
processing the substrate as a previous-stage structure body by using an intermediate layer and a packaging layer to obtain a secondary semi-finished product, wherein,
the processing step of the intermediate layer comprises the following steps: processing an Mth middle pattern layer on the previous stage structure, wherein the Mth middle pattern layer comprises an Mth characteristic metal block, the Mth characteristic metal block covers the previous stage sacrificial metal block, a plurality of cavity parts are arranged in the edge area of the Mth characteristic metal block, and the edge area of the Mth characteristic metal block is used for representing that the Mth characteristic metal block exceeds the area of the previous stage sacrificial metal block under the condition that the Mth characteristic metal block is projected on the previous stage sacrificial metal block; laminating and thinning the middle pattern layer to obtain a middle medium layer, wherein a supporting part is formed at the part of the middle medium layer positioned in the cavity part, and M is a positive integer;
the processing steps of the packaging layer comprise: processing an Nth packaging layer on the intermediate medium layer, wherein the Nth packaging layer comprises an (N + 1) th medium material and an (N + 1) th sacrificial metal block embedded in the (N + 1) th medium material, the (N + 1) th sacrificial metal block covers the characteristic metal block of the previous stage, and N is a positive integer;
etching all the sacrificial metal blocks and all the characteristic metal blocks to obtain at least two packaging cavities and form a flow guide groove between the adjacent supporting parts;
mounting a corresponding electronic component in each packaging cavity, wherein at least one electronic component is supported on the corresponding supporting part;
and carrying out packaging treatment on the packaging cavity.
The manufacturing method of the vertical lamination embedded packaging structure of the active and passive devices according to the embodiment of the invention at least has the following beneficial effects:
according to the embodiment of the invention, the plurality of electronic components are vertically packaged along the lamination direction, so that the packaging space is reduced, the miniaturization design is favorably realized, and the plurality of electronic components can be packaged at one time after being mounted, so that the packaging process is favorably simplified, and the production cost is reduced.
According to some embodiments of the invention, the electronic component is an active device or a passive device.
According to some embodiments of the invention, the substrate further includes a first conduction column embedded in the first dielectric material, in the processing step of the intermediate layer, the mth intermediate pattern layer further includes an mth conduction connection column, the mth conduction connection column corresponds to a position of a conduction column of a previous stage, in the processing step of the encapsulation layer, the N +1 th encapsulation layer further includes an N +1 th conduction column embedded in the N +1 th dielectric material, and the N +1 th conduction column corresponds to a position of a conduction connection column of a previous stage.
According to some embodiments of the present invention, the method for manufacturing the active and passive device vertical stack embedded package structure further comprises:
and processing the intermediate layer and the packaging layer by taking the secondary semi-finished product as a primary structure until the lamination requirement is met.
According to some embodiments of the invention, the mounting of the corresponding electronic component in each of the package cavities includes:
processing a temporary bearing surface at a position, corresponding to the packaging cavity, of one surface of the substrate, which is opposite to the middle graph layer;
mounting a first electronic component on the temporary bearing surface;
and mounting the next electronic component above the previous electronic component and supporting the next electronic component on the corresponding supporting part.
According to some embodiments of the invention, the mounting of the corresponding electronic component in each of the package cavities further comprises:
and carrying out die bonding on the electronic component through silver paste or DAF material.
According to some embodiments of the invention, the encapsulating the encapsulation cavity comprises:
laminating plastic packaging materials on the last layer of packaging layer to obtain a laminated semi-finished product;
and pressing the laminated semi-finished product in a hot pressing mode.
According to some embodiments of the invention, the encapsulating process for the encapsulation cavity further comprises the following steps:
thinning the semi-finished product obtained after the packaging treatment to obtain a first semi-finished product;
and processing a surface circuit layer on the surface of the first semi-finished product, wherein the surface circuit layer comprises a plurality of wires which are respectively connected with the corresponding terminals of the electronic component.
According to some embodiments of the invention, the encapsulating process for the encapsulation cavity further comprises the following steps:
thinning the semi-finished product obtained after the packaging treatment to obtain a first semi-finished product;
performing laser drilling on the first semi-finished product to obtain a first through hole, wherein the first through hole is communicated with a terminal of the corresponding electronic component;
processing a through hole column in the first through hole, and processing a surface circuit layer on the surface of the first semi-finished product, wherein the surface circuit layer comprises a plurality of wires which are respectively connected with the corresponding through hole column or the terminal of the electronic component.
In a second aspect, the active and passive device vertical laminated embedded package structure according to the embodiment of the invention is prepared by the above manufacturing method of the active and passive device vertical laminated embedded package structure.
In a third aspect, the active and passive device vertical stack embedded package structure according to the embodiment of the invention includes: the packaging structure comprises a dielectric material body, a packaging cavity and a packaging cavity, wherein the dielectric material body is provided with at least two packaging cavities, the at least two packaging cavities are arranged along the thickness direction of the dielectric material body and are sequentially communicated, and the sizes of the two adjacent packaging cavities are different; the plurality of supporting parts are arranged on the medium material body and are positioned in the edge areas of two adjacent packaging cavities, and a first gap is arranged between the two adjacent supporting parts, wherein the edge areas of the two adjacent packaging cavities are used for representing that the first packaging cavity exceeds the area of the second packaging cavity under the condition that the first packaging cavity is projected to the second packaging cavity; at least two electronic components, encapsulate respectively in corresponding the encapsulation intracavity, at least one electronic components bearing in the supporting part.
The vertical lamination embedded packaging structure of the active and passive devices according to the embodiment of the invention at least has the following beneficial effects:
the embodiment of the invention vertically encapsulates at least two electronic components along the thickness direction of the medium material body, reduces the encapsulation space, is beneficial to realizing miniaturization design, is provided with a plurality of supporting parts in the medium material body, and is provided with the first gap used as the flow guide groove between the adjacent supporting parts, so that the one-time encapsulation of the plurality of electronic components after being mounted can be realized, the encapsulation process can be simplified, and the production cost can be reduced.
According to some embodiments of the invention, the electronic component is an active device or a passive device.
According to some embodiments of the invention, the dielectric material body comprises a plurality of layers of dielectric material of encapsulation layers, an intermediate layer is arranged between adjacent encapsulation layers, the at least two encapsulation cavities are respectively located in the corresponding encapsulation layers, and the plurality of support portions are respectively located in the corresponding intermediate layers.
According to some embodiments of the invention, a surface circuit layer is disposed on the surface of the dielectric material body, and the surface circuit layer includes a plurality of traces, and the plurality of traces are respectively connected to terminals of the corresponding electronic components.
According to some embodiments of the present invention, a plurality of through hole pillars are disposed in the dielectric material body, first ends of the through hole pillars are connected to terminals of the corresponding electronic component, second ends of the through hole pillars extend to a surface of the dielectric material body, a surface circuit layer is disposed on the surface of the dielectric material body, the surface circuit layer includes a plurality of traces, and the plurality of traces are respectively connected to the corresponding through hole pillars or the terminals of the electronic component.
According to some embodiments of the invention, a plurality of conduction columns are arranged in the dielectric material body, and are sequentially connected along the thickness direction of the dielectric material body.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a flowchart illustrating steps of a method for manufacturing a vertical stack embedded package structure of active and passive devices according to an embodiment of the present invention;
fig. 2 to 10 are schematic cross-sectional views of intermediate processes of one example of a method for manufacturing a vertical stack embedded package structure of an active/passive device according to an embodiment of the present invention;
fig. 11 is one of the schematic diagrams of the vertical stack embedded package structure of the active and passive devices according to the embodiment of the invention;
fig. 12 to 15 are schematic cross-sectional views of intermediate processes of another example of a method for manufacturing an active and passive device vertical stack embedded package structure according to an embodiment of the present invention;
fig. 16 is a second schematic diagram of an active-passive device vertical stack embedded package structure according to an embodiment of the invention;
fig. 17 is one of the schematic cross-sectional views a-a of fig. 16 of an active and passive device vertical stack embedded package structure according to an embodiment of the invention;
fig. 18 is one of cross-sectional views B-B of fig. 16 of an active-passive device vertical stack embedded package structure according to an embodiment of the present invention;
fig. 19 is a second cross-sectional view of the active and passive device vertical stack embedded package structure of fig. 16 at a-a according to the embodiment of the invention;
fig. 20 is a second cross-sectional view of the active-passive device vertical stack embedded package structure at B-B of fig. 16 according to the embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the orientation descriptions referred to, for example, the orientations or positional relationships indicated by the "thickness direction", "width", etc., are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, "a plurality" means one or more, "a plurality" means two or more, and greater than, less than, more than, etc. are understood as excluding the present number, and "greater than", "lower than", "inner", etc. are understood as including the present number. If the description of "first", "second", etc. is used for the purpose of distinguishing technical features, it is not intended to indicate or imply relative importance or to implicitly indicate the number of indicated technical features or to implicitly indicate the precedence of the indicated technical features.
In the description of the present invention, unless otherwise explicitly limited, terms such as "disposed," "attached," "connected," and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the terms in the present invention by combining the specific contents of the technical solutions.
In the description of the present invention, the consecutive reference numbers of the method steps are for convenience of examination and understanding, and the implementation order between the steps is adjusted without affecting the technical effect achieved by the technical solution of the present invention by combining the whole technical solution of the present invention and the logical relationship between the steps.
Referring to fig. 1, the present embodiment discloses a method for manufacturing a vertical stacked embedded package structure of active and passive devices, including step S100, step S200, step S300, step S400, and step S500. The following steps are specifically described:
s100, referring to fig. 2, a substrate 100 used as a first package layer is provided, wherein the substrate 100 includes a first dielectric material 110 and a first sacrificial metal block 120 embedded in the first dielectric material 110. In the present embodiment, the first dielectric material 110 is made of a polymer, wherein the polymer may be FR4, a gourmet powder, polyimide, a prepreg containing glass cloth, or a combination thereof. The first sacrificial metal block 120 may be a metal structure such as a copper block or a copper pillar. It should be noted that the "block" and "column" referred to in the embodiments of the present invention are not specifically limited to the corresponding structure, but are named based on general terms to facilitate the examination and understanding of the technical features of the structure. In practical application, the "blocks" and the "columns" can be interchanged according to the dimensional proportion of the corresponding structures in the vertical direction and the horizontal direction. Here, the "vertical direction" in the present embodiment refers to a direction perpendicular to the surface of the substrate 100, and the "horizontal direction" refers to a direction parallel to the surface of the substrate 100.
S200, referring to fig. 3, the substrate 100 is used as a previous-stage structure, and the intermediate layer and the encapsulation layer are processed to obtain a secondary semi-finished product, where the processing of the intermediate layer refers to step S210, and the processing of the encapsulation layer refers to step S220.
S210, the processing step of the intermediate layer comprises the following steps:
s211, processing an intermediate pattern layer on the previous stage structure, where the intermediate pattern layer includes an mth feature metal block, M is a positive integer, such as the first feature metal block 210 shown in fig. 3, the mth feature metal block covers the previous stage sacrificial metal block, for example, the first sacrificial metal block 120, and a plurality of cavity portions (not shown) are disposed in an edge region of the mth feature metal block. In this embodiment, the edge region of the mth feature metal block is used to characterize a region where the mth feature metal block exceeds the sacrificial metal block of the previous stage, such as a region L shown in fig. 3, in the case where the mth feature metal block is projected onto the sacrificial metal block of the previous stage. It is expected that the area of the mth feature metal block needs to be larger than that of the previous-stage sacrificial metal block to realize that the mth feature metal block covers the previous-stage sacrificial metal block. Specifically, the processing method of the middle graph layer comprises the following steps: and realizing surface metallization on the surface of the former-stage structure body by utilizing a magnetron sputtering process or a copper deposition process, and then processing an Mth characteristic metal block by utilizing a pattern transfer process, an electroplating deposition process and an etching process. It should be appreciated that the process flows of magnetron sputtering, copper deposition, pattern transfer, electroplating deposition and etching are well known techniques, and those skilled in the art can make appropriate selections from various alternative materials and manufacturing flows based on clear knowledge of parameters such as production lot size, substrate complexity and device resolution, and therefore, the embodiments of the present invention do not require a detailed description of the process flows. It is to be understood that the reference to the "first feature metal block" in the present embodiment is used to refer to a feature metal block disposed in a first intermediate layer or a first intermediate pattern layer, and the "feature metal block" is used to refer to a feature metal block of each intermediate layer or intermediate pattern layer in general, and the reference to the "mth sacrificial metal block" is used to refer to, in processing order, a first feature metal block disposed in the first intermediate pattern layer, for example, and a second feature metal block disposed in the second intermediate pattern layer, for example, when it is necessary to express a feature metal block disposed in the mth intermediate layer or intermediate pattern layer.
S212, please continue to refer to fig. 3, performing lamination and thinning process on the middle pattern layer to obtain a middle dielectric layer, and forming a supporting portion 230 at a portion of the middle dielectric layer located in the cavity portion. Since the middle pattern layer is provided with the line patterns, for example, the feature metal blocks, when the middle pattern layer is laminated using the first middle dielectric material 240, the first middle dielectric material 240 is in a flowing state during the hot pressing, and may be filled into the gaps between the line patterns, wherein, in the case where the first middle dielectric material 240 is filled into the cavity portion, the first middle dielectric material 240 may be shaped through the cavity portion, thereby forming the supporting portion 230. In this embodiment, the supporting portions 230 may be supporting blocks, supporting columns, or supporting bars, and a first gap is disposed between adjacent supporting portions 230. After lamination, the first intermediate dielectric material 240 is thinned to expose the surface of the circuit pattern, thereby facilitating subsequent processing of the sacrificial metal block and the conductive via. It should be noted that the first intermediate dielectric material 240 may be the same material as the first dielectric material 110.
S220, the processing steps of the packaging layer comprise: and processing a packaging layer on the intermediate medium layer, wherein the packaging layer comprises an N +1 th medium material and an N +1 th sacrificial metal block embedded in the medium material, N is a positive integer, and the N +1 th sacrificial metal block covers the characteristic metal block of the previous stage. For example, referring to fig. 4, after the intermediate layer processing is completed, the substrate 100 may be regarded as a first packaging layer, the first intermediate layer is processed on the basis of the first packaging layer, the first intermediate layer includes the first feature metal blocks 210, a second packaging layer is processed on the basis of the first intermediate layer, and the second packaging layer includes the second dielectric material 310 and the second sacrificial metal blocks 320 embedded in the second dielectric material 310. The second sacrificial metal block 320 covers the first feature metal block 210.
In practical applications, the number of the encapsulation layers may be multiple, and therefore, the method further includes the steps of:
and S230, taking the secondary semi-finished product as a primary structure, and processing the middle layer and the packaging layer until the lamination requirement is met.
For example, after the second package layer is processed, the secondary semi-finished product includes the substrate 100 as the first package layer, the first intermediate layer and the second package layer, the secondary semi-finished product is used as the previous-stage structure, the intermediate layer and package layer processing is performed, that is, the second intermediate layer is processed on the basis of the second package layer, the third package layer is processed on the basis of the second intermediate layer, and so on until the lamination requirements are met, for example, as shown in fig. 16, the third package layer includes a third dielectric material 410 and a third sacrificial metal block (not shown) embedded in the third dielectric material 410.
It is to be understood that reference to "the first sacrificial metal block" in this embodiment is intended to refer specifically to the sacrificial metal block disposed in the first package layer, i.e., the substrate 100, and "the sacrificial metal block" is intended to refer broadly to the sacrificial metal blocks of the various package layers, and that reference to "the nth sacrificial metal block" is intended to refer specifically to, for example, the second sacrificial metal block disposed in the second package layer, when it is desired to refer to the sacrificial metal block disposed in the nth package layer, in terms of processing order. The specific processing steps of the packaging layer are similar to those of the middle layer, namely, the surface metallization is realized by utilizing a magnetron sputtering process or a copper deposition process, then corresponding circuit patterns, namely a sacrificial metal block and a conductive column, are processed through a pattern transfer process, an electroplating deposition process and an etching process, and then lamination and thinning are carried out, wherein the difference between the two processes is that the circuit patterns need to be changed according to production information.
S300, referring to fig. 5 and fig. 6, all the sacrificial metal blocks and all the feature metal blocks are etched to obtain at least two package cavities 500, and a guiding trench 231 is formed between adjacent supporting portions 230. Fig. 6 is a top view of the package structure shown in fig. 5.
Specifically, a photosensitive shielding film (e.g., a dry film) is applied on the surface of the last packaging layer, a pattern transfer process is performed on the photosensitive shielding film to expose the regions of the sacrificial metal blocks, and then all the sacrificial metal blocks and all the feature metal blocks are removed by etching, so as to obtain at least two packaging cavities 500. For the first gap between adjacent support portions 230, the feature metal block is etched away, so that the first gap forms a flow guiding groove 231 communicated with the package cavity 500. After the etching process is completed, the photosensitive mask is removed to mount the electronic component 600. It should be noted that, according to different production data, a certain gap exists between the supporting portion 230 and the inner wall of the package chamber 500, or the supporting portion 230 is connected to the inside of the package chamber 500, and a first gap serving as the guiding groove 231 is disposed between adjacent supporting portions 230.
S400, referring to fig. 7, a corresponding electronic component 600 is attached to each package cavity 500, wherein at least one electronic component 600 is supported by the corresponding supporting portion 230, and the electronic component 600 is an active device or a passive device. For example, the electronic component 600 in each package cavity 500 is an active device, or the electronic component 600 in each package cavity 500 is a passive device, or one of the electronic components 600 in the package cavity 500 is an active device, and the remaining electronic components 600 in the package cavities 500 are passive devices. It should be appreciated that, when mounting the electronic components 600, if the length directions of the electronic components 600 are arranged along the same direction, the mounting positions of the electronic components 600 need to be arranged according to the size of the electronic components 600, for example, in fig. 7, the first packaging cavity 510 is located below the second packaging cavity 520, and the size of the first packaging cavity 510 is smaller than that of the second packaging cavity 520, so that the size of the first electronic component 610 mounted in the first packaging cavity 510 should be smaller than that of the second electronic component 620 mounted in the second packaging cavity 520, where the first electronic component 610 is an active device and the active surface of the first electronic component 610 faces downward, and the second electronic component 620 is a passive device. In this embodiment, the plurality of electronic components 600 are distributed, mounted, and subsequently packaged in the stacking direction, so that the packaging space is reduced, and the miniaturization design is facilitated. And S500, packaging the packaging cavity 500.
Referring to fig. 6, 7 and 8, in the present embodiment, the package cavities 500 are communicated with each other, and the flow guide groove 231 is formed between the adjacent supporting portions 230, when the package cavities 500 are packaged by using the plastic package material 530, the plastic package material 530 in a flowing state flows from the package cavity 500 on the upper layer to the package cavity 500 on the lower layer through the flow guide groove 231, so as to complete the packaging of the package cavity 500 on the bottom layer, thereby implementing the one-time packaging of the plurality of package cavities 500, which is beneficial to simplifying the packaging process and reducing the production cost. It is contemplated that the size of the package 500 is larger than the size of the electronic component 600 to facilitate mounting of the electronic component 600 in the package 500 and to facilitate filling of the molding compound 530 into the package 500 of the next layer through the gap between the electronic component 600 and the package 500 of the previous layer.
In practical applications, in order to realize electrical connections between different layers, the substrate 100 further includes a first conductive via 130 embedded in the first dielectric material 110, and correspondingly, in the processing step of the intermediate layer, the mth intermediate pattern layer further includes an mth conductive via, the mth conductive via corresponds to a position of a conductive via of a previous stage, for example, the first conductive via 220 corresponds to a position of the first conductive via 130 in fig. 3 or fig. 4, in the processing step of the encapsulation layer, the N +1 th encapsulation layer further includes an N +1 th conductive via embedded in the N +1 th dielectric material, the N +1 th conductive via corresponds to a position of the conductive via of the previous stage, for example, a position of the second conductive via 330 corresponds to a position of the first conductive via 220 in fig. 4. In this embodiment, the width of the mth conduction connection column is smaller than the width of the previous conduction column, so as to facilitate the alignment between the mth conduction connection column and the previous conduction column. In this embodiment, the "first conductive via" is used to refer to a conductive via disposed in the first package layer, and the "conductive via" is used to refer to a conductive via of each package layer, and when the conductive via located in the nth package layer needs to be expressed, the "nth conductive via" is used to refer to the conductive via, for example, the second conductive via located in the second package layer; similarly, when the conduction connecting column positioned in the Mth middle layer or the Mth middle graphic layer needs to be expressed, the 'Mth conduction connecting column' is adopted for carrying out the special purpose.
In the step S400, the corresponding electronic component 600 is attached to each package cavity 500, which includes the steps of:
s410, a temporary carrying surface (not shown) is processed at a position corresponding to the package cavity 500 on a surface of the substrate 100 opposite to the middle pattern layer, in this embodiment, the temporary carrying surface may be an adhesive tape or an adhesive tape, and the adhesive tape or the adhesive tape has a certain viscosity and can be easily separated from the dielectric material, so that the temporary carrying surface can be used for temporarily carrying the electronic component 600.
S420, attaching the first electronic component 600 to the temporary carrying surface. For example, in fig. 7, the first electronic component 610 is mounted on the temporary carrying surface, when the first electronic component 610 is an active device, an active surface of the active device faces the temporary carrying surface, so that pins of the active device can be exposed on the surface after being packaged, so as to facilitate electrical connection, and similarly, when the first electronic component 610 is a passive device, pins of the passive device are in contact connection with the temporary carrying surface.
S430, the next electronic component 600 is mounted above the previous electronic component 600 and supported by the corresponding support part 230. For example, in fig. 7, the second electronic component 620 is attached above the first electronic component 610, two end portions of the second electronic component 620 are respectively supported by the corresponding supporting portions 230, and a certain gap is reserved between the end portion of the second electronic component 620 and the inner wall of the second packaging cavity 520. In order to realize disposable packaging of the electronic component 600 after being mounted up and down, the flow guide grooves 231 are formed between the adjacent supporting parts 230, and the supporting parts 230 are used as stressed components for supporting the electronic component 600, so that the flow channel of the plastic packaging material 530 is reserved after the electronic component 600 is mounted.
Step S400, attaching the corresponding electronic component 600 in each package cavity 500, further comprising the steps of: the electronic component 600 is die bonded by silver paste or DAF (die attach film) material.
The step S500 of performing the encapsulation process on the encapsulation cavity 500 includes the steps of:
s510, laminating the plastic packaging material 530 on the last packaging layer to obtain a laminated semi-finished product;
and S520, laminating the laminated semi-finished product in a hot pressing mode, enabling the plastic packaging material 530 to be in a flowing state, and enabling the plastic packaging material to flow from the packaging cavity 500 on the upper layer to the packaging cavity 500 on the lower layer through the flow guide groove 231 under the action of pressure, so that one-time packaging of all the packaging cavities 500 is realized, the laminating process is facilitated to be simplified, and the production cost is reduced.
After the packaging cavity 500 is packaged, a surface circuit layer can be processed on a semi-finished product obtained by packaging, the processing steps of the surface circuit layer are different according to the packaging depth of the electronic component 600, and the embodiment provides the following two different examples:
one is as follows: step S500, performing encapsulation processing on the encapsulation cavity 500, and then further including the steps of:
s611, referring to fig. 8, thinning the semi-finished product obtained after the packaging process to obtain a first semi-finished product;
s612, performing laser drilling on the first semi-finished product to obtain a first through hole (not shown), where the first through hole is communicated with a terminal of the corresponding electronic component 600;
s613, referring to fig. 9, a through hole pillar 720 is processed in the first through hole, and a surface circuit layer is processed on the surface of the first semi-finished product, where the surface circuit layer includes a plurality of wires 710, and the plurality of wires 710 are respectively connected to the corresponding through hole pillar 720 or the terminal of the electronic component 600. Of course, when the conductive vias are processed, the traces 710 may be connected to the corresponding conductive vias, for example, different traces 710 in fig. 9 are respectively connected to the first conductive via 130 and the second conductive via 330.
The processing method is suitable for burying the terminal of the electronic component 600 in the first semi-finished product, and the routing 710 of the surface circuit layer needs to be indirectly connected with the terminal of the corresponding electronic component 600 through the through hole column 720. The via post 720 may be a solid copper post, a laser via, or a buried via, and specifically, the via post 720 may be formed by an electroplating deposition process.
The second step is as follows: step S500, performing encapsulation processing on the encapsulation cavity 500, and then further including the steps of:
s621, thinning the semi-finished product obtained after the packaging treatment to obtain a first semi-finished product;
s622, referring to fig. 11, a surface circuit layer is processed on the surface of the first semi-finished product, the surface circuit layer includes a plurality of traces 710, and the plurality of traces 710 are respectively connected to the terminals of the corresponding electronic component 600. Of course, when the conductive vias are processed, the traces 710 may be connected to the corresponding conductive vias, for example, different traces 710 in fig. 9 are respectively connected to the first conductive via 130 and the second conductive via 330.
The processing method is suitable for exposing the terminal of the electronic component 600 on the surface of the first semi-finished product, and the wiring 710 of the surface circuit layer can be directly connected with the terminal of the electronic component 600.
It should be understood that, referring to fig. 10 or fig. 11, in order to protect the surface circuit layer, a surface protection layer 800 may be processed on the surface circuit layer, and the surface protection layer 800 may be a solder resist ink layer, an OSP layer, a gold plating layer, or the like.
Referring to fig. 12 to 15, the manufacturing process shown in fig. 12 to 15 is similar to the manufacturing process shown in fig. 2 to 10, and the electronic components 600 packaged by both of them include an active device and a passive device, which are different in that in the manufacturing process shown in fig. 2 to 10, the passive device is located above the active device, and in the manufacturing process shown in fig. 12 to 15, the active device is located above the passive device, and the active surface of the active device faces upward.
The embodiment of the invention also discloses an active and passive device vertical laminated embedded packaging structure which is prepared by the manufacturing method of the active and passive device vertical laminated embedded packaging structure.
Example 2
Referring to fig. 15 and fig. 16, an embodiment of the present invention discloses an active and passive device vertical stacked embedded package structure, including a dielectric material body 900, a support portion 230, and at least two electronic components 600, where the dielectric material body 900 is provided with at least two package cavities 500, the at least two package cavities 500 are arranged along a thickness direction of the dielectric material body 900 and are sequentially communicated, two adjacent package cavities 500 are different in size, the number of the support portion 230 is multiple, the multiple support portions 230 are provided on the dielectric material body 900 and are located in edge regions of the two adjacent package cavities 500, and a first gap is provided between the adjacent support portions 230, where the edge regions of the two adjacent package cavities 500 are used for representing that, when the first package cavity 500 is projected on the second package cavity 500, the first package cavity 500 exceeds a region of the second package cavity 500, for example, a region L in fig. 15; at least two electronic components 600 are respectively packaged in the corresponding packaging cavities 500, at least one electronic component 600 is supported on the supporting parts 230, the structural characteristic is designed based on the characteristics of the packaging process, in order to enable the electronic component 600 to be packaged at one time after being mounted, a first gap between adjacent supporting parts 230 is used as a flow guide groove 231 (see fig. 6), the supporting parts 230 are used as stress parts for supporting the electronic component 600, the flowing channel of the plastic packaging material 530 is reserved after the electronic component 600 is mounted, and when the plastic packaging material 530 used for filling the packaging cavities 500 is in a flowing state, the plastic packaging material can flow to the packaging cavities 500 at the lower layer through the flow guide groove 231 through the packaging cavities 500 at the upper layer, so that the one-time packaging of all the packaging cavities 500 is realized, the pressing process is facilitated to be simplified, and the production cost is reduced. The method for manufacturing the active and passive device vertical stack embedded package structure of this embodiment can refer to embodiment 1, and the description of this embodiment is omitted.
In the embodiment of the present invention, at least two electronic components 600 are vertically packaged along the thickness direction of the dielectric material body 900, for example, in fig. 16, the first electronic component 610 is located below the second electronic component 620, and the second electronic component 620 is located below the third electronic component 630, so that the packaging space is reduced, which is beneficial to implementing a miniaturized design, and the plurality of supporting portions 230 are arranged in the dielectric material body 900, and the first gap serving as the flow guide groove 231 is arranged between the adjacent supporting portions 230, so that the plurality of electronic components 600 can be packaged at one time after being mounted, which is beneficial to simplifying the packaging process and reducing the production cost.
In this embodiment, the electronic component 600 is an active device or a passive device. For example, the electronic component 600 in each package cavity 500 is an active device, or the electronic component 600 in each package cavity 500 is a passive device, or one of the electronic components 600 in the package cavity 500 is an active device, and the remaining electronic components 600 in the package cavities 500 are passive devices. It should be understood that, when the electronic components 600 are mounted, if the length directions of the electronic components 600 are arranged along the same direction, the mounting positions of the electronic components 600 need to be arranged according to the size of the electronic components 600, for example, referring to fig. 7 and 15, the first package chamber 510 is located below the second package chamber 520, and the size of the first package chamber 510 is smaller than that of the second package chamber 520, so that the size of the first electronic component 610 mounted in the first package chamber 510 should be smaller than that of the second electronic component 620 mounted in the second package chamber 520. In this embodiment, the plurality of electronic components 600 are distributed, mounted, and subsequently packaged in the stacking direction, so that the packaging space is reduced, and the miniaturization design is facilitated.
The dielectric material body 900 is made of a dielectric material, wherein the dielectric material body 900 includes a plurality of dielectric materials of encapsulation layers, for example, in fig. 16, the dielectric material body 900 includes a first dielectric material 110 of a first encapsulation layer, a second dielectric material 310 of a second encapsulation layer, and a third dielectric material 410 of a third encapsulation layer, an intermediate layer is disposed between adjacent encapsulation layers, at least two encapsulation cavities 500 are respectively located in the corresponding encapsulation layers, and the plurality of supporting portions 230 are respectively located in the corresponding intermediate layers. Different packaging layers can adopt the same or different dielectric materials, and the dielectric material body 900 can be formed by laminating multiple layers of dielectric materials. A conductive connection post, such as the first conductive connection post 220 shown in fig. 15, is further disposed in the intermediate layer, and two ends of the first conductive connection post 220 are respectively connected to the first conductive via 130 and the second conductive via 330.
In order to enable the electronic component 600 to realize signal transmission, a surface circuit layer is disposed on the surface of the dielectric material body 900, the surface circuit layer includes a plurality of wires 710, and the plurality of wires 710 are respectively connected to terminals of the corresponding electronic component 600. The connection manner of the traces 710 on the surface circuit layer is different according to the packaging depth of the electronic component 600, and the embodiment provides the following two different examples:
one is as follows: referring to fig. 16, a plurality of through hole pillars 720 are disposed in the dielectric material body 900, first ends of the through hole pillars 720 are connected to terminals of the corresponding electronic component 600, second ends of the through hole pillars 720 extend to the surface of the dielectric material body 900, a surface circuit layer is disposed on the surface of the dielectric material body 900, the surface circuit layer includes a plurality of traces 710, and the plurality of traces 710 are respectively connected to the terminals of the corresponding through hole pillars 720 or the corresponding electronic component 600.
The processing method is suitable for burying the terminal of the electronic component 600 in the first semi-finished product, and the routing 710 of the surface circuit layer needs to be indirectly connected with the terminal of the corresponding electronic component 600 through the through hole column 720.
Referring to fig. 17 and 18, a first view of two active devices with different package depths respectively connected to corresponding traces 710 of a surface circuit layer through via posts 720 is shown; referring to fig. 19 and 20, a second view of two active devices with different package depths respectively connected to corresponding traces 710 of the surface circuit layer through via posts 720 is shown. As can be seen from the drawings, the electronic components 600 with different package depths may be regularly arranged in the stacking direction (as shown in the first view) or may be arranged in a staggered manner (as shown in the second view), which is beneficial to flexibly adjusting the wiring of different electronic components 600. The via post 720 may be a solid copper post, a laser via, or a buried via.
The second step is as follows: referring to fig. 11, a surface circuit layer is disposed on the surface of the dielectric material body 900, the surface circuit layer includes a plurality of traces 710, and the plurality of traces 710 are respectively connected to the terminals of the electronic component 600.
The processing method is suitable for exposing the terminal of the electronic component 600 on the surface of the first semi-finished product, and the wiring 710 of the surface circuit layer can be directly connected with the terminal of the electronic component 600.
Referring to fig. 15 and fig. 16, in order to connect the traces 710 on two different surfaces of the dielectric material body 900, a plurality of conductive vias are disposed in the dielectric material body 900, and two ends of each conductive via are respectively connected to the corresponding trace 710. The plurality of conductive vias are connected in series in the thickness direction of the dielectric material body 900. The size of the conductive pillars is related to the thickness of the dielectric material body 900, wherein the width between adjacent conductive pillars may be the same according to different thicknesses of the dielectric material body 900, for example, a connection pad is processed between adjacent conductive pillars to facilitate alignment between conductive pillars between different layers; in some examples, the width dimension of the via post is sequentially decreased or sequentially increased, so as to facilitate interlayer alignment during the processing. For example, in fig. 16, the width dimension of the third conductive via 430 is smaller than the width dimension of the second conductive via 330, and the width dimension of the second conductive via 330 is smaller than the width dimension of the first conductive via 130, so that a connection pad between adjacent conductive vias can be omitted in a processing process, which is beneficial to improving the wiring density of a circuit.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (14)
1. A manufacturing method of a vertical lamination embedded packaging structure of an active and passive device is characterized by comprising the following steps:
providing a substrate (100) used as a first encapsulation layer, wherein the substrate (100) comprises a first dielectric material (110) and a first sacrificial metal block (120) embedded in the first dielectric material (110);
processing the substrate (100) as a previous-stage structure with an intermediate layer and an encapsulation layer to obtain a secondary semi-finished product, wherein,
the processing step of the intermediate layer comprises the following steps: processing an Mth middle pattern layer on the previous stage structure, wherein the Mth middle pattern layer comprises an Mth characteristic metal block, the Mth characteristic metal block covers the previous stage sacrificial metal block, a plurality of cavity parts are arranged in the edge area of the Mth characteristic metal block, and the edge area of the Mth characteristic metal block is used for representing that the Mth characteristic metal block exceeds the area of the previous stage sacrificial metal block under the condition that the Mth characteristic metal block is projected on the previous stage sacrificial metal block; laminating and thinning the middle pattern layer to obtain a middle medium layer, wherein a supporting part (230) is formed at the part of the middle medium layer positioned in the cavity part, and M is a positive integer;
the processing steps of the packaging layer comprise: processing an Nth packaging layer on the intermediate medium layer, wherein the Nth packaging layer comprises an (N + 1) th medium material and an (N + 1) th sacrificial metal block embedded in the (N + 1) th medium material, the (N + 1) th sacrificial metal block covers the characteristic metal block of the previous stage, and N is a positive integer;
etching all the sacrificial metal blocks and all the characteristic metal blocks to obtain at least two packaging cavities (500), and forming flow guide grooves (231) between the adjacent supporting parts (230);
attaching a corresponding electronic component (600) in each packaging cavity (500), wherein at least one electronic component (600) is supported by the corresponding supporting part (230) and the diversion trench (231) is reserved for serving as a packaging channel;
and packaging the at least two packaging cavities (500) by adopting a plastic packaging material (530) in a hot pressing mode.
2. The method for manufacturing an active and passive device vertical stack embedded package structure according to claim 1, wherein the substrate (100) further includes a first conductive via (130) embedded in the first dielectric material (110), the middle layer processing step further includes an mth conductive via, the mth conductive via corresponds to a position of a conductive via of a previous stage, the N +1 encapsulation layer further includes an N +1 conductive via embedded in the N +1 dielectric material, and the N +1 conductive via corresponds to a position of a conductive via of a previous stage.
3. The method for manufacturing an active and passive device vertical stack embedded package structure according to claim 1, further comprising the steps of:
and processing the intermediate layer and the packaging layer by taking the secondary semi-finished product as a primary structure until the lamination requirement is met.
4. The method for manufacturing the active and passive device vertical lamination embedded packaging structure according to claim 1, wherein the step of attaching the corresponding electronic component (600) in each packaging cavity (500) comprises the steps of:
processing a temporary bearing surface at a position, corresponding to the packaging cavity (500), of one surface of the substrate (100) opposite to the middle graph layer;
mounting a first electronic component (600) on the temporary bearing surface;
and mounting the next electronic component (600) above the previous electronic component (600) and supporting the corresponding support part (230).
5. The method for manufacturing the active and passive device vertical stack embedded package structure according to claim 4, wherein the step of attaching the corresponding electronic component (600) in each package cavity (500) further comprises the steps of:
and carrying out die bonding on the electronic component (600) through silver paste or DAF material.
6. The method for manufacturing an active and passive device vertical stack embedded package structure according to claim 1, wherein the packaging process for the at least two package cavities (500) comprises the steps of:
laminating plastic packaging materials (530) on the last layer of packaging layer to obtain a laminated semi-finished product;
and pressing the laminated semi-finished product in a hot pressing mode.
7. The method for manufacturing an active and passive device vertical stack embedded package structure according to any one of claims 1 to 6, wherein the at least two package cavities (500) are subjected to a packaging process, and then the method further comprises the following steps:
thinning the semi-finished product obtained after the packaging treatment to obtain a first semi-finished product;
processing a surface circuit layer on the surface of the first semi-finished product, wherein the surface circuit layer comprises a plurality of wires (710), and the wires (710) are respectively connected with the terminals of the corresponding electronic component (600).
8. The method for manufacturing an active and passive device vertical stack embedded package structure according to any one of claims 1 to 6, wherein the at least two package cavities (500) are subjected to a packaging process, and then the method further comprises the following steps:
thinning the semi-finished product obtained after the packaging treatment to obtain a first semi-finished product;
performing laser drilling on the first semi-finished product to obtain a first through hole, wherein the first through hole is communicated with a terminal of the corresponding electronic component (600);
processing a through hole column (720) in the first through hole, and processing a surface circuit layer on the surface of the first semi-finished product, wherein the surface circuit layer comprises a plurality of wires (710), and the wires (710) are respectively connected with the corresponding through hole column (720) or the terminal of the electronic component (600).
9. An active and passive device vertical lamination embedded packaging structure, which is characterized in that the active and passive device vertical lamination embedded packaging structure is prepared by the manufacturing method of the active and passive device vertical lamination embedded packaging structure of any one of claims 1 to 8.
10. An active and passive device vertical lamination embedding packaging structure is characterized by comprising:
the dielectric material body (900) comprises dielectric materials of a plurality of packaging layers, an intermediate dielectric layer is arranged between every two adjacent packaging layers, the dielectric material body (900) is provided with at least two packaging cavities (500), the at least two packaging cavities (500) are respectively positioned in the corresponding packaging layers, the at least two packaging cavities (500) are arranged along the thickness direction of the dielectric material body (900) and are sequentially communicated, and the sizes of the two adjacent packaging cavities (500) are different;
a plurality of supporting parts (230) formed by the middle medium layer at the edge area of the packaging cavity (500), wherein a first gap serving as a flow guide groove (231) is arranged between every two adjacent supporting parts (230), and the edge area of the two adjacent packaging cavities (500) is used for representing the area of the first packaging cavity (500) beyond the second packaging cavity (500) under the condition that the first packaging cavity (500) is projected on the second packaging cavity (500);
at least two electronic components (600) are respectively packaged in the corresponding packaging cavities (500) by plastic packaging materials (530), and at least one electronic component (600) is supported on the supporting part (230).
11. The active-passive device vertical stack-embedded package structure of claim 10, wherein the electronic component (600) is an active device or a passive device.
12. The active-passive device vertical stack embedded package structure according to claim 10 or 11, wherein a surface circuit layer is disposed on a surface of the dielectric material body (900), the surface circuit layer includes a plurality of traces (710), and the plurality of traces (710) are respectively connected to terminals of the corresponding electronic component (600).
13. The active-passive device vertical stack embedded package structure according to claim 10 or 11, wherein a plurality of via posts (720) are disposed in the dielectric material body (900), first ends of the via posts (720) are connected to terminals of the corresponding electronic component (600), second ends of the via posts (720) extend to a surface of the dielectric material body (900), a surface circuit layer is disposed on the surface of the dielectric material body (900), the surface circuit layer includes a plurality of traces (710), and the plurality of traces (710) are respectively connected to the terminals of the corresponding via posts (720) or the electronic component (600).
14. The active-passive device vertical stack embedded package structure of claim 10, wherein a plurality of conductive vias are disposed in the dielectric material body (900), and the plurality of conductive vias are sequentially connected along a thickness direction of the dielectric material body (900).
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| US6890798B2 (en) * | 1999-06-08 | 2005-05-10 | Intel Corporation | Stacked chip packaging |
| US6531341B1 (en) * | 2000-05-16 | 2003-03-11 | Sandia Corporation | Method of fabricating a microelectronic device package with an integral window |
| TWI276192B (en) * | 2005-10-18 | 2007-03-11 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board and method for fabricating the same |
| JP4926692B2 (en) * | 2006-12-27 | 2012-05-09 | 新光電気工業株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
| TWI417970B (en) * | 2009-09-04 | 2013-12-01 | Unimicron Technology Corp | Package substrate structure and method of forming same |
| US9161461B2 (en) * | 2012-06-14 | 2015-10-13 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic structure with stepped holes |
| US9240392B2 (en) * | 2014-04-09 | 2016-01-19 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd. | Method for fabricating embedded chips |
| CN105161474B (en) * | 2015-07-08 | 2019-01-04 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its production technology |
| US10475770B2 (en) * | 2017-02-28 | 2019-11-12 | Amkor Technology, Inc. | Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof |
| CN113035794B (en) * | 2021-02-01 | 2023-04-07 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
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