CN211428121U - Low-thickness 3D stacking and packaging structure - Google Patents
Low-thickness 3D stacking and packaging structure Download PDFInfo
- Publication number
- CN211428121U CN211428121U CN202020471426.6U CN202020471426U CN211428121U CN 211428121 U CN211428121 U CN 211428121U CN 202020471426 U CN202020471426 U CN 202020471426U CN 211428121 U CN211428121 U CN 211428121U
- Authority
- CN
- China
- Prior art keywords
- layer
- hole
- chip
- plastic package
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 239000004033 plastic Substances 0.000 claims abstract description 75
- 229910000679 solder Inorganic materials 0.000 claims abstract description 47
- 229910052802 copper Inorganic materials 0.000 claims description 58
- 239000010949 copper Substances 0.000 claims description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 55
- 238000000465 moulding Methods 0.000 claims description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 248
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000013067 intermediate product Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 239000000047 product Substances 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229940125773 compound 10 Drugs 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- ZLVXBBHTMQJRSX-VMGNSXQWSA-N jdtic Chemical compound C1([C@]2(C)CCN(C[C@@H]2C)C[C@H](C(C)C)NC(=O)[C@@H]2NCC3=CC(O)=CC=C3C2)=CC=CC(O)=C1 ZLVXBBHTMQJRSX-VMGNSXQWSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The utility model discloses a low thickness 3D piles up packaging structure, include: the circuit comprises a solder mask layer and a first rewiring layer positioned on one side of the solder mask layer, wherein the solder mask layer is provided with a first hole site and a second hole site; the first plastic package layer is provided with an I/O port at one side of the first chip, which faces away from the solder mask layer, and a third hole site exposed out of the conductive block; the second rewiring layer is positioned on the first plastic packaging layer and is connected with the conductive block; the second plastic packaging layer is provided with a fourth hole site for exposing an I/O port of the second chip and the first rewiring layer; and the third redistribution layer is positioned on the second plastic packaging layer and is connected with the first redistribution layer. The utility model discloses can reduce low thickness 3D and pile up packaging structure's encapsulation thickness and switch on the internal resistance, shorten the physical connection and improve the product yield.
Description
Technical Field
The utility model relates to an integrated circuit encapsulation field, concretely relates to low thickness 3D piles up packaging structure.
Background
A Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is a Field-Effect Transistor (Field-Effect Transistor) that can be widely used in analog circuits and digital circuits.
At present, for mos chips, when the mos chips are stacked and packaged with a controller chip, a physical connection line is long, so that the response speed is slow; the height of the packaging structure is large, so that the product size is large, and the miniaturization development requirement of electronic products is difficult to meet.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a low thickness 3D piles up packaging structure, can greatly reduced low thickness 3D pile up packaging structure's encapsulation thickness with switch on the internal resistance, shorten the physics and connect to can improve the product yield.
To achieve the purpose, the utility model adopts the following technical proposal:
provided is a low thickness 3D stack package structure, including:
the circuit comprises a solder mask layer and a first rewiring layer positioned on one side of the solder mask layer, wherein a first hole position and a second hole position penetrating through the solder mask layer along the thickness direction of the solder mask layer are arranged at intervals;
the first plastic package layer is positioned on one side, away from the first rewiring layer, of the solder resist layer, the first chip which is packaged in the first plastic package layer and is pasted at the first hole site through solder paste and provided with a double-sided I/O port, and the conductive block which is pasted at the second hole site through solder paste, and the first plastic package layer is provided with an I/O port on one side, away from the solder resist layer, of the first chip and a third hole site exposed by the conductive block;
the second rewiring layer is positioned on the first plastic packaging layer and is connected with the conductive block through the conductive column in the third hole;
the second plastic package layer is positioned on one side, far away from the first chip, of the first rewiring layer, and the second chip is provided with a single-sided I/O port;
and the third redistribution layer is positioned on the second plastic packaging layer and is connected with the first redistribution layer through the conductive column in the fourth hole.
As a preferred scheme of the low-thickness 3D stacked package structure, the package structure further includes a first copper layer and a second copper layer, the first copper layer is located on the first plastic package layer, the third hole is formed in both the first copper layer and the first plastic package layer, the second copper layer is located on the second plastic package layer, and the fourth hole is formed in both the second copper layer and the second plastic package layer.
As a preferable scheme of the low-thickness 3D stacked package structure, the structure further includes a first seed layer and a second seed layer, the first seed layer is located at the third hole and on the surface of the first copper layer, and the second seed layer is located at the fourth hole and on the surface of the second copper layer.
As a preferable scheme of the low-thickness 3D stacked package structure, the package structure further includes a third plastic package layer, a fourth plastic package layer, and a conductive end, the third plastic package layer is located on the first plastic package layer and covers the second redistribution layer, the third plastic package layer is provided with a fifth hole for exposing a part of the second redistribution layer, the conductive end is located in the fifth hole, and the fourth plastic package layer is located on the second plastic package layer and covers the third redistribution layer.
As a preferable aspect of the low-thickness 3D stacked package structure, the conductive terminal includes a copper layer on the surface of the fifth hole and a tin layer on the copper layer.
As a preferable scheme of the low-thickness 3D stacked package structure, the conductive block is made of Cu, Ag, or Au.
The utility model has the advantages that: the utility model discloses a low thickness 3D piles up packaging structure's thickness is lower, has effectively shortened the physical connection between the chip, and can effectively solve the deep hole electroplating problem to high aspect ratio, through implanting the conducting block in advance, can greatly reduced electroplate the degree of difficulty, improves the product yield.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a flowchart illustrating a method for manufacturing a low-thickness 3D stacked package structure according to an embodiment of the present invention.
Fig. 2 is a specific flowchart of step S50 in the method for manufacturing a low-thickness 3D stacked package structure according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of an intermediate product of a conductive layer attached to a carrier according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of an intermediate product formed by attaching a solder resist layer to a conductive layer according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of an intermediate product after the solder mask hole opening process according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of an intermediate product after solder paste is attached to the first hole site and the second hole site and the first chip and the conductive block are attached thereto according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of an intermediate product after the first chip and the conductive block are molded according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of an intermediate product after bonding and flipping and mounting a first copper layer on a first plastic package layer according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of an intermediate product after a second chip is attached to a first redistribution layer through an insulating layer according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of an intermediate product after a second chip is molded and a second copper layer is attached to the second chip according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of an intermediate product after a third hole site and a fourth hole site are formed according to an embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of an intermediate product after manufacturing the first seed layer and the second seed layer according to an embodiment of the invention.
Fig. 13 is a schematic cross-sectional view of an intermediate product after manufacturing a second redistribution layer and a third redistribution layer according to an embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view of an intermediate product after manufacturing the third plastic package layer and the fourth plastic package layer according to an embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view of a product manufactured by forming a fifth hole site and manufacturing a conductive terminal according to an embodiment of the present invention.
In the figure:
1. a carrier plate; 21. a conductive layer; 22. a first rewiring layer; 3. a solder resist layer; 4. tin paste; 5. a first chip; 6. a conductive block; 7. a first plastic packaging layer; 8. a second chip; 9. an insulating layer; 10. a second plastic packaging layer; 11. a second rewiring layer; 12. a third triple wiring layer; 13. a first copper layer; 14. a second copper layer; 15. a first seed layer; 16. a second seed layer; 17. a third plastic packaging layer; 18. a fourth plastic packaging layer; 19. and a conductive terminal.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The first chip 5 in this embodiment is a chip with a double-sided I/O port, for example, the first chip 51 is a mos chip but is not limited to a mos chip; the second chip 8 is a chip with a single-sided I/O port, for example, the second chip 8 is a controller chip but not limited to a controller chip; next, the technical solution of the present invention will be described in detail by taking the mos chip and the controller chip as examples.
As shown in fig. 1, the embodiment discloses a method for manufacturing a low-thickness 3D stacked package structure, which includes the following steps:
s10, referring to fig. 3-5, providing a carrier board 1, sequentially attaching a conductive layer 21 and a solder mask layer 3 on one side of the carrier board 1 along a thickness direction thereof, and performing a hole opening process on the solder mask layer 3 to form a first hole site and a second hole site for partially exposing the conductive layer 21; the material of the carrier 1 may be one of bt (bimoleimide Triazine resin), FR4, FR5, PP, EMC, ABF or PI material, but is not limited thereto; the opening positions and the number of the first hole sites correspond to the positions and the number of the first chips 5 to be mounted one by one, and the opening positions and the number of the second hole sites correspond to the positions and the number of the conductive blocks 6 to be mounted one by one; the solder mask layer 3 is made of green oil, namely acrylic acid oligomer, is a liquid photo solder mask, forms the solder mask layer 3 after curing, and forms a first hole site and a second hole site through exposure and opening according to the design positions of the first chip 5 and the conductive block 6;
s20, referring to fig. 6, coating solder paste 4 on the first hole site and the second hole site respectively; mounting a first chip 5 with a double-sided I/O port at the position of the solder paste 4 corresponding to the first hole position and mounting a conductive block 6 at the position of the solder paste 4 corresponding to the second hole position, and plastically packaging the first chip 5 and the conductive block 6 to form a first plastic packaging layer 7 with reference to fig. 7; the solder paste 4 is used for preliminarily fixing the first chip 5 and the conductive block 6, and is further protected and fixed by the first plastic package layer 7, wherein the solder paste 4 conducts electricity to the first chip 5 and the conductive block 6;
s30, referring to fig. 8, removing the bond, fixing the semi-finished product by turning it over, and opening the conductive layer 21 to form a first redistribution layer 22; the method for opening the conductive layer 21 by using the hole covering method exposure etching specifically includes: manufacturing a photosensitive film on the conductive layer 21, removing part of the photosensitive film through exposure and development to expose part of the conductive layer 21, and etching the exposed part of the conductive layer 21 to complete hole opening to form a first rewiring layer 22; finally, removing the residual photosensitive film;
s40, referring to fig. 9 and 10, providing a second chip 8 with a single-sided I/O port, attaching the second chip 8 to a side of the first redistribution layer 22 away from the first chip 5 through an insulating layer 9, and performing plastic package on the second chip 8 to form a second plastic package layer 10;
s50, referring to fig. 11 to 15, respectively forming a second redistribution layer 11 connecting the I/O port of the first chip 5 and the conductive bump 6, and a third redistribution layer 12 connecting the I/O port of the second chip 8 and the first redistribution layer 22, and performing plastic encapsulation and electrical extraction on the second redistribution layer 11 and the third redistribution layer 12.
In this embodiment, the I/O port of the second chip 8 is connected to the first redistribution layer 22 through the third redistribution layer 12, the first redistribution layer 22 is connected to the conductive block 6 through the solder paste 4, the conductive block 6 is connected to the I/O port on one side of the first chip 5 through the second redistribution layer 11, the I/O port on the other side of the first chip 5 is connected to the first redistribution layer 22 through the solder paste 4, and the second redistribution layer 11 and the third redistribution layer 12 are electrically led out, so that the 3D stacked package of the first chip 5 and the second chip 8 is realized. In the embodiment, a double-side fan-out rewiring technology is adopted, so that the packaging thickness and the conduction internal resistance can be greatly reduced, the physical connection is shortened, and for the problem of electroplating of the through hole with the high depth-to-width ratio, the method of implanting the conductive block 6 in advance is adopted, so that the electroplating difficulty can be reduced, and the product yield is improved.
Further, in order to improve the connection stability between the second redistribution layer 11 and the first chip 5 and the conductive bump 6, in step S20 of the present embodiment, after the first molding layer 7 is formed, a first copper layer 13 is further mounted on the first molding layer 7 (fig. 8).
Further, in order to improve the connection stability between the third redistribution layer 12 and the second chip 8 and the first redistribution layer 22, in step S40 of the present embodiment, after the second molding compound 10 is manufactured, the second copper layer 14 is further mounted on the second molding compound 10 (fig. 10).
As shown in fig. 2, step S50 specifically includes the following steps:
s50a, referring to fig. 11, forming a third hole for exposing the I/O opening of the first chip 5 and the conductive bump 6 by opening the first copper layer 13 and the first plastic package layer 7, and forming a fourth hole for exposing the I/O opening of the second chip 8 and the first redistribution layer 22 by opening the second copper layer 14 and the second plastic package layer 10; specifically, laser drilling is carried out on a first copper layer 13 and the first plastic package layer 7 to form a third hole site, and laser drilling is carried out on a second copper layer 14 and the second plastic package layer 10 to form a fourth hole site;
s50b, referring to fig. 12 and 13, sequentially forming a first seed layer 15 and a second redistribution layer 11 on the surfaces of the first copper layer 13 and the third hole, and sequentially forming a second seed layer 16 and a third redistribution layer 12 on the surfaces of the second copper layer 14 and the fourth hole; firstly, a first seed layer 15 is manufactured on the surfaces of a first copper layer 13 and the third hole, then a conductive column is manufactured in the third hole, and a second redistribution layer 11 is manufactured on the surfaces of the first copper layer 13 and the conductive column; manufacturing a second seed layer 16 on the surfaces of the second copper layer 14 and the fourth hole, manufacturing a conductive column in the fourth hole, and manufacturing a third redistribution layer 12 on the surfaces of the second copper layer 14 and the conductive column; the manufacturing methods of the first seed layer 15, the second seed layer 16, the second rewiring layer 11 and the third rewiring layer 12 are conventional technical means in the field, and are not described in detail;
s50c, referring to fig. 14, performing plastic package on the second redistribution layer 11 to form a third plastic package layer 17, protecting the second redistribution layer 11, and performing plastic package on the third redistribution layer 12 to form a fourth plastic package layer 18, protecting the third redistribution layer 12;
s50d, referring to fig. 15, forming a fifth hole exposing a part of the second redistribution layer 11 by opening the third plastic package layer 17, and forming a conductive terminal 19 in the fifth hole to complete the package; specifically, a laser drilling method is adopted to perform hole opening processing on the third plastic package layer 17 to form a fifth hole site, then a copper layer is manufactured on the surface of the fifth hole site through electroplating, a tin layer is manufactured on the surface of the copper layer through electroplating, and the copper layer and the tin layer of the fifth hole site are filled to form the conductive terminal 19 so as to electrically lead out the first chip 5 and the second chip 8. The copper layer can improve the bonding force between the tin layer and the second rewiring layer 11.
Alternatively, the materials of the first Molding layer 7, the second Molding layer 10, the third Molding layer 17 and the fourth Molding layer 18 are the same, and may include any one of polyimide, silicone, and EMC (Epoxy Molding Compound), which is preferred in this embodiment.
Optionally, the material of the conductive block 6 in this embodiment is Cu, Ag, or Au.
As shown in fig. 15, the present embodiment further provides a low-thickness 3D stacked package structure manufactured by the manufacturing method of the above embodiment, including:
the circuit comprises a solder mask layer 3 and a first rewiring layer 22 positioned on one side of the solder mask layer 3, wherein a first hole site and a second hole site penetrating through the solder mask layer 3 along the thickness direction of the solder mask layer are formed at intervals;
the first plastic package layer 7 is positioned on one side, away from the first rewiring layer 22, of the solder mask layer 3, the first chip 5 which is packaged in the first plastic package layer 7 and is attached to the first hole position through solder paste 4 and provided with a double-sided I/O port, and the conductive block 6 which is attached to the second hole position through solder paste 4, wherein the first plastic package layer 7 is provided with an I/O port on one side, away from the solder mask layer 3, of the first chip 5 and a third hole position exposed out of the conductive block 6;
a second redistribution layer 11 located on the first molding compound layer 7 and connected to the conductive block 6 through the conductive pillar in the third hole;
a second plastic package layer 10 and a second chip 8 with a single-sided I/O port, which are located on a side of the first redistribution layer 22 away from the first chip 5, wherein the second chip 8 is packaged in the second plastic package layer 10 opposite to the first chip 5 and is attached to the first redistribution layer 22 through an insulating layer 9, and the second plastic package layer 10 is provided with a fourth hole for exposing the I/O port of the second chip 8 and the first redistribution layer 22;
and a third redistribution layer 12 located on the second plastic package layer 10 and connected to the first redistribution layer 22 through the conductive pillar in the fourth hole.
In this embodiment, the first chip 5 is used as a mos chip having a double-sided I/O port, one side of the I/O port is connected to the first redistribution layer 22 through the solder paste 4 in the first hole on the solder resist layer 3, the first redistribution layer 22 is connected to the conductive block 6 and the second redistribution layer 11 through the solder paste 4 in the second hole, and the other side of the I/O port of the first chip 5 is connected to the second redistribution layer 11 through the conductive pillar in the third hole; the second chip 8 is used as a controller chip and is attached to the first chip 5 through the insulating layer 9, the I/O port of the second chip is located on one side far away from the first chip 5, and the I/O port is sequentially connected with the third redistribution layer 12 and the first redistribution layer 22 through a conductive column at a fourth hole, so that the second chip is electrically led out to the second redistribution layer 11. The low thickness 3D of this embodiment piles up packaging structure's thickness is lower, has effectively shortened the physical connection between the chip, and can effectively solve the deep hole electroplating problem to high aspect ratio, through implanting conducting block 6 in advance, can greatly reduced electroplate the degree of difficulty, improves the product yield.
The low-thickness 3D stacked package structure further comprises a first copper layer 13 and a second copper layer 14, the first copper layer 13 is located on the first plastic package layer 7, the third hole is formed in the first copper layer 13 and the first plastic package layer 7, the second copper layer 14 is located on the second plastic package layer 10, and the fourth hole is formed in the second copper layer 14 and the second plastic package layer 10. By arranging the first copper layer 13, the bonding force between the second redistribution layer 11 and the conductive columns at the third via can be effectively improved, and the conductivity is improved; by providing the third redistribution layer 12, the bonding force between the third redistribution layer 12 and the conductive pillar at the fourth hole site can be effectively improved, and the conductivity can be improved.
The low-thickness 3D stacked package structure further includes a first seed layer 15 and a second seed layer 16, where the first seed layer 15 is located at the third hole and on the surface of the first copper layer 13, and the second seed layer 16 is located at the fourth hole and on the surface of the second copper layer 14. The first seed layer 15 is located on the surfaces of the first copper layer 13 and the third hole, so that the electrical connection stability between the second redistribution layer 11 and the I/O port of the first chip 5 and the conductive column at the third hole can be further improved; the second seed layer 16 is located on the surfaces of the second copper layer 14 and the fourth hole, so that the electrical connection stability between the third redistribution layer 12 and the second chip 8 and the conductive pillars at the fourth hole can be further improved.
The first seed layer 15 and the second seed layer 16 each include a titanium metal layer and a copper metal layer on the titanium metal layer.
Of course, the first seed layer 15 and the second seed layer 16 in this embodiment are not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single-layer structure, a two-layer structure, or a multilayer structure having two or more layers. The materials of the first seed layer 15 and the second seed layer 16 are not limited to two single metal materials, and may also be a single metal material or an alloy material, so that the redistribution layer can be stably attached to the corresponding plastic package layer, and details are not described herein.
Further, the low-thickness 3D stacked package structure further includes a third plastic package layer 17, a fourth plastic package layer 18 and a conductive end 19, the third plastic package layer 17 is located on the first plastic package layer 7 and covers the second redistribution layer 11, the third plastic package layer 17 is provided with a fifth hole for exposing a part of the second redistribution layer 11, the conductive end 19 is located in the fifth hole, and the fourth plastic package layer 18 is located on the second plastic package layer 10 and covers the third redistribution layer 12. And the conductive end 19 connected with the second rewiring layer 11 is arranged at the fifth hole position in an electroplating mode, so that the first chip 5 and the second chip 8 are electrically led out.
Further, the conductive terminal 19 includes a copper layer on the surface of the fifth hole and a tin layer on the copper layer.
It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (6)
1. A low-thickness 3D stacked package structure, comprising:
the circuit comprises a solder mask layer and a first rewiring layer positioned on one side of the solder mask layer, wherein a first hole position and a second hole position penetrating through the solder mask layer along the thickness direction of the solder mask layer are arranged at intervals;
the first plastic package layer is positioned on one side, away from the first rewiring layer, of the solder resist layer, the first chip which is packaged in the first plastic package layer and is pasted at the first hole site through solder paste and provided with a double-sided I/O port, and the conductive block which is pasted at the second hole site through solder paste, and the first plastic package layer is provided with an I/O port on one side, away from the solder resist layer, of the first chip and a third hole site exposed by the conductive block;
the second rewiring layer is positioned on the first plastic packaging layer and is connected with the conductive block through the conductive column in the third hole;
the second plastic package layer is positioned on one side, far away from the first chip, of the first rewiring layer, and the second chip is provided with a single-sided I/O port;
and the third redistribution layer is positioned on the second plastic packaging layer and is connected with the first redistribution layer through the conductive column in the fourth hole.
2. The low-thickness 3D stacked package structure according to claim 1, further comprising a first copper layer and a second copper layer, wherein the first copper layer is located on the first molding compound layer, the third hole is formed in both the first copper layer and the first molding compound layer, the second copper layer is located on the second molding compound layer, and the fourth hole is formed in both the second copper layer and the second molding compound layer.
3. The low thickness 3D stack package structure of claim 2, further comprising a first seed layer and a second seed layer, the first seed layer being located at the third hole site and on a surface of the first copper layer, the second seed layer being located at the fourth hole site and on a surface of the second copper layer.
4. The low-thickness 3D stacked package structure according to claim 2, further comprising a third plastic package layer, a fourth plastic package layer and a conductive terminal, wherein the third plastic package layer is located on the first plastic package layer and covers the second redistribution layer, the third plastic package layer defines a fifth hole for exposing a portion of the second redistribution layer, the conductive terminal is located in the fifth hole, and the fourth plastic package layer is located on the second plastic package layer and covers the third redistribution layer.
5. The low thickness 3D stacked package structure of claim 4, wherein the conductive end comprises a copper layer on the surface of the fifth hole and a tin layer on the copper layer.
6. The low thickness 3D stacked package structure of claim 1, wherein the material of the conductive block is Cu, Ag, or Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020471426.6U CN211428121U (en) | 2020-04-02 | 2020-04-02 | Low-thickness 3D stacking and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020471426.6U CN211428121U (en) | 2020-04-02 | 2020-04-02 | Low-thickness 3D stacking and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211428121U true CN211428121U (en) | 2020-09-04 |
Family
ID=72286300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020471426.6U Active CN211428121U (en) | 2020-04-02 | 2020-04-02 | Low-thickness 3D stacking and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211428121U (en) |
-
2020
- 2020-04-02 CN CN202020471426.6U patent/CN211428121U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104851842B (en) | Semiconductor devices including embedded surface installing device and forming method thereof | |
| TWI508196B (en) | Method of making cavity substrate with built-in stiffener and cavity | |
| CN105826306B (en) | Chip package, package substrate and manufacturing method of package substrate | |
| US8524532B1 (en) | Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein | |
| US20140159212A1 (en) | Stacked type power device module | |
| TW201133666A (en) | Integrated circuit packaging system with conductive pillars and method of manufacture thereof | |
| CN107424973B (en) | Package substrate and method for fabricating the same | |
| US10002825B2 (en) | Method of fabricating package structure with an embedded electronic component | |
| TW201220446A (en) | Package structure of embedded semiconductor component and manufacturing method thereof | |
| TW201631701A (en) | Polymer member based interconnect | |
| US20130244382A1 (en) | High precision self aligning die for embedded die packaging | |
| CN103137613B (en) | The method for preparing active chip package substrate | |
| CN112713097A (en) | Antenna packaging structure and packaging method | |
| CN111341681A (en) | Low-thickness 3D stacked packaging structure and preparation method thereof | |
| CN111261532A (en) | Low RDSON three-dimensional stacking integrated packaging structure and preparation method thereof | |
| CN211428121U (en) | Low-thickness 3D stacking and packaging structure | |
| TWI819506B (en) | Embedded packaging structure and manufacturing method thereof | |
| CN116259546A (en) | Multi-pin lead frame and manufacturing method thereof | |
| CN211150512U (en) | Fan-out type three-dimensional packaging structure | |
| JP3781998B2 (en) | Manufacturing method of stacked semiconductor device | |
| JP3757766B2 (en) | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE | |
| CN111029260A (en) | Preparation method of fan-out type three-dimensional packaging structure and fan-out type three-dimensional packaging structure | |
| CN114203882A (en) | Fan-out type LED packaging structure and packaging method thereof | |
| CN212113625U (en) | Low RDSON three-dimensional stacking integrated packaging structure | |
| CN113270327B (en) | Active and passive device vertical laminated embedded packaging structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A low thickness 3D stack packaging structure Effective date of registration: 20201224 Granted publication date: 20200904 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: Guangdong fozhixin microelectronics technology research Co.,Ltd.|Guangdong Xinhua Microelectronics Technology Co.,Ltd. Registration number: Y2020980009995 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230418 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20200904 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: Guangdong Xinhua Microelectronics Technology Co.,Ltd.|Guangdong fozhixin microelectronics technology research Co.,Ltd. Registration number: Y2020980009995 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |