CN113545801A - Multichannel ultrasonic signal receiving system - Google Patents
Multichannel ultrasonic signal receiving system Download PDFInfo
- Publication number
- CN113545801A CN113545801A CN202110825286.7A CN202110825286A CN113545801A CN 113545801 A CN113545801 A CN 113545801A CN 202110825286 A CN202110825286 A CN 202110825286A CN 113545801 A CN113545801 A CN 113545801A
- Authority
- CN
- China
- Prior art keywords
- programmable gate
- gate array
- field programmable
- ultrasonic
- speed transceivers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/56—Details of data transmission or power supply
Landscapes
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Engineering & Computer Science (AREA)
- Biomedical Technology (AREA)
- Medical Informatics (AREA)
- Pathology (AREA)
- Radiology & Medical Imaging (AREA)
- Biophysics (AREA)
- Physics & Mathematics (AREA)
- Heart & Thoracic Surgery (AREA)
- Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
- Molecular Biology (AREA)
- Surgery (AREA)
- Animal Behavior & Ethology (AREA)
- General Health & Medical Sciences (AREA)
- Public Health (AREA)
- Veterinary Medicine (AREA)
- Computer Networks & Wireless Communication (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
Abstract
The invention discloses a multichannel ultrasonic signal receiving system, which comprises a plurality of ultrasonic receiving chips with 8 channels, a first field programmable gate array and a second field programmable gate array, wherein the ultrasonic receiving chips are connected with the first field programmable gate array and the second field programmable gate array; the total number of the ultrasonic receiving chips is 24 or 32; the first field programmable gate array and the second field programmable gate array are integrated with high-speed transceivers, the number of the high-speed transceivers integrated in the first field programmable gate array is less than or equal to the number of the high-speed transceivers integrated in the second field programmable gate array, and the number of the high-speed transceivers in the first field programmable gate array and the second field programmable gate array is greater than or equal to the number of the ultrasonic receiving chips connected with the first field programmable gate array and the second field programmable gate array respectively. By implementing the invention, 192 or 256 channels of full-channel transceiving can be realized, and the integrity of the ultrasonic signal and the quality of the finally generated image are improved.
Description
Technical Field
The invention relates to the technical field of ultrasonic imaging, in particular to a multi-channel ultrasonic signal receiving system.
Background
At present, most medical ultrasonic systems adopt 64-channel ultrasonic signal receiving systems, and some high-end machines adopt 128-channel ultrasonic signal receiving systems, but the quality of the formed images cannot meet the requirements of doctors. While some ultra-high-end ultrasonic systems can support 256 channels, the ultrasonic signal receiving system with 256 channels is substantially expanded into 256 channels from 128 channels through a relay or a MUX switch, and channel data which can be processed at the same time is up to 128 channels, so that full-channel transceiving of the 256 channels cannot be realized, and the signal integrity is insufficient.
Disclosure of Invention
The embodiment of the invention provides a multi-channel ultrasonic signal receiving system, which can realize the receiving and transmitting of 192 full channels and can improve the quality of ultrasonic imaging and the signal integrity.
The invention provides a multichannel ultrasonic signal receiving system, which comprises a plurality of ultrasonic receiving chips with 8 channels, a first field programmable gate array and a second field programmable gate array, wherein the ultrasonic receiving chips are connected with the first field programmable gate array and the second field programmable gate array; wherein the total number of the ultrasonic receiving chips is 24 or 32;
the first field programmable gate array and the second field programmable gate array are integrated with high-speed transceivers, and the number of the high-speed transceivers integrated in the first field programmable gate array is less than or equal to that of the high-speed transceivers integrated in the second field programmable gate array;
each ultrasonic receiving chip is connected with an external ultrasonic probe;
the first field programmable gate array is connected with a first preset number of ultrasonic receiving chips; wherein the first preset number is less than or equal to the number of high-speed transceivers in the first field programmable gate array;
the second field programmable gate array is connected with a second preset number of ultrasonic receiving chips; wherein the second preset number is less than or equal to the number of high-speed transceivers in the second field programmable gate array;
the sum of the first preset number and the second preset number is the total number of the ultrasonic receiving chips, and the first preset number is smaller than or equal to the second preset number;
the first field programmable gate array is also connected with the second field programmable gate array, and the second field programmable gate array is also connected with an upper computer for imaging;
each ultrasonic receiving chip is used for receiving the ultrasonic signals collected by the ultrasonic probe and transmitting the ultrasonic signals to the corresponding field programmable gate array;
the first field programmable gate array transmits the received ultrasonic signals to the second field programmable gate array;
and the second field programmable gate array transmits all the received ultrasonic signals to the upper computer so as to enable the upper computer to perform imaging.
In this embodiment, 192 ultrasound receiving channels are formed by 24 pieces of 8-channel ultrasound receiving chips, the 24 pieces of ultrasound receiving chips are divided into two groups, each ultrasound receiving chip in one group is connected with the first field programmable gate array, and each ultrasound receiving chip in the other group is connected with the second field programmable gate array; the number of the high-speed transceivers in the first field programmable gate array and the second field programmable gate array is larger than that of the ultrasonic receiving chips connected with the first field programmable gate array and the second field programmable gate array, so that 192-channel full-channel transceiving can be realized.
Or 192 ultrasonic receiving channels are formed by 32 pieces of 8-channel ultrasonic receiving chips, the 32 pieces of ultrasonic receiving chips are divided into two groups, each ultrasonic receiving chip in one group is connected with the first field programmable gate array, and each ultrasonic receiving chip in the other group is connected with the second field programmable gate array; the number of the high-speed transceivers in the first field programmable gate array and the second field programmable gate array is larger than that of the ultrasonic receiving chips connected with the first field programmable gate array and the second field programmable gate array, so that 256-channel full-channel transceiving can be realized.
In addition, the two field programmable gate arrays are adopted for receiving and transmitting the ultrasonic signals, so that the on-chip resources can be efficiently utilized, and the cost is saved. If a field programmable gate array with the full transceiving function of 192 channels or 256 channels is used, more high-speed transceivers need to be integrated in the field programmable gate array, and the price is far higher than the total price of the field programmable gate array with fewer two high-speed transceivers.
Further, the method also comprises the following steps: a clock module; the clock module is respectively connected with the ultrasonic receiving chips, the first field programmable gate array and the second field programmable gate array. In this embodiment, the clock module provides a clock signal to each module, thereby ensuring that each module can operate synchronously.
Further, the first field programmable gate array is further configured to generate a first synchronization signal; the second field programmable gate array is also used for generating a second synchronous signal; and the third synchronous signal generated after the line summation of the first synchronous signal and the second synchronous signal is a synchronous trigger signal of each ultrasonic receiving chip. If the data of each ultrasonic signal receiving chip is not synchronous, the display of the final image is affected, so in this embodiment, the finally output synchronous signal is used as the synchronous trigger signal of each ultrasonic receiving chip by performing the line and logic operation on the synchronous signals of the two field programmable gate arrays, thereby ensuring the data synchronization of each ultrasonic receiving chip.
Further, when the total number of the ultrasonic chips is 24, the first preset number is 4, and the second preset number is 20; when the total number of the ultrasonic chips is 32, the first preset number is 12, and the second preset number is 20. In this embodiment, when the total number of the ultrasound chips is 24, 4 ultrasound receiving chips are connected to the first field programmable gate array, and then 20 ultrasound receiving chips are connected to the second field programmable gate array. When the total number of the ultrasonic chips is 32, 12 ultrasonic receiving chips are connected with a first field programmable gate array, and then 20 ultrasonic receiving chips are connected with a second field programmable gate array.
Further, when the first preset number is 4 and the second preset number is 20, 4 groups of high-speed transceivers are integrated in the first field programmable gate array; the second field programmable gate array is integrated with 28 groups of high-speed transceivers; the 4 groups of high-speed transceivers in the first field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip; 8 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with an upper computer; and the 20 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip. In this embodiment, the first field programmable gate array integrates 4 sets of high-speed transceivers for data transmission with the 4 pieces of ultrasound receiving chips connected with the first field programmable gate array, and the second field programmable gate array integrates 28 sets of high-speed transceivers, wherein 20 sets of the high-speed transceivers are used for data transmission with the 20 pieces of ultrasound receiving chips connected with the high-speed transceivers, and the remaining 8 sets are used for data transmission with the upper computer.
Further, when the first preset number is 12 and the second preset number is 20, 12 groups of high-speed transceivers are integrated in the first field programmable gate array; the second field programmable gate array is integrated with 28 groups of high-speed transceivers; the 12 groups of high-speed transceivers in the first field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip; 8 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with an upper computer; and 20 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip. In this embodiment, the first field programmable gate array integrates 12 sets of high-speed transceivers for data transmission with 12 pieces of ultrasound receiving chips connected with the first field programmable gate array, and the second field programmable gate array integrates 28 sets of high-speed transceivers, wherein 20 sets of the high-speed transceivers are used for data transmission with 20 pieces of ultrasound receiving chips connected with the high-speed transceivers, and the remaining 8 sets are used for data transmission with the upper computer. Furthermore, each ultrasonic receiving chip outputs ultrasonic signals to a high-speed transceiver of a corresponding field programmable gate array in an output configuration of 1 lane. The output configuration of 1lane is adopted, namely 8 integrated channels are serially output through 1lane, so that only 24 lanes are needed for 192 channels, compared with 192 pairs of data lines needed for normal transmission, physical connecting lines are saved by 87%, and only 32 lanes are needed for 256 channels, so that the physical connecting lines are greatly saved.
Further, the first field programmable gate array is connected with the second field programmable gate array through an LVDS interface.
Further, each ultrasonic receiving chip is connected with a corresponding field programmable gate array through a JESD204B interface.
Further, the second field programmable gate array is connected with the upper computer through a PCIE interface.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a multi-channel ultrasonic signal receiving system, which comprises: the ultrasonic receiver comprises a plurality of ultrasonic receiving chips with 8 channels, a first field programmable gate array and a second field programmable gate array; the first field programmable gate array and the second field programmable gate array are integrated with high-speed transceivers, the number of the high-speed transceivers integrated in the first field programmable gate array is less than or equal to the number of the high-speed transceivers integrated in the second field programmable gate array, the number of the high-speed transceivers in the first field programmable gate array and the second field programmable gate array is greater than or equal to the number of the ultrasonic receiving chips connected with the first field programmable gate array and the second field programmable gate array respectively, and the total number of the ultrasonic receiving chips is 24 or 32, so that 192-channel or 256-channel full-channel transceiving can be realized. Compared with the existing 128-channel ultrasonic receiving system, the quality of the ultrasonic image generated by the upper computer is better, and compared with the existing 256-channel ultrasonic receiving system, the ultrasonic receiving system can achieve the transceiving of the whole channel, and improves the integrity of signals. In addition, the two field programmable gate arrays are adopted for receiving and transmitting the ultrasonic signals, so that the on-chip resources can be efficiently utilized, and the cost is saved.
Drawings
Fig. 1 is a schematic structural diagram of a 192-channel ultrasonic signal receiving system according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a 256-channel ultrasonic signal receiving system according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 and 2, an embodiment of the present invention provides a multi-channel ultrasound signal receiving system, including: the ultrasonic receiving chips are provided with 8 channels, and the ultrasonic receiving chips comprise a first field programmable gate array and a second field programmable gate array; wherein the total number of the ultrasonic receiving chips is 24 or 32.
The first field programmable gate array and the second field programmable gate array are integrated with high-speed transceivers, and the number of the high-speed transceivers integrated in the first field programmable gate array is less than or equal to that of the high-speed transceivers integrated in the second field programmable gate array;
each ultrasonic receiving chip is connected with an external ultrasonic probe;
the first field programmable gate array is connected with a first preset number of ultrasonic receiving chips; wherein the first preset number is less than or equal to the number of high-speed transceivers in the first field programmable gate array;
the second field programmable gate array is connected with a second preset number of ultrasonic receiving chips; wherein the second preset number is less than or equal to the number of high-speed transceivers in the second field programmable gate array;
the sum of the first preset number and the second preset number is the total number of the ultrasonic receiving chips, and the first preset number is smaller than or equal to the second preset number;
the first field programmable gate array is also connected with the second field programmable gate array, and the second field programmable gate array is also connected with an upper computer for imaging;
each ultrasonic receiving chip is used for receiving the ultrasonic signals collected by the ultrasonic probe and transmitting the ultrasonic signals to the corresponding field programmable gate array;
the first field programmable gate array transmits the received ultrasonic signals to the second field programmable gate array;
and the second field programmable gate array transmits all the received ultrasonic signals to the upper computer so as to enable the upper computer to perform imaging.
Specifically, in this embodiment, 192 ultrasound receiving channels may be formed by using 24 pieces of 8-channel ultrasound receiving chips, or 256 ultrasound receiving channels may be formed by using 32 pieces of 8-channel ultrasound receiving chips to receive ultrasound signals acquired from an ultrasound probe, and optionally, the ultrasound probe is a probe having 192 array elements, and it is understood that the ultrasound probe may also be a probe having 128 array elements.
If 24 pieces of 8-channel ultrasonic receiving chips are adopted, the 24 pieces of ultrasonic receiving chips are divided into two groups, each ultrasonic receiving chip in one group is connected with a first field programmable gate array, and each ultrasonic receiving chip in the other group is connected with a second field programmable gate array; the number of the high-speed transceivers in the first field programmable gate array and the second field programmable gate array is larger than that of the ultrasonic receiving chips connected with the first field programmable gate array and the second field programmable gate array, so that 192-channel full-channel transceiving can be realized. In addition, the number of high-speed transceivers in the first field programmable gate array is less than or equal to the number of high-speed transceivers in the second field programmable gate array; preferably, 4 groups of high-speed transceivers GTX are integrated in the first field programmable gate array, the first preset number is 4, and the first field programmable gate array receives data transmitted by the 4 ultrasonic signal receiving chips through the 4 groups of high-speed transceivers GTX; 28 groups of high-speed transceivers GTH are integrated in the second field programmable gate array, the second preset number is 20, 8 groups of high-speed transceivers in the second field programmable gate array are used for high-speed transmission of an upper computer and hardware, and the other 20 groups of high-speed transceivers are used for receiving data transmitted by 20 ultrasonic signal receiving chips; each ultrasonic receiving chip is connected with an external probe, ultrasonic signals collected by the probe are subjected to analog-to-digital conversion and then transmitted to a first field programmable gate array and a second field programmable gate array, the first field programmable gate array receives the ultrasonic signals transmitted by the 4 ultrasonic signal receiving chips, the received ultrasonic signals are transmitted to the second field programmable gate array, and the second field programmable gate array is used as a receiving center of all the ultrasonic signals. And after receiving all the ultrasonic signals, the second field programmable gate array uploads all the ultrasonic signals to an upper computer connected with the second field programmable gate array, and the upper computer performs ultrasonic imaging.
If the ultrasonic receiving chips of 32 pieces and 8 channels are adopted, the 32 pieces of ultrasonic receiving chips are divided into two groups, each ultrasonic receiving chip in one group is connected with the first field programmable gate array, and each ultrasonic receiving chip in the other group is connected with the second field programmable gate array; the number of the high-speed transceivers in the first field programmable gate array and the second field programmable gate array is larger than that of the ultrasonic receiving chips connected with the first field programmable gate array and the second field programmable gate array, so that 256-channel full-channel transceiving can be realized. In addition, the number of high-speed transceivers in the first field programmable gate array is less than or equal to the number of high-speed transceivers in the second field programmable gate array; preferably, at this time, 12 groups of high-speed transceivers GTX are integrated in the first field programmable gate array, the first preset number is 12, and the first field programmable gate array receives data transmitted by 12 pieces of ultrasonic signal receiving chips through the 12 groups of high-speed transceivers GTX; 28 groups of high-speed transceivers GTH are integrated in the second field programmable gate array, the second preset number is 20, 8 groups of high-speed transceivers in the second field programmable gate array are used for high-speed transmission of an upper computer and hardware, and the other 20 groups of high-speed transceivers are used for receiving data transmitted by 20 ultrasonic signal receiving chips; each ultrasonic receiving chip is connected with an external probe, ultrasonic signals collected by the probe are subjected to analog-to-digital conversion and then transmitted to a first field programmable gate array and a second field programmable gate array, the first field programmable gate array receives the ultrasonic signals transmitted by the 12 ultrasonic signal receiving chips, the received ultrasonic signals are transmitted to the second field programmable gate array, and the second field programmable gate array is used as a receiving center of all the ultrasonic signals. And after receiving all the ultrasonic signals, the second field programmable gate array uploads all the ultrasonic signals to an upper computer connected with the second field programmable gate array, and the upper computer performs ultrasonic imaging. In a preferred embodiment, each of the ultrasonic receiving chips is AD 9671; each ultrasonic receiving chip is connected with a corresponding field programmable gate array through a JESD204B interface; the first programmable gate array is connected with the second field programmable gate array through an LVDS interface; and the second field programmable gate array is connected with the upper computer through a PCIE interface. The AD9671 is an 8-channel ultrasonic receiving chip, an 8-channel Low Noise Amplifier (LNA), a Variable Gain Amplifier (VGA), an Anti-Aliasing Filter (AAF), a 14-bit ADC, a digital demodulator and a JESD204B interface are integrated in the AD9671, the AD9671 mainly has the functions of A/D conversion, amplification and filtering of signals acquired by an analog front end, and simultaneously supports in-chip demodulation, reduces the transmission data rate of a field programmable gate array, communicates with the field programmable gate array through a JESD204B high-speed interface, supports the maximum rate of 5Gb/s, and supports the configuration of 1lane, 2lane and 4lane to be output to the field programmable gate array transceiver interface. Preferably, in the invention, each of the ultrasound receiving chips is configured with an output of 1lane, and outputs an ultrasound signal to a corresponding high-speed transceiver of the field programmable gate array, that is, 8 integrated channels output serially through 1lane, so that only 24 lanes are needed for 192 channels, which saves 87 physical connection wires compared with 192 pairs of data lines needed for normal transmission.
When the total number of the ultrasonic receiving chips is 24, the model of the first programmable gate array is KCU060-FFVA 1156; the model of the second programmable gate array is XC7K70T-FBG 484.
XC7K70T-FBG484 has 4 sets of high speed transceivers GTX integrated inside it, with the highest supported on-line rate of 10.3 Gb/s. XC7K70T-FBG484 is connected with 4 AD9671 ultrasonic receiving chips, XC7K70T-FBG484 converts serial data of the 4 AD9671 chips in parallel, each chip integrates 8 channels to obtain 32-channel parallel data, each channel data is demodulated I/Q data 32bit, and the data is transmitted to KCU060-FFVA1156 through 32 pairs of LVDS;
the KCU060-FFVA1156 receives ultrasonic signals transmitted by 20 AD9671 ultrasonic receiving chips connected with the KCU on one hand, receives ultrasonic signals transmitted by XC7K70T-FBG484 on the other hand, then carries out induction and arrangement on all the ultrasonic signals of 192 channels, uploads the ultrasonic signals to an upper computer through PCIE, and carries out ultrasonic imaging by the upper computer.
In a preferred embodiment, further comprising: a clock module; the clock module is respectively connected with the ultrasonic receiving chips, the first field programmable gate array and the second field programmable gate array. The first field programmable gate array is also used for generating a first synchronization signal; the second field programmable gate array is also used for generating a second synchronous signal; and the third synchronous signal generated after the line summation of the first synchronous signal and the second synchronous signal is a synchronous trigger signal of each ultrasonic receiving chip. If the data of each ultrasonic signal receiving chip is not synchronous, the display of the final image is affected, therefore, in this embodiment, the clock module provides a clock signal for each module, so as to ensure that each module can operate synchronously, and then the synchronous signals of the two field programmable gate arrays are subjected to line and logic operation, and finally output synchronous signals are used as synchronous trigger signals of each ultrasonic receiving chip, so as to ensure that the data of each ultrasonic receiving chip are synchronous.
Preferably, the clock module is AD9528, the AD9528 is a dual-stage PLL, and the integrated JESD204B SYSREF generator is used for multi-device synchronization. A first stage Phase Locked Loop (PLL) (PLL1) achieves input reference voltage conditioning by reducing jitter in the system clock. The second stage PLL (PLL2) provides a high frequency clock that can achieve lower integration jitter and lower wideband noise from the clock output driver. The external VCXO provides the low noise reference voltage required by the PLL2 to meet the stringent phase noise and jitter requirements for acceptable performance. The tuning frequency range of the on-chip VCO is 3.450GHz to 4.025 GHz. The integrated SYSREF generator outputs a single, N-times, or continuous signal and is synchronized with the PLL1 and PLL2 outputs to time align the multiple devices. AD9528 produces two outputs (output 1 and output 2) with a maximum frequency of 1.25GHz, and 12 outputs up to 1GHz, each of which can be configured to be output directly from PLL1, PLL2, or an internal SYSREF generator. Each of the 14 output channels contains a frequency divider with a digital coarse phase adjustment function and an analog fine phase delay module, allowing a high degree of flexibility in timing alignment of the entire 14 outputs. The AD9528 may also be used as a flexible dual channel input buffer to enable distribution of 14-way device clocks and/or SYSREF signals.
By implementing the embodiment of the invention, 192 or 256 channels of full-channel transceiving can be realized, and compared with the existing 256-channel ultrasonic receiving system, the method and the system can improve the number of channels of an ultrasonic imaging system and ensure the precision and the integrity of signals; the larger the number of receiving channels, the higher the transverse resolution, so that the quality of the finally generated ultrasonic image is better compared with a 128-channel ultrasonic signal receiving system.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A multi-channel ultrasound signal receiving system, comprising: the ultrasonic receiving chips are provided with 8 channels, and the ultrasonic receiving chips comprise a first field programmable gate array and a second field programmable gate array; wherein the total number of the ultrasonic receiving chips is 24 or 32;
the first field programmable gate array and the second field programmable gate array are integrated with high-speed transceivers, and the number of the high-speed transceivers integrated in the first field programmable gate array is less than or equal to that of the high-speed transceivers integrated in the second field programmable gate array;
each ultrasonic receiving chip is connected with an external ultrasonic probe;
the first field programmable gate array is connected with a first preset number of ultrasonic receiving chips; wherein the first preset number is less than or equal to the number of high-speed transceivers in the first field programmable gate array;
the second field programmable gate array is connected with a second preset number of ultrasonic receiving chips; wherein the second preset number is less than or equal to the number of high-speed transceivers in the second field programmable gate array;
the sum of the first preset number and the second preset number is the total number of the ultrasonic receiving chips, and the first preset number is smaller than or equal to the second preset number;
the first field programmable gate array is also connected with the second field programmable gate array, and the second field programmable gate array is also connected with an upper computer for imaging;
each ultrasonic receiving chip is used for receiving the ultrasonic signals collected by the ultrasonic probe and transmitting the ultrasonic signals to the corresponding field programmable gate array;
the first field programmable gate array transmits the received ultrasonic signals to the second field programmable gate array;
and the second field programmable gate array transmits all the received ultrasonic signals to the upper computer so as to enable the upper computer to perform imaging.
2. The ultrasonic signal receiving system of claim 1, further comprising: a clock module; the clock module is respectively connected with the ultrasonic receiving chips, the first field programmable gate array and the second field programmable gate array.
3. The ultrasonic signal receiving system of claim 2, wherein the first field programmable gate array is further configured to generate a first synchronization signal; the second field programmable gate array is also used for generating a second synchronous signal; and the third synchronous signal generated after the line summation of the first synchronous signal and the second synchronous signal is a synchronous trigger signal of each ultrasonic receiving chip.
4. The ultrasonic signal receiving system according to claim 3, wherein when the total number of the ultrasonic chips is 24, the first preset number is 4, and the second preset number is 20;
when the total number of the ultrasonic chips is 32, the first preset number is 12, and the second preset number is 20.
5. The ultrasonic signal receiving system according to claim 4, wherein when the first predetermined number is 4 and the second predetermined number is 20, 4 sets of high-speed transceivers are integrated in the first field programmable gate array; the second field programmable gate array is integrated with 28 groups of high-speed transceivers; 4 groups of high-speed transceivers in the first field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip; 8 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with an upper computer; and 20 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip.
6. The ultrasonic signal receiving system of claim 4, wherein when the first predetermined number is 12 and the second predetermined number is 20, 12 sets of high-speed transceivers are integrated in the first field programmable gate array; the second field programmable gate array is integrated with 28 groups of high-speed transceivers; the 12 groups of high-speed transceivers in the first field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip; 8 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with an upper computer; and 20 groups of high-speed transceivers in the second field programmable gate array are used for carrying out signal transmission with the corresponding ultrasonic receiving chip.
7. The ultrasonic signal receiving system according to claim 5 or 6, wherein each of the ultrasonic receiving chips outputs an ultrasonic signal to a high-speed transceiver of a corresponding field programmable gate array in an output configuration of 1 lane.
8. The ultrasonic signal receiving system of claim 7, wherein the first programmable gate array is connected to the second field programmable gate array through an LVDS interface.
9. The ultrasonic signal receiving system according to claim 8, wherein each of the ultrasonic receiving chips is interfaced with a corresponding field programmable gate array through JESD 204B.
10. The ultrasonic signal receiving system of claim 9, wherein the second field programmable gate array is connected to the upper computer through a PCIE interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825286.7A CN113545801A (en) | 2021-07-21 | 2021-07-21 | Multichannel ultrasonic signal receiving system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825286.7A CN113545801A (en) | 2021-07-21 | 2021-07-21 | Multichannel ultrasonic signal receiving system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113545801A true CN113545801A (en) | 2021-10-26 |
Family
ID=78103856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110825286.7A Pending CN113545801A (en) | 2021-07-21 | 2021-07-21 | Multichannel ultrasonic signal receiving system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113545801A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102640012A (en) * | 2009-09-30 | 2012-08-15 | 垓技术公司 | Ultrasound 3D imaging system |
| CN104306024A (en) * | 2014-10-28 | 2015-01-28 | 青岛海信医疗设备股份有限公司 | Ultrasonic device |
| US20210045718A1 (en) * | 2019-08-13 | 2021-02-18 | Thomas C. Moore | Multiple sensor catheter assembly |
-
2021
- 2021-07-21 CN CN202110825286.7A patent/CN113545801A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102640012A (en) * | 2009-09-30 | 2012-08-15 | 垓技术公司 | Ultrasound 3D imaging system |
| CN104306024A (en) * | 2014-10-28 | 2015-01-28 | 青岛海信医疗设备股份有限公司 | Ultrasonic device |
| US20210045718A1 (en) * | 2019-08-13 | 2021-02-18 | Thomas C. Moore | Multiple sensor catheter assembly |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113467696B (en) | Multichannel AD data synchronous transmission system | |
| CN1747376B (en) | Synchronization device and semiconductor device | |
| CN109683137B (en) | Multi-channel synchronization method applied to phased array radar | |
| CN111736517A (en) | Synchronous acquisition and processing card system based on multichannel ADC and FPGA | |
| CN109889211A (en) | A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit | |
| CN114039600B (en) | Multichannel high-speed AD synchronous acquisition device and method | |
| CN105573949A (en) | Acquiring and processing circuit with JESD204B interface of VPX architecture | |
| CN104980156A (en) | Field programmable gate array (FPGA) based high-speed analog-digital converter (ADC) synchronous acquisition system | |
| CN111555764A (en) | Radio frequency direct-sampling broadband digital receiver system, method and radio observation system | |
| CN110032262B (en) | High-speed digital transceiver system power-on configuration method based on JESD204B interface | |
| EP2258108A1 (en) | High-speed video serializer and deserializer | |
| US20100248644A1 (en) | Wireless device | |
| EP1813029A1 (en) | Timing system and method for a wireless transceiver system | |
| CN111193891A (en) | FPGA-based Camera Link data receiving system and transmission method | |
| CN114090497A (en) | Synchronization scheme of high-speed data acquisition clock | |
| JP2001007880A (en) | Orthogonal channelizer in digital demodulator | |
| CN101321051A (en) | Clock synchronization apparatus and method for radio frequency remote unit | |
| CN114124278B (en) | Digital synchronization circuit and method for digital simultaneous multi-beam transmission | |
| CN113545801A (en) | Multichannel ultrasonic signal receiving system | |
| CN210626562U (en) | System for improving effective sampling bandwidth under condition of not improving sampling rate | |
| JP5560867B2 (en) | Data receiving circuit | |
| CN215990748U (en) | System clock device and acquisition equipment of 5G full-band radio frequency signals | |
| CN112118063A (en) | Clock synchronization device, optical transmitter, optical receiver and method | |
| CN114070444B (en) | Synchronization system and method based on digital array receiving channel | |
| CN116208173A (en) | Parallelization decoding device and method under high-speed serial interface clock-free line application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20221019 Address after: 100000303-24, Floor 3, Building 4, Yard 9, Yike Road, Life Science Park, Changping District, Beijing (cluster registration) Applicant after: Yichao Medical Technology (Beijing) Co.,Ltd. Address before: Zero second space, Block E, building B36, Hengtong business park, No. 10 Jiuxianqiao, Chaoyang District, Beijing 100020 Applicant before: Yichao Technology (Beijing) Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230423 Address after: 430000 West facing 701-715, Building B1, 7th Floor, Phase II, Block B, Wuhan High tech Medical Equipment Park, No. 818 Gaoxin Avenue, Donghu New Technology Development Zone, Wuhan, Hubei Province (Wuhan area of the Free Trade Zone) Applicant after: Yichao Technology (Wuhan) Co.,Ltd. Address before: 100000303-24, Floor 3, Building 4, Yard 9, Yike Road, Life Science Park, Changping District, Beijing (cluster registration) Applicant before: Yichao Medical Technology (Beijing) Co.,Ltd. |