CN113540225B - 一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管及其制备方法 - Google Patents
一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管及其制备方法 Download PDFInfo
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- 230000005641 tunneling Effects 0.000 title claims abstract description 105
- 230000005669 field effect Effects 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 178
- 230000005764 inhibitory process Effects 0.000 claims abstract description 36
- 230000001629 suppression Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 230000002401 inhibitory effect Effects 0.000 abstract description 12
- 230000002829 reductive effect Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 108091006146 Channels Proteins 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 239000010408 film Substances 0.000 description 8
- 230000001965 increasing effect Effects 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 229910001868 water Inorganic materials 0.000 description 7
- 238000001816 cooling Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000002243 precursor Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 230000009467 reduction Effects 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000011010 flushing procedure Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 239000013077 target material Substances 0.000 description 3
- 229910021642 ultra pure water Inorganic materials 0.000 description 3
- 239000012498 ultrapure water Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 102000003691 T-Type Calcium Channels Human genes 0.000 description 1
- 108090000030 T-Type Calcium Channels Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009046 primary transport Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
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Abstract
本发明公开了一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管及其制备方法,该晶体管包括P+GaAsSb源区、i‑InGaAs第一抑制层、i‑InGaAs第二抑制层、n+InGaAs第一漏区、n+InGaAs第二漏区、i‑InGaAs隧穿层、栅极介质层和凹型栅极;P+GaAsSb源区远离i‑InGaAs隧穿层的一侧设置有源极,n+InGaAs第一漏区设置有第一漏极,n+InGaAs第二漏区上设置有第二漏极。本发明通过引入凹型栅结构、隧穿层、抑制层、高k栅极介质以及GaAsSb/InGaAs异质结,提高了晶体管开态电流,降低了晶体管亚阈值摆幅与工作电压,可用于超低功耗集成电路器件。
Description
技术领域
本发明属于微电子器件技术领域,具体涉及到一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管及其制备方法。
背景技术
在集成电路领域,随着器件特征尺寸的减小,集成度的提高,器件亚阈值电压的降低与静态功耗的提升成为难以调和的矛盾。同时,量子隧穿效应导致的栅极漏电和沟道漏电,沟道变短而加剧的热载流子效应、负偏压温度不稳定性、漏致势垒降低以及沟道载流子分布量子涨落等,严重影响器件性能。传统金属氧化物半导体场效应晶体管(MOSFET)导通是建立在电子热激发输运机制之上,亚阈值摆幅(SS)难以突破60mv/dec的物理限制。随着器件尺寸的减小与电源电压的降低,为了保证有足够的输出电流,迫使传统MOSFET阈值电压不断降低,而过低的阈值电压将导致器件的关态泄漏电流激增,静态功耗急剧增加。为了提高开态电流同时抑制关态漏电,需要突破亚阈值摆幅60mv/dec的物理限制。不同于传统MOSFET,隧穿场效应晶体管(TFET)的主要输运机制基于带间隧穿(BTBT)的物理机制,从而能够在室温下获得低于60mV/dec的亚阈值摆幅。这使得TFET能够在更低的开启电压下,获得更高的开态电流,且不易受到短沟道效应所带来的负面影响。
然而,当前对TFET的研究表明,大多数的TFET开态电流只能达到微安甚至亚微安量级,为提高隧穿场效应晶体管的开态电流,人们提出多种改进的器件结构与材料,如L型沟道隧穿场效应晶体管(LTFET),U型沟道隧穿场效应晶体管(UTFET),T型沟道隧穿场效应晶体管(TGTFET),异质结隧穿场效应晶体管(HTFET)等。隧穿场效应晶体管的开态电流主要依赖于垂直于沟道的电子带带隧穿效率,在上述器件结构中,TGTFET由于采用了增加有效隧穿结面积的线型隧穿结结构、提高隧穿率的辅助隧穿势垒区、增强电场的顶部栅极覆盖以及进一步增加有效隧穿结面积的双源极设计,从而获得了较为良好的性能。但是受限于硅材料本身性质以及仍有改进空间的器件结构,其开态电流距离实际应用的最低标准百微安量级仍有一定的差距。
发明内容
本发明的目的是提供一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管及其制备方法,可以进一步降低亚阈值摆幅SS、工作电压和关态电流,大幅度提高隧穿效率和开态电流,进而提高器件的开关性能。
为达上述目的,本发明提供了一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管,包括P+GaAsSb源区、i-InGaAs第一抑制层、i-InGaAs第二抑制层、n+InGaAs第一漏区、n+InGaAs第二漏区、i-InGaAs隧穿层、栅极介质层和凹型栅极;
凹型栅极的外侧依次设置有凹型的栅极介质层和凹型的i-InGaAs隧穿层,i-InGaAs隧穿层的凹口侧两边分别设置有n+InGaAs第一漏区和n+InGaAs第二漏区,i-InGaAs隧穿层的外侧设置有i-InGaAs第一抑制层和i-InGaAs第二抑制层,i-InGaAs第一抑制层与n+InGaAs第一漏区连接,i-InGaAs第二抑制层和n+InGaAs第二漏区连接,n+InGaAs第一漏区、n+InGaAs第二漏区、i-InGaAs隧穿层、栅极介质层和凹型栅极的一端面齐平,i-InGaAs隧穿层的非凹口侧嵌入P+GaAsSb源区,i-InGaAs第一抑制层和i-InGaAs第二抑制层均与P+GaAsSb源区连接;
P+GaAsSb源区远离i-InGaAs隧穿层的一侧设置有源极,n+InGaAs第一漏区设置有第一漏极,n+InGaAs第二漏区上设置有第二漏极。
采用上述方案的有益效果是:通过引入InGaAs/GaAsSb的准断带异质结、引入i-InGaAs辅助隧穿势垒层(隧穿层)、凹型栅极结构、高k栅极介质(栅极介质层)以及i-InGaAs关态隧穿抑制层(抑制层),从而改善隧穿率、增大有效隧穿面积、增强栅极控制能力并有效抑制关态隧穿结开启,最终实现提高TFET的开态电流、降低SS、降低工作电压以及抑制关态漏电;其中i-InGaAs隧穿层与p+GaAsSb源区能够形成准断带的线隧穿结,准断带的能带结构能够有效增大隧穿效率,且不同于传统的点隧穿,线隧穿具有隧穿率高且均匀的优势,而i型的InGaAs隧穿层还能够最大程度的避免小尺寸工艺掺杂波动对器件所带来的影响;凹型栅极结构能够进一步大幅度增加线隧穿结的有效隧穿结面积;i-InGaAs抑制层能够有效降低关态漏电,同时在开态条件下,i-InGaAs抑制层与p+GaAsSb源区界面能够形成线隧穿结,且靠近栅极一侧能够形成点隧穿结,进一步增大开态电流;高k栅极介质能够有效增加栅控能力,提高隧穿结对栅极电压的敏感度。
进一步地,P+GaAsSb源区上方包裹有i-InGaAs隧穿层,包裹的高度为36-44nm。
进一步地,P+GaAsSb源区为p型掺杂,掺杂厚度为1019/cm3。
进一步地,i-InGaAs第一抑制层与i-InGaAs第二抑制层的厚度均为38-42nm。
进一步地,n+InGaAs第一漏区和n+InGaAs第二漏区的厚度均为18-22nm,n+InGaAs第一漏区和n+InGaAs第二漏区的均为n型掺杂,掺杂浓度为5×1018/cm3。
进一步地,i-InGaAs隧穿层的厚度为4-6nm。
进一步地,栅极介质层的材质为HfO2、TiO2和Al2O3中的一种或多种,栅极介质层的厚度为1.8-2.2nm。
一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管的制备方法,包括以下步骤:
(1)利用气相外延工艺在p型掺杂的:P+GaAsSb源区衬底上生长一层i-InGaAs第一抑制层和i-InGaAs第二抑制层;
(2)利用气相外延工艺分别在i-InGaAs第一抑制层和i-InGaAs第二抑制层上生长一层n+InGaAs第一漏区和n+InGaAs第二漏区;
(3)光刻凹槽区域,并利用反应离子刻蚀工艺刻蚀一个凹型深槽;
(4)利用气相外延工艺生长一层i-InGaAs隧穿层;
(5)利用原子层淀积工艺生长一层栅极介质层;
(6)利用磁控溅射工艺制作凹型栅极,分别光刻并制作第一漏极、第二漏极以及源极。
进一步地,步骤(1)的生长参数包括:压强760mT、温度550℃和生长速率0.9mL/s;步骤(2)的生长参数包括:压强760mT、温度550℃、生长速率0.9mL/s以及以Te作为掺杂源;步骤(3)的刻蚀参数包括:压强10mT和功率20W;步骤(4)的生长参数包括:压强760mT、温度500℃和生长速率0.6mL/s;步骤(5)的生长参数包括:反应腔温度250℃、TDEAH气压3×10- 4Pa和H2O气压0.2Pa;步骤(6)的磁控溅射参数包括:反应腔气压0.3Pa、氩气流量20sccm、电流0.1A以及电压100V。
进一步地,步骤(3)中凹型深槽的宽度为76-84nm,深度为96-104nm。
综上所述,本发明具有以下优点:
1、源区采用P+GaAsSb,隧穿层采用i-InGaAs,从而形成准断带的GaAsSb/InGaAs异质型隧穿结,提高了隧穿效率;
2、P+GaAsSb源区部分包裹i-InGaAs隧穿层、栅极介质层以及凹型栅极,形成了具有均匀稳定的高隧穿率线隧穿结,且凹型结构大幅度增加了有效线隧穿结面积;
3、在源区左右两侧的上方加入了i-InGaAs抑制层,能够在器件关态时形成缓变结,从而有效抑制漏致势垒降低效应带来的关态泄漏电流,且开态时在交界处形成准断带的GaAsSb/InGaAs异质型线隧穿结进一步增加器件开态的有效隧穿结面积;
4、i-InGaAs第一抑制层与i-InGaAs第二抑制层位于中央凹型栅极结构左右两侧,且下方与源区的界面为准断带的GaAsSb/InGaAs异质隧穿结,其效果在于,两个抑制层分别为源区的界面,在靠近凹型栅极的位置,能够产生具有较高隧穿率的点隧穿结。
5、本发明优化的器件结构在提高性能的同时,使得器件制备过程更加简单,降低了器件加工的工艺难度。
附图说明
图1为基于准断带异质结的高性能凹栅型隧穿场效应晶体管的结构示意图;
其中,1、P+GaAsSb源区;2、i-InGaAs第一抑制层;3、i-InGaAs第二抑制层;4、n+InGaAs第一漏区;5、n+InGaAs第二漏区;6、i-InGaAs隧穿层;7、栅极介质层;8、凹型栅极;
图2为基于准断带异质结的高性能凹栅型隧穿场效应晶体管的制备流程图;
图3为现有TGTFET与实施例1制备得到的基于准断带异质结的高性能凹栅型隧穿场效应晶体管的转移特性曲线对比图。
具体实施方式
以下结合实施例对本发明的原理和特征进行描述,所举实例只用于解释本发明,并非用于限定本发明的范围。实施例中未注明具体条件者,按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者,均为可以通过市售购买获得的常规产品。
如图1所示,本发明提供了一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管,包括P+GaAsSb源区1、i-InGaAs第一抑制层2、i-InGaAs第二抑制层3、n+InGaAs第一漏区4、n+InGaAs第二漏区5、i-InGaAs隧穿层6、栅极介质层7和凹型栅极8;
凹型栅极8的外侧依次设置有凹型的栅极介质层7和凹型的i-InGaAs隧穿层6,i-InGaAs隧穿层6的凹口侧两边分别设置有n+InGaAs第一漏区4和n+InGaAs第二漏区5,i-InGaAs隧穿层6的外侧设置有i-InGaAs第一抑制层2和i-InGaAs第二抑制层3,i-InGaAs第一抑制层2与n+InGaAs第一漏区4连接,i-InGaAs第二抑制层3和n+InGaAs第二漏区5连接,n+InGaAs第一漏区4、n+InGaAs第二漏区5、i-InGaAs隧穿层6、栅极介质层7和凹型栅极8的一端面齐平,i-InGaAs隧穿层6的非凹口侧嵌入P+GaAsSb源区1,i-InGaAs第一抑制层2和i-InGaAs第二抑制层3均与P+GaAsSb源区1连接;
P+GaAsSb源区1远离i-InGaAs隧穿层6的一侧设置有源极,n+InGaAs第一漏区4设置有第一漏极,n+InGaAs第二漏区5上设置有第二漏极。
其中,P+GaAsSb源区1部分包裹i-InGaAs隧穿层6,包裹的部分的高度为36-44nm;
其中,P+GaAsSb源区1为p型掺杂,掺杂厚度为1019/cm3;
其中,i-InGaAs第一抑制层2与i-InGaAs第二抑制层3的厚度均为38-42nm,且不做掺杂;
其中,n+InGaAs第一漏区4和n+InGaAs第二漏区5的厚度均为18-22nm,n+InGaAs第一漏区4和n+InGaAs第二漏区5均为n型掺杂,掺杂浓度为5×1018/cm3;
其中,i-InGaAs隧穿层6的厚度为4-6nm,不做掺杂;
其中,栅极介质层7采用HfO2、TiO2或Al2O3等高k介质材料或多种混合的叠层介质材料,厚度为1.8-2.2nm。
下面结合实施例对本发明进行详细说明。
实施例1
如图2所示,本实施例提供了一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管的制备方法,包括以下步骤:
S1在P+GaAsSb源区1上方生长抑制层
S1.1将P+GaAsSb源区1衬底放入气态源分子束外延薄膜生长设备,打开气瓶,向设备中通入保护气体He气,设置反应生长炉内的压强为760mT;
S1.2将反应生长炉温度升温到550℃,之后,保持550℃生长温度;
S1.3 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、生长速率为0.9mL/s条件下,生长厚度为40nm的本征InGaAs材料作为抑制层,分别得到i-InGaAs第一抑制层2和i-InGaAs第二抑制层3,生长厚度均为40nm;
S2在抑制层上生长漏区
S2.1 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、Te作为掺杂源,生长速率为0.9mL/s条件下,生长厚度为20nm,掺杂浓度为5×1018/cm3的n型InGaAs材料作为漏区,分别得到n+InGaAs第一漏区4和n+InGaAs第二漏区5;
S2.2生长完抑制层与漏区后,在反应生长炉中致密降温1h;
S3刻蚀凹型深槽
S3.1在生长了n型InGaAs的衬底上表面涂100nm厚度的光刻胶并显影,之后在超纯水液面下冲洗90s,并在N2氛围中冲干;
S3.2将经过光刻显影处理后的衬底送入等离子刻蚀机,手动设置刻蚀腔体的压强为10mT,功率为20W,并通过供气系统向刻蚀腔体输入50sccm的Cl2和20sccm的O2,进行反应离子刻蚀,刻蚀后形成一个宽度80nm,深度100nm的凹型深槽;
S3.3刻蚀完之后使用剥离液对器件进行有机清洗,去除残留的光刻胶;
S4生长i-InGaAs隧穿层6
S4.1将刻蚀深槽后的衬底放入气态源分子束外延薄膜生长设备,打开气瓶,向设备中通入保护气体He气,设置反应生长炉内的压强为760mT;
S4.2将反应生长炉温度升温到500℃并保温;
S4.3 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、生长速率为0.6mL/s条件下,生长厚度为5nm的本征InGaAs材料作为i-InGaAs隧穿层6;
S4.4生长完成后,在反应生长炉中致密降温1h;
S5生长一层HfO2薄膜
将完成刻蚀沟道后的衬底移入原子层淀积系统中,使用四二乙基氨基铪和水作为前驱体,使用纯氮气作为载体,将两种前驱体导入反应腔,同时通过氮气导出氧化物,设置反应腔温度250℃、TDEAH气压为3×10-4Pa、H2O气压为0.2Pa,在沟道上面生长一层厚度为2nm的HfO2薄膜,得到栅极介质层7;
S6制作凹型栅极8
将直径10mm,厚度3mm的高纯度无氧铜靶材放入靶室,反应腔气压0.3Pa,氩气流量20sccm,电流0.1A,电压100V,时间50s,在HfO2薄膜上方凹型中制作栅电极,包括第一漏极、第二漏极以及源极。
试验例
在漏极电压为0.5V的条件下,对实施例1制备得到的基于准断带异质结的高性能凹栅型隧穿场效应晶体管和现有的凹栅型器件TGTFET的转移特性进行仿真,结果如图3。
由图3可知,当栅极电压为0.5V时,本发明制备得到的基于准断带异质结的高性能凹栅型隧穿场效应晶体管的开态电流比现有的凹栅型器件TGTFET在相同电压条件下电流增大近3个数量级,达到了350μA,关态漏电减小近3个数量级,亚阈值摆幅明显更加陡峭,这是由于本发明晶体管引入凹型栅结构、隧穿层、抑制层、高k栅极介质以及GaAsSb/InGaAs异质结的结果。说明本发明更适用于目前超低功耗集成电路器件的需求。
实施例2
本实施例提供了一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管的制备方法,包括以下步骤:
S1在P+GaAsSb源区1上方生长抑制层
S1.1将P+GaAsSb源区1衬底放入气态源分子束外延薄膜生长设备,打开气瓶,向设备中通入保护气体He气,设置反应生长炉内的压强为760mT;
S1.2将反应生长炉温度升温到550℃,之后,保持550℃生长温度;
S1.3 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、生长速率为0.9mL/s条件下,生长厚度为40nm的本征InGaAs材料作为抑制层,分别得到i-InGaAs第一抑制层2和i-InGaAs第二抑制层3,生长厚度分别为42nm;
S2在抑制层上生长漏区
S2.1 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、Te作为掺杂源,生长速率为0.9mL/s条件下,生长厚度为22nm,掺杂浓度为5×1018/cm3的n型InGaAs材料作为漏区,分别得到n+InGaAs第一漏区4和n+InGaAs第二漏区5;
S2.2生长完抑制层与漏区后,在反应生长炉中致密降温1h;
S3刻蚀凹型深槽
S3.1在生长了n型InGaAs的衬底上表面涂100nm厚度的光刻胶并显影,之后在超纯水液面下冲洗90s,并在N2氛围中冲干;
S3.2将经过光刻显影处理后的衬底送入等离子刻蚀机,手动设置刻蚀腔体的压强为10mT,功率为20W,并通过供气系统向刻蚀腔体输入50sccm的Cl2和20sccm的O2,进行反应离子刻蚀,刻蚀后形成一个宽度84nm,深度104nm的凹型深槽;
S3.3刻蚀完之后使用剥离液对器件进行有机清洗,去除残留的光刻胶;
S4生长i-InGaAs隧穿层6
S4.1将刻蚀深槽后的衬底放入气态源分子束外延薄膜生长设备,打开气瓶,向设备中通入保护气体He气,设置反应生长炉内的压强为760mT;
S4.2将反应生长炉温度升温到500℃并保温;
S4.3 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、生长速率为0.6mL/s条件下,生长厚度为6nm的本征InGaAs材料作为i-InGaAs隧穿层(6);
S4.4生长完成后,在反应生长炉中致密降温1h;
S5生长一层HfO2薄膜
将完成刻蚀沟道后的衬底移入原子层淀积系统中,使用四二乙基氨基铪和水作为前驱体,使用纯氮气作为载体,将两种前驱体导入反应腔,同时通过氮气导出氧化物,设置反应腔温度250℃、TDEAH气压为3×10-4Pa、H2O气压为0.2Pa,在沟道上面生长一层厚度为2.2nm的HfO2薄膜,得到栅极介质层7;
S6制作凹型栅极8
将直径10mm,厚度3mm的高纯度无氧铜靶材放入靶室,反应腔气压0.3Pa,氩气流量20sccm,电流0.1A,电压100V,时间50s,在HfO2薄膜上方凹型中制作栅电极,包括第一漏极、第二漏极以及源极。
实施例3
本实施例提供了一种基于准断带异质结的高性能凹栅型隧穿场效应晶体管的制备方法,包括以下步骤:
S1在P+GaAsSb源区1上方生长抑制层
S1.1将P+GaAsSb源区1衬底放入气态源分子束外延薄膜生长设备,打开气瓶,向设备中通入保护气体He气,设置反应生长炉内的压强为760mT;
S1.2将反应生长炉温度升温到550℃,之后,保持550℃生长温度;
S1.3 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、生长速率为0.9mL/s条件下,生长厚度为40nm的本征InGaAs材料作为抑制层,分别得到i-InGaAs第一抑制层2和i-InGaAs第二抑制层3,生长厚度均为38nm;
S2在抑制层上生长漏区
S2.1 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、Te作为掺杂源,生长速率为0.9mL/s条件下,生长厚度为18nm,掺杂浓度为5×1018/cm3的n型InGaAs材料作为漏区,分别得到n+InGaAs第一漏区4和n+InGaAs第二漏区5;
S2.2生长完抑制层与漏区后,在反应生长炉中致密降温1h;
S3刻蚀凹型深槽
S3.1在生长了n型InGaAs的衬底上表面涂100nm厚度的光刻胶并显影,之后在超纯水液面下冲洗90s,并在N2氛围中冲干;
S3.2将经过光刻显影处理后的衬底送入等离子刻蚀机,手动设置刻蚀腔体的压强为10mT,功率为20W,并通过供气系统向刻蚀腔体输入50sccm的Cl2和20sccm的O2,进行反应离子刻蚀,刻蚀后形成一个宽度78nm,深度99nm的凹型深槽;
S3.3刻蚀完之后使用剥离液对器件进行有机清洗,去除残留的光刻胶;
S4生长i-InGaAs隧穿层6
S4.1将刻蚀深槽后的衬底放入气态源分子束外延薄膜生长设备,打开气瓶,向设备中通入保护气体He气,设置反应生长炉内的压强为760mT;
S4.2将反应生长炉温度升温到500℃并保温;
S4.3 In源温度在830℃、Ga源温度在980℃、As源温度在270℃、生长速率为0.6mL/s条件下,生长厚度为4.5nm的本征InGaAs材料作为i-InGaAs隧穿层6;
S4.4生长完成后,在反应生长炉中致密降温1h;
S5生长一层HfO2薄膜
将完成刻蚀沟道后的衬底移入原子层淀积系统中,使用四二乙基氨基铪和水作为前驱体,使用纯氮气作为载体,将两种前驱体导入反应腔,同时通过氮气导出氧化物,设置反应腔温度250℃、TDEAH气压为3×10-4Pa、H2O气压为0.2Pa,在沟道上面生长一层厚度为1.8nm的HfO2薄膜,得到栅极介质层7;
S6制作凹型栅极8
将直径10mm,厚度3mm的高纯度无氧铜靶材放入靶室,反应腔气压0.3Pa,氩气流量20sccm,电流0.1A,电压100V,时间50s,在HfO2薄膜上方凹型中制作栅电极,包括第一漏极、第二漏极以及源极。
虽然结合附图对本发明的具体实施方式进行了详细地描述,但不应理解为对本专利的保护范围的限定。在权利要求书所描述的范围内,本领域技术人员不经创造性劳动即可作出的各种修改和变形仍属本专利的保护范围。
Claims (9)
1.一种基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,包括P+GaAsSb源区(1)、i-InGaAs第一抑制层(2)、i-InGaAs第二抑制层(3)、n+InGaAs第一漏区(4)、n+InGaAs第二漏区(5)、i-InGaAs隧穿层(6)、栅极介质层(7)和凹型栅极(8);
所述凹型栅极(8)的外侧依次设置有凹型的栅极介质层(7)和凹型的i-InGaAs隧穿层(6),所述i-InGaAs隧穿层(6)的凹口侧两边分别设置有n+InGaAs第一漏区(4)和n+InGaAs第二漏区(5),所述i-InGaAs隧穿层(6)的外侧设置有i-InGaAs第一抑制层(2)和i-InGaAs第二抑制层(3),所述i-InGaAs第一抑制层(2)与n+InGaAs第一漏区(4)连接,所述i-InGaAs第二抑制层(3)和n+InGaAs第二漏区(5)连接,所述n+InGaAs第一漏区(4)、n+InGaAs第二漏区(5)、i-InGaAs隧穿层(6)、栅极介质层(7)和凹型栅极(8)的一端面齐平,所述i-InGaAs隧穿层(6)的非凹口侧嵌入P+GaAsSb源区(1),所述i-InGaAs第一抑制层(2)和i-InGaAs第二抑制层(3)均与P+GaAsSb源区(1)连接;
所述P+GaAsSb源区(1)远离i-InGaAs隧穿层(6)的一侧设置有源极,所述n+InGaAs第一漏区(4)设置有第一漏极,所述n+InGaAs第二漏区(5)上设置有第二漏极。
2.如权利要求1所述的基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,所述P+GaAsSb源区(1)上方包裹有i-InGaAs隧穿层(6),包裹的高度为36-44nm。
3.如权利要求1所述的基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,所述P+GaAsSb源区(1)为p型掺杂,掺杂厚度为1019/cm3。
4.如权利要求1所述的基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,所述i-InGaAs第一抑制层(2)与i-InGaAs第二抑制层(3)的厚度均为38-42nm。
5.如权利要求1所述的基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,所述n+InGaAs第一漏区(4)和n+InGaAs第二漏区(5)的厚度均为18-22nm,所述n+InGaAs第一漏区(4)和n+InGaAs第二漏区(5)均为n型掺杂,掺杂浓度为5×1018/cm3。
6.如权利要求1所述的基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,所述i-InGaAs隧穿层(6)的厚度为4-6nm。
7.如权利要求1所述的基于准断带异质结的凹栅型隧穿场效应晶体管,其特征在于,所述栅极介质层(7)的材质为HfO2、TiO2和Al2O3中的一种或多种,所述栅极介质层(7)的厚度为1.8-2.2nm。
8.权利要求1-7任一项所述的基于准断带异质结的凹栅型隧穿场效应晶体管的制备方法,其特征在于,包括以下步骤:
(1)利用气相外延工艺在p型掺杂的P+GaAsSb源区(1)衬底上生长一层i-InGaAs第一抑制层(2)和i-InGaAs第二抑制层(3);
(2)利用气相外延工艺分别在i-InGaAs第一抑制层(2)和i-InGaAs第二抑制层(3)上生长一层n+InGaAs第一漏区(4)和n+InGaAs第二漏区(5);
(3)光刻凹槽区域,并利用反应离子刻蚀工艺刻蚀一个凹型深槽;
(4)利用气相外延工艺生长一层i-InGaAs隧穿层(6);
(5)利用原子层淀积工艺生长一层栅极介质层(7);
(6)利用磁控溅射工艺制作凹型栅极(8),分别光刻并制作第一漏极、第二漏极以及源极。
9.如权利要求8所述的基于准断带异质结的凹栅型隧穿场效应晶体管的制备方法,其特征在于,步骤(3)中凹型深槽的宽度为76-84nm,深度为96-104nm。
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