CN113536715B - Method for analyzing signal line data of industrial graphic computer-aided manufacturing - Google Patents
Method for analyzing signal line data of industrial graphic computer-aided manufacturing Download PDFInfo
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- CN113536715B CN113536715B CN202110772323.2A CN202110772323A CN113536715B CN 113536715 B CN113536715 B CN 113536715B CN 202110772323 A CN202110772323 A CN 202110772323A CN 113536715 B CN113536715 B CN 113536715B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
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Abstract
The invention discloses a method for analyzing signal line data of industrial graphic computer-aided manufacturing, which comprises the following steps of: step one, importing and confirming data of a signal circuit manufacturing yield related layer into a computer; step two, analyzing the signal layer objects, and listing the Size and the number of (1) Size objects in a table; screening out an SMD Pad and a Pad, and listing out (2) risks related to the SMD Pad and the Pad after interactive analysis; comparing and analyzing the (1) and the molding layer, and listing (3) Rout related risks to molding in a table; step five, tabulating (4) the thickness change risk of the Bottleneeck line; step six, listing (5) Spacing and interval related risks, (6) Sliver clearance or filament risks and (7) Connection object Connection risks; step seven, comparing and analyzing the (1) and the pore layer, and listing (8) the risk associated with the Drill and the pore. By the method, systematic analysis data are obtained, risk assessment is facilitated, and the risk points can be found out quickly and efficiently to improve.
Description
Technical Field
The invention relates to the technical field of printed circuit board CAM, in particular to a method for analyzing signal circuit data of industrial graphic computer-aided manufacturing.
Background
As Printed Circuit Board (PCB) line densities increase, manufacturing processes become more challenging and often must rely on associated computer aided manufacturing CAM software to complete the manufacturing. The CAM technology of the printed circuit board is widely used, and for a circuit layer, the current CAM software can list objects and the number of the objects, wherein the objects comprise straight lines, arc lines, pads, copper surfaces and pictures and texts, but no more systematic summary can be made on the interrelations among the objects.
In addition, during manufacturing, each object on the circuit layer is affected by different materials and processes to different degrees, and the current CAM software cannot analyze each object on the circuit layer according to different process capabilities to find out a risk point, which needs to be improved.
Disclosure of Invention
The invention mainly solves the technical problem of providing an analysis method of signal line data of industrial graphic computer-aided manufacturing, which can systematically summarize and analyze the interrelation among objects and conveniently find out risk points.
In order to solve the technical problems, the invention adopts a technical scheme that: the method for analyzing the signal circuit data of the industrial graphic computer-aided manufacturing comprises the following steps:
leading in and confirming data of signal circuit manufacture yield related layers into a computer, wherein the signal circuit manufacture yield related layers comprise a hole layer, a molding layer and a signal layer;
step two, analyzing the signal layer objects, and listing the Size and the number of the Size objects in the table (1);
(1) size and number of Size pieces:
(1.1) Line Linear object
(1.2) Arc article
(1.3) Pad article
(1.4) Text-Text object
(1.5) Text Fields Text string
(1.6) possible Line break of Line neutral Down
(1.7) line objects with shaded Lines masked by negative data
(1.8) arc objects with shaded Arcs shaded with negative data
(1.9) pads where shielded SMDs are masked by negative data;
screening an SMD bonding Pad and a Pad from the step (1.3) and the step (1.9), and after interactive analysis, listing the risk related to the SMD and the bonding Pad in the table (2);
(2) SMD risks related to pads:
(2.1) SMD Pads
(2.2) SMD to Pad
(2.3) SMD to SMD pad-to-pad;
comparing and analyzing the (1) and the molding layer, and listing (3) Rout related risks to molding in a table;
(3) rout risks associated with molding:
(3.1) Rout to Copper forming pitch for all Copper articles;
step five, after analyzing (1.1) and (1.2), listing (4) the risk of thickness change of the Bottleneck line in a table;
(4) the risk of variation in thickness of the Bottleneeck line:
(4.1) the Conductor Width line is too thin;
comparing and analyzing each item in the step (1), and listing (5) Spacing and space related risks, (6) Sliver gap or filament risks and (7) Connection object Connection risks;
(5) spacing is associated with the risk of Spacing:
(5.1) Pad to Pad spacing
(5.2) Pad-to-Circuit Pad pitch loop
(5.3) SMD to Circuit pad pitch loop
(5.4) Circuit to Circuit Loop spacing Loop
(5.5) the space between the Same Net Spacing and the network is too close
(5.6) Spacing Length parallel Spacing
(5.7) BGA to Circuit ball pad pitch loop
(5.8) Feature to Feature object distance object
(5.9) BGA to BGA ball pad Pitch ball pad
(5.10) BGA to Pad ball Pad pitch Pad
(5.11) Pad to Line Mat distance Line
(5.12) Pad to Surface Pad distance copper Surface
(5.13) Via to Copper-Same Net with Via-pitch other Copper objects under the Same network
(5.14) Circuit to Line Loop Pitch Line
(5.15) Line to Line spacing Line
(5.16) Via-Pad to Via-Pad spacing Via Pad
(5.17) PTH-Pad to PTH-Pad plating through hole Pad distance plating through hole Pad;
(6) sliver gap or filament risk:
(6.1) too small spaces between drivers and too small copper area
(6.2) the distance between Local Spacing closed zones is too small;
(7) connection item Connection risk:
(7.1) Pad to Pad Connection Pad too close to Pad
(7.2) Pad to Cu Connection Pad too close to copper face
(7.3) Pad to Line Connection Pad too close to Line
(7.4) Stubs broken;
step seven, comparing and analyzing the (1) and the pore layer, and listing (8) the risk related to the Drill and the pore;
(8) hole-related risk for Drill:
(8.1) PTH to Copper plated through hole distance to other Copper article
(8.2) PTH Registration plated through hole overlay
(8.3) Miss Pad for PTH plated through hole lack Pad
(8.4) PTH Annular Ring plated through hole distance self-pad
(8.5) PTH to Line plated through hole pitch Line
(8.6) PTH to Pad plated through hole distance Pad
(8.7) NPTH to Pad non-plated through hole spacer
(8.8) NPTH to Circuit non-plated through hole distance loop
(8.9) NPTH Touches Copper non-plated through hole contact to other Copper article
(8.10) NPTH Registration non-plated through hole overlay
(8.11) NPTH Annular Ring non-plated through hole pitch pad itself
(8.12) Via to Line Via pitch Line
(8.13) Via to Pad conducting pitch Pad
(8.14) Via to Copper Via spacing to other Copper articles
(8.15) Via Annular Ring conducting Pitch pad
(8.16) Missing Pad for Via hole lack itself
(8.17) Missing Cu for Via is not placed in the copper object;
and integrating scattered data into correlated systematic analysis data with reference value.
In a preferred embodiment of the present invention, the method further comprises performing simulation before manufacturing according to the systematic analysis data, evaluating risk places and feeding back to the corresponding design end, material supplier, equipment supplier or industrial software development end.
In a preferred embodiment of the invention, the data of the aperture layer, the shaping layer and the signal layer are each generated as a file or are generated together as a file.
The beneficial effects of the invention are: the method for analyzing the signal line data of the industrial graphic computer-aided manufacturing analyzes the hole layer, the forming layer and the signal layer to obtain systematic analysis data, conveniently, quickly and efficiently evaluates risks, is favorable for analyzing risk points according to specific process capacity to improve and improves the manufacturing yield.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention comprises the following steps:
a method for analyzing signal line data for computer aided manufacturing of industrial graphics, comprising the steps of:
the method comprises the steps of firstly, importing and confirming data of a signal line manufacturing yield related layer into a computer, wherein the signal line manufacturing yield related layer comprises a hole layer, a molding layer and a signal layer;
analyzing the signal layer objects through analysis software in a computer, and listing the Size and the number of (1) Size objects in a table;
(1) size and number of Size pieces:
(1.1) Line Linear object
(1.2) Arc article
(1.3) Pad tray article
(1.4) Text-Text object
(1.5) Text Fields Text string
(1.6) possible Line break of Line neutral Down
(1.7) shaded Lines Linear objects with negative data
(1.8) arc objects with shaded Arcs shaded with negative data
(1.9) pads where shielded SMDs are masked by negative data;
classifying all objects on a complex circuit board, wherein the objects on the circuit board are numerous and must be classified, and the classification mode comprises shape classification and actual function classification;
screening an SMD bonding Pad and a Pad from the step (1.3) and the step (1.9), and after interactive analysis, listing the risk related to the SMD and the bonding Pad in the table (2);
(2) SMD risks related to pads:
(2.1) SMD Pads
(2.2) SMD to Pad
(2.3) SMD to SMD pad-to-pad;
the SMD Pad is a special Pad, and the Pad has a large influence on the yield of the circuit board and needs to be taken out for research;
comparing and analyzing each sub item under the step (1) with a forming layer one by one, and listing the risk related to the forming of Rout in a table (3);
(3) rout risks associated with molding:
(3.1) Rout to Copper forming pitch for all Copper articles;
step five, after the (1.1) and the (1.2) are analyzed, the (4) Bottleneeck line thickness change risk is listed in a table;
(4) the risk of variation in thickness of the Bottleneeck line:
(4.1) the Conductor Width line is too thin;
wherein, the (1.1) straight line of the table (1.2) table arc line, analyze two kinds of lines, analyze its size, distance, etc., the width is insufficient is too thin;
comparing and analyzing each item in the step (1), and listing (5) Spacing and interval related risks, (6) Sliver clearance or filament risks and (7) Connection object Connection risks;
(5) spacing is associated with the risk of Spacing:
(5.1) Pad to Pad distance Pad
(5.2) Pad-to-Circuit Pad pitch loop
(5.3) SMD to Circuit pad pitch loop
(5.4) Circuit to Circuit Loop distance Loop
(5.5) the space between the Same Net Spacing and the network is too close
(5.6) Spacing Length parallel Spacing
(5.7) BGA to Circuit ball pad pitch loop
(5.8) Feature to Feature object distance object
(5.9) BGA to BGA ball pad Pitch ball pad
(5.10) BGA to Pad ball Pad pitch Pad
(5.11) Pad to Line Mat Pitch Line
(5.12) Pad to Surface Pad distance copper Surface
(5.13) Via to Copper-Same Net with Via-pitch other Copper objects under the Same network
(5.14) Circuit to Line Loop Pitch Line
(5.15) Line to Line spacing Line
(5.16) Via-Pad to Via-Pad spacing Via Pad
(5.17) PTH-Pad to PTH-Pad plating through hole Pad distance plating through hole Pad;
(6) sliver gap or filament risk:
(6.1) too small spaces between drivers and too small copper area
(6.2) the distance between Local Spacing closed zones is too small;
(7) connection item Connection risk:
(7.1) Pad to Pad Connection Pad too close to Pad
(7.2) Pad to Cu Connection Pad too close to copper face
(7.3) Pad to Line Connection Pad too close to Line
(7.4) Stubs broken;
comparing and analyzing the (1) and the hole layer, and listing (8) the risk related to the Drill and the hole aiming at various process manufacturing of the PCB;
(8) hole-related risk for Drill:
(8.1) PTH to Copper plated through hole distance to other Copper article
(8.2) PTH Registration plated through hole overlay
(8.3) Miss Pad for PTH plated through hole lack Pad
(8.4) PTH Annular Ring plated through hole distance self-pad
(8.5) PTH to Line plated through hole pitch Line
(8.6) PTH to Pad plated through hole distance Pad
(8.7) NPTH to Pad non-plated through hole spacer
(8.8) NPTH to Circuit non-plated through hole distance loop
(8.9) NPTH Touches Copper non-plated through hole contact to other Copper article
(8.10) NPTH Registration non-plated through hole overlay
(8.11) NPTH Annular Ring non-plated through hole distance pad
(8.12) Via to Line Via pitch Line
(8.13) Via to Pad conducting pitch Pad
(8.14) Via to Copper Via distance to other Copper article
(8.15) Via Annular Ring conducting Pitch pad
(8.16) Missing Pad for Via hole lack itself
(8.17) Missing Cu for Via is not placed in the copper object;
and integrating scattered data into systematic analysis data which are correlated with each other and have reference values, and performing simulation by a board factory engineer before manufacturing according to the systematic analysis data, evaluating risk positions and feeding back the risk positions to corresponding design terminals, material suppliers, equipment suppliers or industrial software development terminals for continuous improvement.
For example, the Same Net Spacing project:
the threshold is set at 10 mils, meaning that any object on the circuit under the same network will be easily shorted if the pitch is less than 10 mils.
The reason is that although the design is ideally below 10mil, the practical design interval cannot be perfectly achieved due to process errors, environmental variables, etc. during manufacturing, and when the object is too close, not only the wires are mistakenly connected together to cause short circuit, but also other problems may be caused by electromagnetic force, etc.
After the analysis method is used for analyzing, systematic analysis data with reference values are provided, risks are conveniently evaluated, improvement on aspects such as design, materials and production equipment of risk positions is facilitated, and accordingly yield during actual production is improved.
In summary, the method for analyzing signal line data of industrial graphic computer aided manufacturing provided by the invention can analyze the signal line data of industrial graphic computer aided manufacturing to obtain systematic analysis data with reference value, which is beneficial to risk assessment and continuous improvement according to specific process capability, and reduces the risk of line short circuit and other problems in the production process.
The above description is only an embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (7)
1. A method for analyzing signal line data of industrial graphic computer-aided manufacturing is characterized in that,
the method comprises the following steps:
leading in and confirming data of signal circuit manufacture yield related layers into a computer, wherein the signal circuit manufacture yield related layers comprise a hole layer, a molding layer and a signal layer;
step two, analyzing the signal layer objects, and listing the Size and the number of (1) Size objects in a table;
(1) size and number of Size pieces:
(1.1) Line Linear object
(1.2) Arc article
(1.3) Pad article
(1.4) Text-Text object
(1.5) Text Fields Text string
(1.6) possible Line break of Line neutral Down
(1.7) line objects with shaded Lines masked by negative data
(1.8) arc objects with shaded Arcs shaded with negative data
(1.9) pads where shielded SMDs are masked by negative data;
screening an SMD bonding Pad and a Pad from the step (1.3) and the step (1.9), and after interactive analysis, listing the risk related to the SMD and the bonding Pad in the table (2);
(2) SMD risks related to pads:
(2.1) SMD Pads
(2.2) SMD to Pad
(2.3) SMD to SMD pad to pad;
comparing and analyzing the (1) and the molding layer, and listing (3) Rout related risks to molding in a table;
(3) rout risks associated with molding:
(3.1) Rout to Copper forming pitch for all Copper articles;
step five, after the (1.1) and the (1.2) are analyzed, the (4) Bottleneeck line thickness change risk is listed in a table;
(4) the risk of variation in thickness of the Bottleneeck line:
(4.1) the Conductor Width line is too thin;
comparing and analyzing each item in the step (1), and listing (5) Spacing and space related risks, (6) Sliver gap or filament risks and (7) Connection object Connection risks;
step seven, comparing and analyzing the (1) and the pore layer, and listing (8) the risk related to the Drill and the pore;
and integrating scattered data into correlated systematic analysis data with reference value.
2. The method of analyzing signal line data for computer aided manufacturing of industrial graphics according to claim 1, further comprising performing simulation before manufacturing based on the systematic analysis data, evaluating risk and feeding back to corresponding design end, material supplier, equipment supplier or industrial software development end.
3. The method for analyzing signal line data for computer aided manufacturing of industrial graphics according to claim 1, wherein the data of the orifice layer, the molding layer and the signal layer are each generated as one file or are generated as one file together.
4. The method for analyzing signal line data for computer aided manufacturing of industrial graphics according to claim 1, wherein (5) Spacing-related risks:
(5.1) Pad to Pad spacing
(5.2) Pad-to-Circuit Pad pitch loop
(5.3) SMD to Circuit pad pitch loop
(5.4) Circuit to Circuit Loop distance Loop
(5.5) the space between the Same Net Spacing and the network is too close
(5.6) Spacing Length parallel Spacing
(5.7) BGA to Circuit ball pad pitch loop
(5.8) Feature to Feature object distance object
(5.9) BGA to BGA ball pad Pitch ball pad
(5.10) BGA to Pad ball Pad pitch Pad
(5.11) Pad to Line Mat Pitch Line
(5.12) Pad to Surface Pad distance copper Surface
(5.13) Via to Copper-Same Net with Via-pitch other Copper objects under the Same network
(5.14) Circuit to Line Loop Pitch Line
(5.15) Line to Line spacing Line
(5.16) Via-Pad to Via-Pad spacing Via Pad
(5.17) PTH-Pad to PTH-Pad plated through hole Pad to through hole Pad.
5. The method of analyzing signal line data for computer-aided manufacturing of industrial graphics according to claim 1, characterized by (6) driver gap or filament risk:
(6.1) too small spaces between drivers and too small copper area
(6.2) the distance between the Local Spacing closed zones is too small.
6. The method for analyzing signal line data for industrial graphic computer-aided manufacturing according to claim 1, wherein (7) Connection item Connection risk:
(7.1) Pad to Pad Connection Pad too close to Pad
(7.2) Pad to Cu Connection Pad too close to copper face
(7.3) Pad to Line Connection Pad too close to Line
(7.4) Stubs broken string.
7. The method for analyzing signal trace data for industrial graphic computer aided manufacturing according to claim 1, wherein (8) hole-related risk of Drill:
(8.1) PTH to Copper plated through hole distance to other Copper article
(8.2) PTH Registration plated through hole overlay
(8.3) Miss Pad for PTH plated through hole lack Pad
(8.4) PTH Annular Ring plated through hole distance self-pad
(8.5) PTH to Line plated through hole pitch Line
(8.6) PTH to Pad plated through hole distance Pad
(8.7) NPTH to Pad non-plated through hole spacer
(8.8) NPTH to Circuit non-plated through hole distance loop
(8.9) NPTH Touches Copper non-plated through hole contact to other Copper article
(8.10) NPTH Registration non-plated through hole overlay
(8.11) NPTH Annular Ring non-plated through hole distance pad
(8.12) Via to Line Via pitch Line
(8.13) Via to Pad conducting pitch Pad
(8.14) Via to Copper Via spacing to other Copper articles
(8.15) Via Annular Ring conducting Pitch pad
(8.16) Missing Pad for Via hole lack itself
(8.17) Missing Cu for Via is not placed in the copper object.
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| CN109543307A (en) * | 2018-11-23 | 2019-03-29 | 上海望友信息科技有限公司 | PCB design domain opens test for short-circuit method, detection system and electronic equipment |
| CN110516390A (en) * | 2019-09-02 | 2019-11-29 | 江西众晶源科技有限公司 | A kind of high-density packages integrated circuit linkage silk touching methods of risk assessment |
| CN112818624A (en) * | 2021-01-06 | 2021-05-18 | 深圳沸石智能技术有限公司 | Method for generating printed circuit board design drawing, printed circuit board and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109543307A (en) * | 2018-11-23 | 2019-03-29 | 上海望友信息科技有限公司 | PCB design domain opens test for short-circuit method, detection system and electronic equipment |
| CN110516390A (en) * | 2019-09-02 | 2019-11-29 | 江西众晶源科技有限公司 | A kind of high-density packages integrated circuit linkage silk touching methods of risk assessment |
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