CN111737945A - Back drilling design method, system, terminal and storage medium of PCB - Google Patents
Back drilling design method, system, terminal and storage medium of PCB Download PDFInfo
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- CN111737945A CN111737945A CN202010470922.4A CN202010470922A CN111737945A CN 111737945 A CN111737945 A CN 111737945A CN 202010470922 A CN202010470922 A CN 202010470922A CN 111737945 A CN111737945 A CN 111737945A
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- 238000005553 drilling Methods 0.000 title claims abstract description 140
- 238000013461 design Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000012216 screening Methods 0.000 claims abstract description 28
- 238000012545 processing Methods 0.000 claims description 8
- 238000004590 computer program Methods 0.000 claims description 3
- 238000012790 confirmation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 69
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
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Abstract
The invention provides a back drilling design method, a system, a terminal and a storage medium of a PCB, comprising the following steps: setting attribute information of the back drilling signal, and screening and marking the back drilling signal from a PCB design graph according to the attribute information; extracting back drilling signal topology information of all layers and each layer from the PCB design graph, and screening out invalid layers of back drilling signals from all layers according to the back drilling signal topology information; screening out the coordinates of the through holes and the bonding pads corresponding to the back drilling signals from the invalid layer; and creating an avoidance area taking the coordinates of the via hole and the pad as the center on the invalid layer, wherein the avoidance area is a blank area without routing. The invention can avoid the PCB quality problem possibly caused by back drilling deviation in advance, and effectively improves the design efficiency and the design quality.
Description
Technical Field
The invention relates to the technical field of PCB processing, in particular to a back drilling design method, a back drilling design system, a back drilling terminal and a storage medium of a PCB.
Background
In high speed interconnect systems, the signal line rate on the PCB is higher and higher, and the requirements on signal integrity and electromagnetic compatibility are stricter and stricter. When signal rates reach certain values, especially rates greater than 8Gbps, signal integrity and electromagnetic interference issues due to vias and PTH pad stubs must be considered. On a PCB board, when a signal line is replaced through a via hole, if it is not replaced from a surface layer to another surface layer, a layer (stub) having an excessive copper plated portion is always generated. This excess copper plating increases the inductive value of the via, resulting in increased loss of high speed signals; the redundant copper plating is also equivalent to an antenna, signal radiation is generated to cause interference on other surrounding signals, the normal operation of a line system is affected in severe cases, and the backsill is used for drilling the redundant copper plating in a drilling mode, so that the EMI problem is eliminated.
Most PCB manufacturers have the back drilling capability, but the back drilling capability of different manufacturers is different, the situation that peripheral wiring is damaged due to drilling deviation caused by the influence of drilling tolerance and the like in the back drilling process occurs, and the product function is seriously and directly influenced. Generally, the distances from the drilling holes and the PTH pads to all the vias, pads, traces, copper foils and the like related to the layer are controlled according to the specification, and not only the total pitch rule of the signals needing to be back-drilled is set independently, but also all the pitch rules related to the layer for back-drilling are set continuously on the total pitch rule. This process is very cumbersome for PCB Layout engineers, labor intensive, and easily missed.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method, a system, a terminal and a storage medium for designing a back drill of a PCB board, so as to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a back drilling design method for a PCB, including:
setting attribute information of the back drilling signal, and screening and marking the back drilling signal from a PCB design graph according to the attribute information;
extracting back drilling signal topology information of all layers and each layer from the PCB design graph, and screening out invalid layers of back drilling signals from all layers according to the back drilling signal topology information;
screening out the coordinates of the through holes and the bonding pads corresponding to the back drilling signals from the invalid layer;
and creating an avoidance area taking the coordinates of the via hole and the pad as the center on the invalid layer, wherein the avoidance area is a blank area without routing.
Further, after screening and marking the back drilling signal from the PCB design pattern, the method further comprises:
judging whether the screened back drilling signal is matched with a back drilling signal in a pre-stored back drilling demand table or not:
if so, judging that the back drilling signal is correct;
if not, the back drilling signal is judged to be wrong.
Further, after the invalid layer of the back-drilling signal is screened out from all layers according to the topology information of the back-drilling signal, the method further comprises the following steps:
and exporting the wiring information of each layer to an excel, carrying out consistency comparison on the wiring information of each layer and actual wiring, and outputting error prompts of corresponding layers if the wiring information of each layer and the actual wiring are not consistent.
Further, an avoidance area with coordinates of the via hole and the pad as a center is created on the invalid layer, and the avoidance area is a blank area without routing. Previously, the method further comprises:
and setting the size of the avoiding area according to the processing capacity, the aperture of the via hole and the size of the bonding pad.
In a second aspect, the present invention provides a back drilling design system for a PCB, comprising:
the target setting unit is used for configuring attribute information for setting the back drilling signals, and screening and marking the back drilling signals from the PCB design graph according to the attribute information;
the layer extracting unit is configured for extracting back drilling signal topology information of all layers and each layer from the PCB design graph and screening out invalid layers of back drilling signals from all layers according to the back drilling signal topology information;
the coordinate screening unit is configured to screen out the coordinates of the via hole and the pad corresponding to the back drilling signal from the invalid layer;
and the area creating unit is configured to create an avoidance area with the coordinates of the via hole and the pad as the center on the invalid layer, wherein the avoidance area is a blank area without routing.
Further, the system further comprises:
the target judgment unit is configured for judging whether the screened back drilling signal is matched with a back drilling signal in a prestored back drilling demand table;
the target confirmation unit is configured for judging that the back drilling signal is correct if the screened back drilling signal is consistent with a pre-stored back drilling demand table;
and the target error unit is configured for judging that the back drilling signal is wrong if the screened back drilling signal is inconsistent with the pre-stored back drilling demand table.
Further, the system further comprises:
and the layer export unit is configured to export the wiring information of each layer to excel, compare the wiring information of each layer with the actual wiring in consistency, and output an error prompt of a corresponding layer if the wiring information of each layer is inconsistent with the actual wiring.
Further, the system further comprises:
and the area setting unit is configured for setting the size of the avoiding area according to the processing capacity, the aperture of the via hole and the size of the bonding pad.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
according to the back drilling design method, system, terminal and storage medium of the PCB, back drilling signals are automatically screened, back drilling signal information of each layer is further extracted from a PCB design graph, and invalid layers (namely layers which do not need routing and need back drilling) of the back drilling signals are screened out. And then screening out the coordinates of the via holes and the pads corresponding to the back drilling signals from the invalid layer, and setting an avoidance area on the invalid layer according to the coordinates of the via holes and the pads. The avoiding area is a blank area without the routing, so that the PCB quality problem possibly caused by back drilling deviation can be avoided in advance, and the design efficiency and the design quality are effectively improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following explains key terms appearing in the present invention.
Stub invalid layer
PTH pad
Pcb (print circuit board): printed circuit board
Backdrill: i.e. back drilling. On a PCB, when a signal line passes through a through hole and is changed in layers, if the signal line is not changed from a surface layer to another surface layer, an excessive copper plating part is always generated, and the process of drilling the excessive copper plating in a drilling mode is called backdrilling.
Cadence SKILL language: cadence company provides secondarily developed SKILL language for users, and the users can access the SKILL language and develop own tools based on Cadence platform
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. Wherein, the implementation body of fig. 1 can be a back drilling design system of a PCB board.
As shown in fig. 1, the method 100 includes:
and 140, an area creating unit configured to create an avoidance area with coordinates of the via hole and the pad as a center on the invalid layer, where the avoidance area is a blank area without traces.
In order to facilitate understanding of the present invention, the back drill design method of the PCB provided by the present invention is further described below with reference to the principle of the back drill design method of the PCB of the present invention and the design process of the back drill of the PCB in the embodiments.
Specifically, the back drilling design method of the PCB comprises the following steps:
and S1, setting the attribute information of the back drilling signal, and screening and marking the back drilling signal from the PCB design graph according to the attribute information.
Inputting net names or keywords for rapid filtering according to the search requirements of users, screening back drilling signals from PCB design graphs, and leading out the screened back drilling signals (the back drilling signals are component information needing back drilling) and comparing the back drilling signals with a back drilling requirement table provided by engineers. If the comparison is consistent, the screened back drilling signals are complete, and if the comparison is inconsistent, the back drilling signals are searched again according to the back drilling requirement table.
S2, extracting back drilling signal topology information of all layers and each layer from the PCB design graph, and screening out invalid layers of back drilling signals from all layers according to the back drilling signal topology information.
And automatically extracting the topological information of the laminated PCB and the back drilling signal, and displaying the wiring layer with the back drilling attribute signal and the invalid layer without the wiring, wherein all the extracted layer information can be exported to excel to be compared with the actual wiring.
And S3, screening out the coordinates of the via hole and the pad corresponding to the back drilling signal from the invalid layer.
According to the topology extracted in step S2, the program may further screen and display coordinate information of the via hole and PTHpad corresponding to the back drilling signal (the coordinates of the same group of via holes and pthpads are the same), and the coordinate information may allow the user to export to excel for subsequent inspection.
And S4, creating an avoidance area with the coordinates of the via hole and the pad as the center on the invalid layer, wherein the avoidance area is a blank area without the routing.
And creating avoidance areas of the via holes and the PTH pads at corresponding positions on the invalid layer according to the coordinate information of the via holes and the PTH pads of the step S3. The avoidance area can be set to a reasonable value according to the factory manufacturing capability and the aperture. The avoiding area is a blank area without the routing.
As shown in fig. 2, the system of this embodiment is developed by using Cadence skip language, and the system 200 includes:
a target setting unit 210 configured to set attribute information of the back drilling signal, and to screen and mark the back drilling signal from a PCB design pattern according to the attribute information;
the layer extracting unit 220 is configured to extract back-drilling signal topology information of all layers and each layer from the PCB design pattern, and screen out invalid layers of back-drilling signals from all layers according to the back-drilling signal topology information;
a coordinate screening unit 230 configured to screen out via hole and pad coordinates corresponding to the back drilling signal from the invalid layer;
and an area creating unit 240 configured to create an avoidance area with coordinates of the via and the pad as a center on the invalid layer, where the avoidance area is a blank area without a trace.
Optionally, as an embodiment of the present invention, the system further includes:
the target judgment unit is configured for judging whether the screened back drilling signal is matched with a back drilling signal in a prestored back drilling demand table;
the target confirmation unit is configured for judging that the back drilling signal is correct if the screened back drilling signal is consistent with a pre-stored back drilling demand table;
and the target error unit is configured for judging that the back drilling signal is wrong if the screened back drilling signal is inconsistent with the pre-stored back drilling demand table.
Optionally, as an embodiment of the present invention, the system further includes:
and the layer export unit is configured to export the wiring information of each layer to excel, compare the wiring information of each layer with the actual wiring in consistency, and output an error prompt of a corresponding layer if the wiring information of each layer is inconsistent with the actual wiring.
Optionally, as an embodiment of the present invention, the system further includes:
and the area setting unit is configured for setting the size of the avoiding area according to the processing capacity, the aperture of the via hole and the size of the bonding pad.
Fig. 3 is a schematic structural diagram of a terminal system 300 according to an embodiment of the present invention, where the terminal system 300 may be used to execute a back drilling design method for a PCB board according to the embodiment of the present invention.
The terminal system 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention further extracts the back drilling signal information of each layer from the PCB design graph by automatically screening the back drilling signals, and screens out the invalid layer of the back drilling signals (namely, the layer which does not need routing and needs back drilling). And then screening out the coordinates of the via holes and the pads corresponding to the back drilling signals from the invalid layer, and setting an avoidance area on the invalid layer according to the coordinates of the via holes and the pads. The avoidance area is a blank area without routing, so that the PCB quality problem possibly caused by back drilling deviation can be avoided in advance, the design efficiency and the design quality are effectively improved, the technical effect achieved by the embodiment can be referred to the description above, and the description is omitted here.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A back drilling design method of a PCB is characterized by comprising the following steps:
setting attribute information of the back drilling signal, and screening and marking the back drilling signal from a PCB design graph according to the attribute information;
extracting back drilling signal topology information of all layers and each layer from the PCB design graph, and screening out invalid layers of back drilling signals from all layers according to the back drilling signal topology information;
screening out the coordinates of the through holes and the bonding pads corresponding to the back drilling signals from the invalid layer;
and creating an avoidance area taking the coordinates of the via hole and the pad as the center on the invalid layer, wherein the avoidance area is a blank area without routing.
2. The method of claim 1, wherein after screening and marking the back-drill signal from the PCB board design pattern, the method further comprises:
judging whether the screened back drilling signals are matched with back drilling signals in a pre-stored back drilling demand table or not:
if so, judging that the back drilling signal is correct;
if not, the back drilling signal is judged to be wrong.
3. The method of claim 1, wherein after screening the invalid levels of the back-drilling signal from all levels according to the back-drilling signal topology information, the method further comprises:
and exporting the wiring information of each layer to the excel, carrying out consistency comparison on the wiring information of each layer and the actual wiring, and outputting an error prompt of a corresponding layer if the wiring information of each layer and the actual wiring are inconsistent.
4. The method of claim 1, wherein an avoidance area centered on via and pad coordinates is created at the inactive level, the avoidance area being a clear area without traces. Previously, the method further comprises:
and setting the size of the avoiding area according to the processing capacity, the aperture of the via hole and the size of the bonding pad.
5. A back drill design system for a PCB board, comprising:
the target setting unit is used for configuring attribute information for setting the back drilling signals, and screening and marking the back drilling signals from the PCB design graph according to the attribute information;
the layer extracting unit is configured for extracting back drilling signal topology information of all layers and each layer from the PCB design graph and screening out invalid layers of back drilling signals from all layers according to the back drilling signal topology information;
the coordinate screening unit is configured to screen out the coordinates of the via hole and the pad corresponding to the back drilling signal from the invalid layer;
and the area creating unit is configured to create an avoidance area with the coordinates of the via hole and the pad as the center on the invalid layer, wherein the avoidance area is a blank area without routing.
6. The system of claim 5, further comprising:
the target judgment unit is configured for judging whether the screened back drilling signal is matched with a back drilling signal in a prestored back drilling demand table;
the target confirmation unit is configured for judging that the back drilling signal is correct if the screened back drilling signal is consistent with a pre-stored back drilling demand table;
and the target error unit is configured for judging that the back drilling signal is wrong if the screened back drilling signal is inconsistent with the pre-stored back drilling demand table.
7. The system of claim 5, further comprising:
and the layer export unit is configured to export the wiring information of each layer to the excel, compare the consistency of the wiring information of each layer and the actual wiring, and output an error prompt of a corresponding layer if the wiring information of each layer and the actual wiring are inconsistent.
8. The system of claim 5, further comprising:
and the area setting unit is configured for setting the size of the avoiding area according to the processing capacity, the aperture of the via hole and the size of the bonding pad.
9. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010470922.4A CN111737945A (en) | 2020-05-28 | 2020-05-28 | Back drilling design method, system, terminal and storage medium of PCB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010470922.4A CN111737945A (en) | 2020-05-28 | 2020-05-28 | Back drilling design method, system, terminal and storage medium of PCB |
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| CN111737945A true CN111737945A (en) | 2020-10-02 |
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| CN202010470922.4A Withdrawn CN111737945A (en) | 2020-05-28 | 2020-05-28 | Back drilling design method, system, terminal and storage medium of PCB |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112328554A (en) * | 2020-11-23 | 2021-02-05 | 迈普通信技术股份有限公司 | Method and device for generating secondary drilling file, electronic equipment and storage medium |
| CN112528587A (en) * | 2020-11-12 | 2021-03-19 | 苏州浪潮智能科技有限公司 | Method, system, terminal and storage medium for judging hole plugging requirement of PCB back drilling hole |
| CN113807044A (en) * | 2021-08-06 | 2021-12-17 | 苏州浪潮智能科技有限公司 | Anti-crosstalk PCIE port channel design method, system, terminal and storage medium |
| CN114867213A (en) * | 2022-05-31 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Via hole optimization method and system of high-speed crimping device, terminal and storage medium |
-
2020
- 2020-05-28 CN CN202010470922.4A patent/CN111737945A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112528587A (en) * | 2020-11-12 | 2021-03-19 | 苏州浪潮智能科技有限公司 | Method, system, terminal and storage medium for judging hole plugging requirement of PCB back drilling hole |
| CN112528587B (en) * | 2020-11-12 | 2022-07-19 | 苏州浪潮智能科技有限公司 | Method, system, terminal and storage medium for judging hole plugging requirement of PCB back drilling hole |
| CN112328554A (en) * | 2020-11-23 | 2021-02-05 | 迈普通信技术股份有限公司 | Method and device for generating secondary drilling file, electronic equipment and storage medium |
| CN112328554B (en) * | 2020-11-23 | 2022-09-13 | 迈普通信技术股份有限公司 | Method and device for generating secondary drilling file, electronic equipment and storage medium |
| CN113807044A (en) * | 2021-08-06 | 2021-12-17 | 苏州浪潮智能科技有限公司 | Anti-crosstalk PCIE port channel design method, system, terminal and storage medium |
| CN113807044B (en) * | 2021-08-06 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Crosstalk-resistant PCIE port channel design method, system, terminal and storage medium |
| CN114867213A (en) * | 2022-05-31 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Via hole optimization method and system of high-speed crimping device, terminal and storage medium |
| CN114867213B (en) * | 2022-05-31 | 2023-06-16 | 苏州浪潮智能科技有限公司 | Via optimization method, system, terminal and storage medium for high-speed crimping device |
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Application publication date: 20201002 |