CN113497131A - Power chip, control method thereof and electrical equipment - Google Patents
Power chip, control method thereof and electrical equipment Download PDFInfo
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- CN113497131A CN113497131A CN202010249977.2A CN202010249977A CN113497131A CN 113497131 A CN113497131 A CN 113497131A CN 202010249977 A CN202010249977 A CN 202010249977A CN 113497131 A CN113497131 A CN 113497131A
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
Abstract
The invention provides a power chip, a control method thereof and electrical equipment, which relate to the technical field of power semiconductor devices and comprise the following steps: the chip structure of the power chip is provided with a drift region, and the chip structure further comprises at least two emitter bonding pads and at least two grid bonding pads corresponding to the drift region; different emitter bonding pads are arranged independently, each emitter bonding pad is correspondingly matched with at least one grid bonding pad, and an isolation structure is arranged between the corresponding matched emitter bonding pad and the grid bonding pad. In the technical scheme, a plurality of mutually independent regional emitter bonding pads are divided on the power chip, each emitter bonding pad and the mutually matched grid bonding pad are communicated in a single control circuit, the number of the connected emitter bonding pads can be adjusted through the control circuit, and then the area of the actually working emitter bonding pads is adjusted according to the number of the connected emitter bonding pads, so that the current adjusting capacity and the working efficiency of the power chip can be adjusted.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a power chip, a control method thereof and electrical equipment.
Background
An insulated Gate Bipolar transistor (igbt) is a novel power device developed in the 80 th 20 th century, and it uses a Gate driving current of a MOSFET structure to provide a base current for a Bipolar junction transistor, so that it has both the large current capability of a BJT and the voltage-controlled driving circuit of a MOS transistor.
Since the IGBT is favored in the medium-high voltage field due to its extremely high current capability, it has been widely used in many fields such as motor control, smart grid, and transportation since its birth. Although the power chip has excellent large current capability, the overall working efficiency of the device carrying the power chip in the prior art is very low, which is a problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a power chip, a control method thereof and electrical equipment, and aims to solve the technical problem that the power chip in the prior art is low in working efficiency.
Through research on the structure of the IGBT power chip in the prior art, it is found that the emitter pads are basically distributed on the existing power chip, and when the structure of the IGBT is designed, in order to meet a certain current capacity, a corresponding chip area (i.e., an emitter pad area) needs to be designed, so that the larger the current capacity, the larger the chip area (i.e., the emitter pad area) needs to be. However, a larger chip area results in higher switching loss, so that a power chip with a larger rated current capacity can have higher switching loss when operated at a smaller current, and the operating efficiency in this state is not higher than that of a power chip with a smaller rated current capacity.
In practical application, the device carrying the power chip operates in a light load state most of the time, so that a smaller current is introduced in the light load state but the switching loss is higher, which directly results in low overall operating efficiency. In order to solve the technical problem, the present application provides the following technical solutions.
The chip structure of the power chip is provided with a drift region, and the chip structure further comprises at least two emitter bonding pads and at least two grid bonding pads corresponding to the drift region; different emitter bonding pads are arranged independently, each emitter bonding pad is correspondingly matched with at least one grid bonding pad, and an isolation structure is arranged between the corresponding matched emitter bonding pad and the grid bonding pad.
Furthermore, each emitter bonding pad and one gate bonding pad are correspondingly arranged, the gate bonding pad is in a first rectangle, and the emitter bonding pad, the isolation structure and the gate bonding pad jointly form a second rectangle.
Further, the first rectangle and the second rectangle share the same right angle.
Further, the center point of the first rectangle coincides with the center point of the second rectangle.
Further, each emitter pad is arranged corresponding to two gate pads.
Furthermore, the two gate pads are third rectangles with the same shape, and the emitter pads corresponding to the two gate pads are fourth rectangles;
the two gate bonding pads are symmetrically arranged on two sides of the emitter bonding pad, so that the two gate bonding pads and the emitter bonding pad form a complete rectangle.
Further, the at least two emitter pads are arranged in sequence along a straight line.
The invention also provides a control method of the power chip, which comprises the following steps:
calculating the ratio of the current of the load to the rated current of a single emitter pad;
and switching on the gate bonding pads corresponding to the emitter bonding pads which are more than or equal to the specific number.
The invention also provides electrical equipment which comprises the power chip; further comprising:
at least one control circuit electrically connected to the emitter pad and the gate pad disposed corresponding to the emitter pad.
The invention also provides electrical equipment and a control method adopting the power chip.
In the technical scheme, a plurality of mutually independent area emitter bonding pads are divided on the power chip, each emitter bonding pad and a grid bonding pad matched with each other are communicated in a single control circuit, the control circuits are controlled through a total control signal so as to control the single control circuits to be switched on or switched off under the control of the control signal, the number of the switched-on emitter bonding pads is adjusted, and then the area of the actually-working emitter bonding pads is adjusted according to the number of the switched-on emitter bonding pads, so that the current adjusting capacity and the working efficiency of the power chip can be adjusted.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram 1 of a layout of a power chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram 2 of a layout of a power chip according to an embodiment of the present invention;
fig. 3 is a schematic diagram 3 of a layout of a power chip according to an embodiment of the present invention;
fig. 4 is a schematic diagram 1 of a layout of a power chip according to another embodiment of the present invention;
fig. 5 is a schematic diagram 2 of a layout of a power chip according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a layout of a power chip according to another embodiment of the present invention;
fig. 7 is a schematic diagram of a power chip level structure according to an embodiment of the present invention.
Reference numerals:
1. an emitter pad;
2. a gate pad;
3. a collector electrode;
4. a drift region.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 1 to fig. 3, in the power chip provided in this embodiment, a chip structure of the power chip has one drift region 4, and the chip structure further includes at least two emitter pads 1 and at least two gate pads 2 corresponding to the one drift region 4; different emitter bonding pads 1 are arranged independently, each emitter bonding pad 1 is correspondingly matched with at least one grid bonding pad 2, and an isolation structure is arranged between the corresponding emitter bonding pad 1 and the grid bonding pad 2.
As known in the art, the emitter pad 1 is substantially distributed on the existing power chip, and the current capacity is proportional to the chip area (i.e., the area of the emitter pad 1), and the larger the current capacity is, the larger the chip area is required. However, a larger chip area, while enabling a larger current capacity, may instead also result in higher switching losses. That is, the current capacity is proportional to the chip area, and the switching loss is inversely proportional to the chip area. Therefore, the power chip with the larger rated current capacity has higher switching loss when operating at a smaller current, and the operating efficiency in this state is not higher than that of the power chip with the smaller rated current capacity.
In the layout structure (i.e. chip structure) of the power chip provided by the invention, in order to balance the current capacity and the working efficiency, the pad structure of the original emitter is improved to be formed by a plurality of areas of emitter pads 1 together, and the emitter pads 1 are mutually independent, so that the mutually independent operation of different emitter pads 1 can be ensured when the power chip works by introducing current. Based on the relatively independent layout structure of a plurality of emitter pads 1, each emitter pad 1 is also matched with at least one gate pad 2, the emitter pads 1 and the gate pads 2 simultaneously correspond to one drift region 4, and an isolation structure is arranged between the emitter pads and the gate pads which are correspondingly matched, wherein the isolation structure can be, for example, a PN junction isolation structure, P is connected with the emitter pads 1, and N is connected with the gate pads 2. In assembly use, each emitter pad 1 is communicated with the mutually matched gate pad 2 in a single control circuit, that is, a plurality of emitter pads 1 are respectively communicated in different control circuits. The plurality of control circuits are controlled by the total control signal to control the plurality of individual control circuits to be switched on or off under the control of the control signal, the number of the switched-on emitter pads 1 is adjusted, and the area of the emitter pads 1 which actually work is adjusted according to the number of the switched-on emitter pads 1. Of course, multiple sets of emitter pads 1 and corresponding gate pads 2 may also be controlled by one control circuit, and those skilled in the art may perform specific settings as needed, which is not described herein again.
Referring to fig. 1, in the layout structure of fig. 1, the layout of the power chip is formed by two regions of emitter pads 1, each emitter pad 1 being associated with a gate pad 2. When the power chip is assembled and used, each emitter pad 1 and the gate pad 2 matched with each other are communicated in a single control circuit, namely, the two emitter pads 1 are respectively communicated in the two control circuits. A worker can control any one of the two emitter bonding pads 1 to be communicated through a total control signal according to requirements, or can simultaneously communicate the two emitter bonding pads 1, when one emitter bonding pad 1 is communicated with the grid bonding pad 2 matched with the other emitter bonding pad, smaller current can be switched on, the load operates under lower power, and the switching loss is greatly reduced under the condition that the required through-current capacity is ensured.
When larger current capacity is needed, the two control circuits can be switched on through the control signals, so that the emitter bonding pads 1 in the two areas and the grid bonding pads 2 matched with each other all participate in working, the needed current capacity can be ensured, and the current capacity and the working efficiency of the power chip can be balanced. In addition, the number of the regions of the power chip in the layout for arranging the emitter pads 1 may be determined according to actual use requirements, for example, the power chip may be divided into 3 regions as shown in fig. 2, or divided into 4 regions as shown in fig. 3, and the like.
With continued reference to fig. 7, in a complete embodiment, the power chip may include an emitter pad 1, a gate pad 2, a collector 3, and a drift region 4. Wherein, the plurality of emitter pads 1 can divide the power chip into a plurality of emitting regions, for example, the number of emitting regions is equal to the number of gate pads 2, or at least one gate pad 2 is disposed in each emitting region into which the plurality of emitter pads 1 are divided. A plurality of emitter pads 1 and gate pads 2 each correspond to one drift region 4, and a collector 3 may be disposed on the back of the emitter pads 1 and gate pads 2. Therefore, the power chip is functionally equivalent to an independent chip structure and can be independently used to realize independent control of the power chips in different areas.
In the embodiment of the present application, the power chip may be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Fig. 1 only schematically shows a structure with two emitter pads 1, one gate pad 2 in each of the emitter regions formed by the two emitter pads 1. In practical applications, a plurality of emitter pads 1 can be arranged according to requirements.
With continuing reference to fig. 1, 2, or 3, each of the emitter pads 1 is disposed corresponding to one of the gate pads 2, the gate pads 2 are shaped as a first rectangle, and the emitter pads 1, the isolation structure, and the gate pads 2 together form a second rectangle. In a microscopic state, a large number of cells exist under the surface layer of the emitter bonding pad 1, a control signal (or a grid signal) of a control circuit is transmitted to a polysilicon grid of the cells through the grid bonding pad 2, and the opening of each cell is controlled through the polysilicon grid. Therefore, the gate pad 2 and the emitter pad 1 are compactly arranged, and the turn-on of the unit cell can be facilitated. In addition, the layout structure of the gate pad 2 and the emitter pad 1 in a rectangular structure can also reasonably utilize the area of the power chip, so that the utilization rate of the area of the power chip is improved.
With continued reference to fig. 1, 2, or 3, the first rectangle and the second rectangle share the same right angle.
At this time, the gate pad 2 is arranged at the corner of the emitter pad 1, so that the area ratio of the emitter pad 1 in the power chip can be increased on the premise of ensuring the normal work of the gate pad 2, and the gate pad 2 and the emitter pad 1 are reasonably arranged in the layout of the power chip. Grid pad 2 sets up to the rectangle structure, can form good adaptation through the regular avris of rectangle structure and emitter pad 1, guarantees that grid pad 2 and emitter pad 1 switch-on can be effective, steady open a large amount of cells on emitter pad 1 top layer in control circuit back, guarantees job stabilization nature.
With continued reference to fig. 4 or 5, the center point of the first rectangle coincides with the center point of the second rectangle.
At this time, the gate pad 2 is located at the center of the emitter pad 1, and the emitter pad 1 forms a frame structure capable of surrounding the gate pad 2, so that the peripheral distance between the gate pad 2 and the center of the emitter pad 1 can be more uniform, a large number of cells on the surface layer of the emitter pad 1 can be relatively uniformly opened, and the working stability of the power chip can be improved.
With continued reference to fig. 6, each of the emitter pads 1 is disposed in correspondence with two of the gate pads 2. As can be seen from the foregoing, in addition to the operation using the structure in which a single emitter pad 1 is provided corresponding to a single gate pad 2, the operation may be performed by providing a single emitter pad 1 corresponding to two or more gate pads 2. When the number of the gate pads 2 is more than 1, two or more gate pads 2 can be connected through the gate bus, and the action consistency of the cells at each position of the power chip in the switching process of the device can be effectively improved in such a way.
Continuing to refer to fig. 6, two of the gate pads 2 are third rectangles having the same shape, and the emitter pad 1 disposed corresponding to the two gate pads 2 is fourth rectangle; the two gate pads 2 are symmetrically arranged on two sides of the emitter pad 1, so that the two gate pads 2 and the emitter pad 1 form a complete rectangle.
At this time, after arranging two gate pads 2 at both symmetrical sides of the emitter pad 1, the two gate pads 2 may be connected through a gate bus line so as to be simultaneously used in cooperation with the emitter pad 1. By the layout structure, the cells at all positions of the power chip can be ensured to act consistently in the switching process of the device, the opening degree is consistent, and the reliability of the power chip is improved.
Referring to fig. 1 to 6, the at least two emitter pads 1 are sequentially arranged along a straight line. At this moment, the emitter bonding pads 1 in the multiple regions are arranged along a straight line, so that the layout of the power chip can be ensured to be more regular, and when the power chip is connected to multiple control circuits, the connection stability can be ensured, so that the whole power chip is more efficiently and stably assembled.
The invention also provides a control method of the power chip, which comprises the following steps:
calculating the ratio of the current of the load to the rated current of a single emitter pad 1;
and turning on the gate bonding pads 2 corresponding to the emitter bonding pads 1 of which the number is greater than or equal to the ratio number.
In the control method of the power chip, the description of the technical content of the power chip in the foregoing can be referred to for the layout structure of the power chip. Based on the design of the layout of the power chip, each emitter pad 1 and the gate pad 2 matched with each other can be communicated in a single control circuit, and each control circuit controls one emitter pad 1 to be communicated with or disconnected from the matched gate pad 2 independently.
In this case, a corresponding arithmetic device such as a controller or a processor may be connected to the load and simultaneously connected to the plurality of control circuits. In the calculation process, the processor is electrically connected with the load to obtain first data information of current currently required by the load, the first data information is compared with preset or stored second data information of rated current of a single emitter bonding pad 1, a ratio of the current represented by the first data information and the current represented by the second data information is calculated, and then the ratio is carried upwards to be an integer. For example, when the ratio is 1.6, the carry-up is rounded to 2; when the ratio is 3.6, the carry-up is rounded to 4. Then, a control command for controlling the connection or disconnection of the plurality of control circuits is generated and sent to the electrically connected controller.
Then, the controller is electrically connected with the processor, acquires the control command, and controls the connection or disconnection of all the control circuits according to the control command. For example, when the ratio is 1.6 and the carry-up is rounded to 2, the control circuit of 2 emitter pads 1 is turned on at this time; when the ratio is 3.6 and the carry-up is rounded to 4, the control circuit for 4 emitter pads 1 is turned on at this time.
In summary, according to the above control method, any number of emitter pads 1 in the plurality of emitter pads 1 can be controlled to be connected through the total control signal, and when the number of the emitter pads 1 which are connected individually and the number of the gate pads 2 which are matched with each other are smaller, a correspondingly smaller current can be switched on, so that the load can operate at a lower power, and the switching loss can be greatly reduced while the required current capacity is ensured. Meanwhile, the number of the connected emitter bonding pads 1 is increased to improve the current capacity, and meanwhile, the switching loss is properly increased, so that the current capacity and the working efficiency of the power chip are balanced.
The invention also provides electrical equipment which comprises the power chip; further comprising:
at least one control circuit, each of which is electrically connected to the emitter pad 1 and the gate pad 2 which are correspondingly disposed.
As can be seen from the foregoing, according to the power chip structure shown in fig. 1 to 6, multiple sets of emitter pads 1 and corresponding gate pads 2 can be controlled by one control circuit, and each emitter pad 1 and the gate pad 2 that is matched with each other can be connected in one separate control circuit, so in the electric control connection structure of the electrical equipment, multiple matched control circuits are configured according to the number of emitter pads 1, and each control circuit separately controls one emitter pad 1 to be connected or disconnected with the matched gate pad 2.
At the moment, a worker can control any number of emitter bonding pads 1 in the plurality of emitter bonding pads 1 to be communicated through a total control signal according to requirements, and when the number of the independently communicated emitter bonding pads 1 and the number of the mutually matched grid bonding pads 2 are smaller, the smaller current can be switched on, so that the load can operate at lower power, and the switching loss is greatly reduced under the condition of ensuring the required through-current capacity. Meanwhile, the number of the connected emitter bonding pads 1 is increased to improve the current capacity, and meanwhile, the switching loss is properly increased, so that the current capacity and the working efficiency of the power chip are balanced.
Since the specific structure, functional principle and technical effect of the power chip are all detailed in the foregoing, detailed description is omitted here. For any technical content related to the power chip, reference may be made to the above description.
The invention also provides electrical equipment and a control method adopting the power chip. When the electrical device adopts the control method of the power chip, reference may be made to the content described above, and details are not repeated here.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A power chip is provided with a drift region in a chip structure, and is characterized in that the chip structure further comprises at least two emitter bonding pads and at least two grid bonding pads corresponding to the drift region; different emitter bonding pads are arranged independently, each emitter bonding pad is correspondingly matched with at least one grid bonding pad, and an isolation structure is arranged between the corresponding matched emitter bonding pad and the grid bonding pad.
2. The power chip of claim 1, wherein each of the emitter pads is disposed corresponding to one of the gate pads, the gate pads are shaped as a first rectangle, and the emitter pads, the isolation structures and the gate pads together form a second rectangle.
3. The power chip of claim 2, wherein the first rectangle and the second rectangle share a same right angle.
4. The power chip of claim 2, wherein a center point of the first rectangle coincides with a center point of the second rectangle.
5. The power chip of claim 1, wherein each emitter pad is disposed in correspondence with two gate pads.
6. The power chip of claim 5, wherein two of the gate pads are third rectangles having the same shape, and the emitter pads disposed corresponding to the two gate pads are fourth rectangles;
the two gate bonding pads are symmetrically arranged on two sides of the emitter bonding pad, so that the two gate bonding pads and the emitter bonding pad form a complete rectangle.
7. The power chip of any of claims 1-6, wherein the at least two emitter pads are arranged in series along a straight line.
8. A method for controlling a power chip, comprising the steps of any one of claims 1 to 7, as follows:
calculating the ratio of the current of the load to the rated current of a single emitter pad;
and switching on the gate bonding pads corresponding to the emitter bonding pads which are more than or equal to the specific number.
9. An electrical device comprising the power chip of any one of claims 1-7; further comprising:
at least one control circuit electrically connected to the emitter pad and the gate pad disposed corresponding to the emitter pad.
10. An electric appliance characterized by adopting the control method of the power chip as claimed in claim 8.
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| CN202010249977.2A CN113497131A (en) | 2020-04-01 | 2020-04-01 | Power chip, control method thereof and electrical equipment |
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Application publication date: 20211012 |