JP2019213244A - Electric power conversion system - Google Patents

Abstract

To decrease the number of taps of a transformer while restraining deterioration of gate drive performance and achieve the downsizing of and cost reduction of a system.SOLUTION: An electric power conversion system according to the invention comprises: a group of k sets of switch elements for connecting an emitter and a collector of a transistor element and connecting with a k phase load; a gate drive circuit for changing potential of a gate electrode of each transistor to perform on-off control of a switch state; and an insulation power supply circuit for supplying power to the gate drive circuit. The insulation power supply circuit has a transformer. The transformer has k+2 sets of taps. A first tap of one set of the k+2 sets of taps is connected with a first diode group having 2k diodes connected in parallel. Any tap other than the first tap of the k+2 sets of taps is connected with a second diode.SELECTED DRAWING: Figure 3(a)

Description

  The present invention relates to a power conversion device, and more particularly to a drive circuit that controls an inverter circuit provided in a multiphase power conversion device.

  The multi-phase power converter is configured by a k-phase voltage source inverter circuit, where k is an integer of 1 or more. The k-phase voltage source inverter circuit has k sets of switch elements in which the emitter and collector of a transistor element are connected. The collectors of each of the k sets of transistor elements are connected, and this is referred to as a P terminal. The emitters of each of the k sets of transistor elements are connected, and this is referred to as an N terminal.

  The P terminal is connected to the positive electrode of the DC voltage source, and the N terminal is connected to the negative electrode of the DC voltage source. The connection point between the emitter and collector of each of the k groups is defined as an AC output terminal. Among them, k = 3, that is, a three-phase inverter circuit is widely used.

  FIG. 1 is a block configuration diagram of a motor drive system using a three-phase power converter.

  The motor 3 has windings and is connected to an AC output terminal, and is used for variable speed drive applications in various fields.

  The inverter circuit 2 includes diodes Dup, Dvp, Dwp, Dun, Dvn, Dwn at the collector of each transistor for the purpose of circulating the current of the inductive load when the transistors Tup, Tvp, Twp, Tun, Tvn, Twn are turned off. Each cathode is connected to the emitter of each transistor and the respective anode. The transistors Tup, Tvp, Twp, Tun, Tvn, and Twn are, for example, IGBTs.

  A high voltage battery 1, a smoothing capacitor 12 for removing switching ripples, a first Y capacitor 13 for removing high frequency noise, and a second Y capacitor 14 are connected to the P terminal and N terminal of the inverter circuit 2.

  The U-phase current detector 5, the V-phase current detector 6, and the W-phase current detector 7 detect a three-phase current that flows between the inverter circuit 2 and the motor 3. The control circuit 9 mounted with a microprocessor or the like performs a predetermined control calculation so that the detected value follows the current command.

  Note that the detection voltage of the DC voltage detector 4 and the detected rotor angle of the rotation detector 8 are used in the control calculation by the control circuit 9. In response to the result, each transistor of the inverter circuit 2 is on / off controlled.

  At that time, each set of transistors is operated in a complementary manner. In addition, the potential of the emitter terminal of the transistor having the collector terminal as the P terminal (which is also a terminal for providing a reference potential for the switching voltage of the transistor) is the negative electrode potential when the other transistor in the pair is on, In this case, the potential is positive.

  Accordingly, since the emitter terminals of the transistors may be different, a short circuit current is generated between the positive electrode potential and the negative electrode potential when they are connected. Therefore, the circuit for driving each transistor is driven by the gate supplied with the insulated power supply 11b. The circuit 10 is required.

  On the other hand, the potential of the transistor having the N terminal as the emitter terminal is the potential of the negative electrode regardless of whether the transistor is on or off. However, this is a case where the voltage drop generated in the wiring impedance connecting the respective emitter terminals can be ignored. In this case, since the emitter terminals of the transistors have the same potential, they can be connected.

  Otherwise, the aforementioned voltage drop is superimposed on the negative electrode potential, and the respective emitter potentials fluctuate. Therefore, in a high-current and high-speed switching inverter circuit in which the voltage drop becomes large at the time of switching, these transistor switching circuits are also supplied with isolated power.

  Note that a switching power supply using a transformer shown in FIG. 2 is generally employed as the insulated power supply. FIG. 2 is a circuit diagram of an isolated switching power supply as an example of the switching power supply 11b shown in FIG. An insulated switching power supply as shown in FIG. 2 is described in, for example, Patent Document 1.

  In FIG. 2, the switching power supply 11 a that supplies power to the control circuit 9 that transmits and receives signals is shown as an isolation power supply in the present invention.

  As shown in FIG. 1, a transistor having a collector connected to the P terminal (hereinafter referred to as an upper arm transistor) has three elements, and a transistor having an emitter connected to the N terminal (hereinafter referred to as a lower arm transistor). ) Has three elements. Therefore, as shown in FIG. 2, there are a total of six sets of independent transformer taps. When these are referred to as secondary sides, one set of taps (referred to as primary side) for supplying power to the secondary side taps, at least a total of 7 sets are required. Here, the tap is a terminal (one set of two terminals) for connecting the lead wire of the transformer winding.

  Since the emitter terminal potential changes to the P terminal potential or the N terminal potential depending on the switching state, the secondary side upper arm transistor has a predetermined creepage or tap on the tap connected to them from the viewpoint of securing the insulation strength. It is necessary to secure a spatial distance. The same applies to the lower arm and upper arm transistors when adjacent taps are used.

  The taps on the primary side and the secondary side need to ensure a predetermined creepage or a spatial distance in accordance with the maximum potential difference generated between them.

  For example, IEC606664-1 can be referred to for a predetermined creepage or calculation of a spatial distance. According to this, the creepage distance between the transformer taps needs to be 4.63 mm or more when the material Gr of the material for forming the bobbin holding the tap and the tap is 1 and the maximum input DC voltage of the inverter is 925 VDC. Further, the spatial distance when the maximum altitude is assumed to be 6000 m needs to be 2.55 mm or more.

  In order to ensure a predetermined creepage distance between the taps, the outer dimensions of the transformer inevitably increase according to the number of taps. Therefore, the area of the board on which it is mounted increases, which becomes an obstacle to downsizing.

  Examples of avoiding this are described in Patent Document 2 and Patent Document 3, for example.

  In Patent Document 2, the emitter terminals of the lower arm transistors (three elements) are connected to each other. As a result, the number of transformer taps constituting the insulated power supply can be reduced by two sets. However, as described above, it is difficult to adopt in a system in which the voltage drop generated in the wiring impedance connecting each emitter terminal is large.

  In Patent Document 3, even in a system in which an impedance is inserted into a path connecting the emitter terminal of the lower arm transistor and the power supply and a voltage drop generated in the wiring impedance connecting each emitter terminal is large, the transformer constituting the insulated power supply is also disclosed. A technique that can reduce the number of taps by two is disclosed.

  However, in the circuit diagram described in Patent Document 2, there is a need to further suppress the maximum rating applied to the gate terminal of the transistor.

JP 2013-222050 A JP 2008-29060 A Japanese Patent Laying-Open No. 2015-33222

  An object of the present invention is to reduce the number of taps of a transformer while suppressing a decrease in gate drive performance, and to achieve downsizing and cost reduction of the system.

  A power conversion device according to the present invention includes a set of k switch elements that connect an emitter and a collector of a transistor element and that is connected to a k-phase load, a positive electrode terminal that connects a collector of the k sets of the transistor elements, Switch state by changing the potential of the negative electrode terminal connecting the emitters of the k sets of the transistor elements, the AC output terminal connecting the connection points of the emitters and the collectors of the sets, and the gate electrodes of the transistor elements. A gate drive circuit that controls on / off of the power supply, and an insulated power supply circuit that supplies power to the gate drive circuit, wherein the insulated power supply circuit includes a transformer, and the transformer includes k + 2 sets of taps, Among the k + 2 sets of taps, one set of the first taps includes 2k first diode groups connected in parallel and the k + 2 sets of taps of the first tap. The one of the tap other than the flop is connected to a second diode.

  According to the present invention, it is possible to reduce the number of taps of a transformer while suppressing a decrease in gate drive performance, and to achieve downsizing and cost reduction of the system.

It is a block block diagram of the motor drive system using a three-phase power converter. It is a circuit diagram which becomes an example of an insulation type switching power supply. It is a circuit diagram which shows the insulated power supply circuit and inverter circuit which concern on this embodiment. The operation of the circuit according to FIG. 3A is obtained by analyzing the voltages V (gu, eu), V (gv, ev), and V (gw, ew) between the emitters and the gates of the transistors Tun, Tvn, and Twn. is there. It is a circuit diagram which shows the insulated power supply circuit and inverter circuit which concern on the comparative example 1. It is the result of having analyzed operation of the circuit concerning Drawing 4 (a). It is a circuit diagram which shows the insulated power supply circuit and inverter circuit which concern on the comparative example 2. It is the result of having analyzed the operation | movement of the circuit which concerns on Fig.5 (a). It is a circuit diagram concerning an insulation type switching power supply concerning other embodiments.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3A is a circuit diagram showing an insulated power supply circuit and an inverter circuit according to the present embodiment. In describing the operation related to the circuit, wiring inductances Lun, Lvn, Lwn, leun, levn, and lewn necessary for consideration of the emitter terminal potential of the lower arm transistor are added to the inverter circuit (omitted in FIG. 1). .

  Gate drive circuits GCup, GCvp, GCwp, GCun, GCvn, and GCwn connected to each transistor correspond to the gate drive circuit 10 shown in FIG. This is achieved by insulating the switching signals Sup, Svp, Swp, Sun, Svn, Swn from the control circuit 9 shown in FIG. 1 with a photocoupler and the like, and supplying them to the gate terminals of the corresponding transistors through an appropriate amplifier circuit. .

  The power supplies Eup, Evp, and Ewp supply insulated power to the gate drive circuits GCup, GCvp, and GCwp, respectively.

  The power supply voltage of the gate drive circuit GCun is supplied after the output voltage of the transformer winding Ln is smoothed by the diodes D1un, D0un and Cun. The power supply voltage of the remaining gate drive circuit GCxn is supplied after the output voltage of the same transformer winding Ln is smoothed by the diodes D1xn, D0xn and Cxn. Here, x is v or w.

  The circuit on the primary side of the transformer is different in that one end of the transformer winding L0 is connected to the drain of the switching element (FET) S0 through the anode of the diode D0. However, since there is no change in the excitation operation of the transformer T due to the on / off of the switching element S0, it is necessary to use a plurality of transformers by sharing the windings Lup, Lvp, and Lwp of FIG. 2 with L0 and Ln. Absent.

  That is, the total of 7 windings (7 sets of taps) of windings L0, Lup, Lvp, Lwp, Lun, Lvn, and Lwn in FIG. 2 are 5 windings (5 sets of L0, Lup, Lvp, Lwp, and Ln). (Tap).

  FIG. 3B shows the operation of the circuit according to FIG. 3A with the voltages V (gu, eu), V (gv, ev), V (gw, Vb) between the emitters and gates of the transistors Tun, Tvn, and Twn. ew) is a result of analysis.

  Here, the wiring inductances Lun, Lvn, and Lwn shown in FIG. 2 were set to 30 nH (resistance component 60 uΩ), and leun, levn, and lewn were set to 10 nH (resistance component 0.1 Ω). The DC voltage between the PNs was set to 400 VDC, the currents during transistor switching were set to iu, iv was set to 265A, and iw was set to -530A. The transistor gate resistance is selected to be the fastest switching value within the range in which the surge voltage during ON / OFF is within the maximum rating of the device.

  Here, the PWM frequency of the inverter circuit is 10 kHz, the drive frequency of the primary side switching element S0 (FET) of the power source is 100 kHz, and the duty is set so that the secondary side voltage is 15V.

  For comparison, the comparison circuit of FIG. 4A is shown, and the result of analyzing FIG. 4A is shown in FIG. 4B. FIG. 4A is a circuit diagram showing an insulated power supply circuit and an inverter circuit according to the first comparative example. FIG. 4B shows the result of analyzing the operation of the circuit according to FIG.

    This circuit supplies an insulating power supply to the lower arm transistor as well, but as can be seen by comparing FIG. 3B and FIG. 4B, the overshoot generated in the gate voltage is almost the same.

  Next, as in the present embodiment, FIG. 5A, which is one of the comparison circuits for reducing the number of transformer taps, is shown, and the results of analyzing the operation of the circuit of FIG. ). FIG. 5A is a circuit diagram showing an insulated power supply circuit and an inverter circuit according to Comparative Example 2. FIG. 5B shows the result of analyzing the operation of the circuit according to FIG.

  According to FIG. 5B, the overshoot generated in the gate voltage is higher than that in FIG. 3B or FIG. 4B. V (gw, ew) exceeds the maximum rating ± 20 V of the transistor selected for analysis.

  This can be solved by setting the transistor gate resistance larger and slowing the switching speed, but there is a problem that the loss accompanying switching increases.

  Here, the reason why the difference between FIG. 3A according to the present embodiment and FIG. 5A according to the comparative example 2 occurs will be described.

  In this embodiment, the transformer windings of the power supply for the gate drive circuit of the lower arm transistor are concentrated in one Ln, but circuits for rectifying the output voltage are provided individually.

  At the time of switching, the emitter potential of each transistor changes due to a voltage drop v = L · di / dt generated in the wiring inductance. As a result, only the phase rectifier diode having the highest potential (for example, Du0n) is turned on.

  The diodes of other phases (for example, Dv0n and Dw0n) are turned off, and the state is equivalent to insulation. Therefore, during the switching transition period, the transformer winding is temporarily disconnected, but the supply voltage is maintained because the smoothing capacitors are provided for each phase.

  Therefore, the operation is the same as that of FIG. 4A in which the insulated power is supplied to the gate drive circuits of all transistors.

  From the viewpoint of rectification, the diodes Du0n, Dv0n, Dw0n having the cathodes connected to the transformer winding terminals are sufficient, but the diodes Du0p, Dv0p connecting the anodes to the other terminals of the transformer winding to which they are not connected. , Dw0p is added.

  The reason will be described below. If the diodes Dv0n and Dw0n are off, and there are no diodes Dv0p and Dw0p, depending on the path of the v-phase transistor emitter terminal → smoothing capacitor Cvn → smoothing capacitor Cwn → w-phase transistor emitter terminal, The emitter potential fluctuates. Diodes Du0p, Dv0p, and Dw0p prevent this variation.

  In the secondary side circuit according to the present embodiment, immediately after the primary side switching element (FET) S0 is turned on, a current is generated from the secondary side ground through the parasitic diode of the FET toward the positive electrode of the secondary side power supply. In order to prevent this, a diode D0 is added to the primary side of the transformer.

  On the other hand, in the circuit of FIG. 5 (a), one rectifier circuit is provided in the transformer winding Ln to supply power to the gate drive circuit, and through a diode having a cathode connected to the reference potential point, Each emitter terminal is connected.

  As a result, as in the present embodiment, only the diode having the highest potential is turned on and the remaining other phases are turned off at the time of switching, so that the influence of the transient emitter potential fluctuation is not given to the other phases. However, since there is no capacitor for smoothing the voltage in the path, it is considered that the capacitor is more susceptible to potential fluctuations than the present embodiment.

  Further, in the circuit of FIG. 5A, it is impossible to apply a negative voltage to the gate terminal in view of the polarity of the diode, but since this embodiment is a system for supplying power to each lower arm transistor. If a circuit as shown in FIG. 6 is connected to both ends of the smoothing capacitors Cun, Cvn, and Cwn of FIG. .

  FIG. 6 is a circuit diagram according to an isolated switching power supply according to another embodiment.

  In the circuit according to FIG. 6, a virtual ground is formed by a Zener diode 20 having an anode connected to the ground side of the rectified voltage and a cathode connected to the bias resistor 21. One end of the bias resistor 21 is connected to the positive electrode of the rectified voltage, and a predetermined bias current for obtaining a Zener voltage is passed through the Zener diode 20. A capacitor 22 and a capacitor 23 for voltage smoothing are connected in parallel to the bias resistor 21 and the Zener diode 20, respectively. The connection point between the bias resistor 21 and the Zener diode 20 is a virtual ground, which is connected to the emitter of the transistor.

  A resistor 24 is connected to the positive electrode of the rectified voltage, and the other end is connected to the collector of the npn transistor 25. The emitter is connected to the transistor gate of the inverter circuit. When the npn transistor 25 is turned on, a positive voltage E-V_DZ is applied to the gate via the resistor 24.

  A resistor 26 is connected to the ground of the rectified voltage, and the other end is connected to the collector of the pnp transistor 27. The emitter is connected to the transistor gate of the inverter circuit. When the pnp transistor 27 is turned on, a negative voltage V_DZ is applied to the gate via the resistor 26.

  The bases of the npn transistor 25 and the pnp transistor 27 are connected, and are turned on and off in response to a control signal Sxx through an insulating element such as a photocoupler through an appropriate base resistor (not shown). Here, the npn transistor 25 and the pnp transistor 27 operate in a complementary manner.

  In the embodiment, the transistor constituting the inverter circuit is an IGBT (Insulated Gate Bipolar Transistor) as an example. However, if the semiconductor element has two terminals for supplying a main current for switching control and one terminal for controlling on / off, This implementation failure is applicable. In contrast to the IGBT exemplified in the present embodiment, in the case of FET (Field Effect Transistor), the collector is replaced with the drain and the emitter is the source and the terminal for flowing the main current is read. In the case of BJT (Bipolar Junction Transistor), the gate is the base. It is sufficient to read the terminal that performs the control.

DESCRIPTION OF SYMBOLS 1 ... High voltage battery, 2 ... Inverter circuit, 3 ... Motor, 4 ... DC voltage detector, 5 ... U phase current detector, 6 ... V phase current detector, 7 ... W phase current detector, 8 ... Rotation position detection 9 ... control circuit, 10 ... gate drive circuit, 11a ... switching power supply, 11b ... switching power supply, 12 ... smoothing capacitor, 13 ... first Y capacitor, 14 ... second Y capacitor, 20 ... zener diode, 21 ... bias resistor, 22 ... smoothing capacitor, 23 ... smoothing capacitor, 24 ... resistor, 25 ... npn transistor, 26 ... resistor, 27 ... pnp transistor, 28 ... photocoupler
Tup ... IGBT, Tvp ... IGBT, Twp ... IGBT, Tun ... IGBT, Tvn ... IGBT, Twn ... IGBT, Dup ... diode, Dvp ... diode, Dwp ... diode, Dun ... diode, Dvn ... diode, Dwn ... diode, D0up ... Diode, D0vp ... Diode, D0wp ... Diode, D0un ... Diode, D0vn ... Diode, D0wn ... Diode, D1vn ... Diode, D1wn ... Diode, D0 ... Diode, Eup ... Power supply, Evp ... Power supply, Ewp ... Power supply, S0 ... FET, L0 ... transformer winding, Lup ... transformer winding, Lvp ... transformer winding, Lwp ... transformer winding, Lun ... transformer winding, Lvn ... transformer winding, Lwn ... transformer winding, Ln ... transformer winding Line, Lun ... wiring inductance, Lvn ... wiring inductance, Lwn ... wiring inductance, leun ... wiring inductance, levn ... wiring inductance, lewn ... wiring inductance, C0up ... smoothing capacitor, C0vp ... flat Smooth capacitor, C0wp ... smoothing capacitor, C0un ... smoothing capacitor, C0vn ... smoothing capacitor, C0wn ... smoothing capacitor, Cun ... smoothing capacitor, Cvn ... smoothing capacitor, Cwn ... smoothing capacitor, GCup ... gate drive circuit, GCvp ... gate drive circuit, GCwp ... Gate drive circuit, GCun ... Gate drive circuit, GCvn ... Gate drive circuit, GCwn ... Gate drive circuit

Claims (1)

A set of k switch elements connecting the emitter and collector of the transistor element and connecting to the k-phase load;
A positive terminal connecting collectors of the k sets of the transistor elements;
A negative terminal connecting the emitters of the k sets of the transistor elements;
AC output terminals connected to the connection points of the emitters and collectors of each set,
A gate drive circuit for controlling on / off of a switch state by changing a potential of each gate electrode of the transistor element;
An insulated power supply circuit for supplying power to the gate drive circuit,
The insulated power supply circuit has a transformer,
The transformer has k + 2 sets of taps,
Of the k + 2 sets of taps, 2k first diode groups connected in parallel to one set of first taps;
A power conversion device in which a second diode is connected to any one of the k + 2 sets of taps other than the first tap.

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