CN112687654B

CN112687654B - Trench gate IGBT device

Info

Publication number: CN112687654B
Application number: CN202011474042.0A
Authority: CN
Inventors: 梁利晓; 肖强; 朱利恒; 刘葳; 宁旭斌
Original assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Current assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Priority date: 2020-12-14
Filing date: 2020-12-14
Publication date: 2024-02-23
Anticipated expiration: 2040-12-14
Also published as: CN112687654A

Abstract

The present disclosure provides a trench gate IGBT device including a cell region; the cell area comprises a plurality of first cell structures and second cell structures which are alternately arranged, and the switching delay time of the first cell structures is longer than that of the second cell structures; the gate pads are located at corresponding positions of the first cell structure to compensate for delays caused by gate signal transmission. According to the characteristics of the grid electrode bonding pad, the emitter electrode bonding pad and the grid electrode bus, at least two cell structures are arranged in a chip (alternately arranged), and the grid electrode bonding pad is positioned above a first cell structure with larger switching delay time, so that the difference of electrical properties among different cell structures compensates the transmission delay of grid electrode signals in the device, the electric stress born by each part of the device is more balanced, cell switches at different positions can be synchronous, and the working reliability of the device is enhanced.

Description

Trench gate IGBT device

Technical Field

The disclosure relates to the technical field of semiconductor devices, in particular to a trench gate IGBT device.

Background

Insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs) are typical representatives of power electronics and have found widespread use in modern power electronics. The bipolar transistor has the advantages of high input impedance, small control power, simple driving circuit, high switching speed and small switching loss of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and has the advantages of high current density, reduced saturation voltage and strong current processing capability of a bipolar transistor (Bipolar Junction Transistor, BJT), so that the bipolar transistor is an ideal switching device in the power electronics field.

Among them, trench gate IGBTs are employed in medium and low voltage IGBTs to increase the power class of the device due to their higher channel density. In general, by applying a continuous pulse control signal to the gate of an IGBT, the device can be turned on and off alternately. The equivalent circuit is shown in FIG. 1, the external gate control signal is first passed through an external gate resistor (R _G ) To the gate electrode of the chip and then sequentially through the on-chip resistor (R _g ) A Gate bus resistor (R _b ) To one individual cell. Due to parasitic capacitance and the like in the chip, the time for transmitting the gate signal to each cell is delayed, which results in that the cell switches at different positions are not synchronized in the switching process of the device. Especially, with the improvement of the current level of the chip, the phenomenon that the cells are not synchronously switched due to the increase of the area of the chip is more obvious, and the working reliability of the device is seriously affected.

Disclosure of Invention

Aiming at the problems, the disclosure provides a trench gate IGBT device, which solves the technical problem that the gate signal transmission delay is serious due to the large chip area in the prior art.

In a first aspect, the present disclosure provides a trench gate IGBT device comprising:

A cell region; the cell area comprises a plurality of first cell structures and second cell structures which are alternately arranged along a preset direction, and the switching delay time of the first cell structures is longer than that of the second cell structures;

an emitter pad arranged above the cell region and used for being connected with the emitters of the first cell structure and the second cell structure;

a gate bus line disposed above the cell region and around the emitter pad, for connecting with trench gates of the first cell structure and the second cell structure;

the grid electrode bonding pad is arranged above the cell area and electrically connected with the grid electrode bus and is used for leading out the grid electrode bus; the gate pad is located at a position corresponding to the first cell structure to compensate for gate signal transmission delay.

According to an embodiment of the present disclosure, preferably, an area of each of the first cell structures within a preset range of the gate pad is larger than an area of each of the first cell structures outside the preset range.

According to an embodiment of the present disclosure, preferably, an area of each of the second cell structures within the preset range of the gate pad is larger than an area of each of the second cell structures outside the preset range.

Preferably, according to an embodiment of the present disclosure, the cell region further includes a third cell structure and a fourth cell structure;

the first cell structure, the second cell structure, the third cell structure and the fourth cell structure are sequentially and alternately arranged along the preset direction;

the switching delay time of the third cell structure is smaller than that of the second cell structure, and the switching delay time of the fourth cell structure is smaller than that of the third cell structure.

According to an embodiment of the present disclosure, preferably, the first cell structure includes a first conductive type first substrate, a plurality of first trench gates and a plurality of second trench gates disposed in a surface of the first substrate, and a second conductive type first well region disposed at both sides of each trench gate and a first conductive type first source region located in the surface of the first well region;

the first trench gate is electrically connected with the gate bus, and the second trench gate is electrically connected with the emitter pad;

and the two adjacent first trench gates are isolated by a plurality of second trench gates.

According to an embodiment of the present disclosure, preferably, the second cell structures each include a first conductive type second substrate, a plurality of third trench gates and a plurality of fourth trench gates disposed in a surface of the second substrate, and a second conductive type second well region disposed at both sides of each trench gate and a first conductive type second source region located in a surface of the second well region;

The third trench gate is electrically connected with the gate bus, and the fourth trench gate is electrically connected with the emitter pad;

isolation is carried out between two adjacent third trench gates through a plurality of fourth trench gates;

the number of the fourth trench gates between two adjacent third trench gates is greater than the number of the second trench gates between two adjacent first trench gates.

According to an embodiment of the present disclosure, preferably, the first cell structure includes a first conductive type third substrate, a plurality of fifth trench gates disposed in a surface of the third substrate, and second conductive type third well regions disposed at both sides of each of the fifth trench gates, a first conductive type third source region located in a surface of the third well regions, and a first conductive type first storage region located under the third well regions;

wherein the fifth trench gate is electrically connected to the gate bus.

According to an embodiment of the present disclosure, preferably, the second cell structure includes a first conductive type fourth substrate, a plurality of sixth trench gates disposed in a surface of the fourth substrate, and second conductive type fourth well regions disposed at both sides of each of the sixth trench gates, a first conductive type fourth source region located in the surface of the fourth well region, and a first conductive type second storage region located under the fourth well region;

The sixth trench gate is electrically connected with the gate bus, and the ion doping concentration of the second storage area is smaller than that of the first storage area.

According to an embodiment of the present disclosure, preferably, the first cell structure includes a fifth substrate of a first conductivity type, a plurality of seventh trench gates disposed in a surface of the fifth substrate, and fifth well regions of a second conductivity type disposed at both sides of each of the seventh trench gates, and fifth source regions of the first conductivity type and sixth source regions of the second conductivity type disposed in the surface of the fifth well regions alternately in a longitudinal direction;

wherein the seventh trench gate is electrically connected to the gate bus.

According to an embodiment of the present disclosure, preferably, the second cell structure includes a sixth substrate of a first conductivity type, a plurality of eighth trench gates disposed in a surface of the sixth substrate, and sixth well regions of a second conductivity type disposed at both sides of each of the eighth trench gates, seventh source regions of the first conductivity type and eighth source regions of the second conductivity type disposed in the surface of the sixth well regions alternately in a longitudinal direction;

wherein the eighth trench gate is electrically connected to the gate bus;

A longitudinal width ratio of the seventh source region and the eighth source region is greater than a longitudinal width ratio of the fifth source region and the sixth source region.

By adopting the technical scheme, at least the following technical effects can be achieved:

the present disclosure provides a trench gate IGBT device including a cell region; the cell area comprises a plurality of first cell structures and second cell structures which are alternately arranged, and the switching delay time of the first cell structures is longer than that of the second cell structures; an emitter pad arranged above the cell region and used for being connected with the emitters of the first cell structure and the second cell structure; a gate bus line disposed above the cell region and around the emitter pad, for connecting with trench gates of the first cell structure and the second cell structure; the grid electrode bonding pad is arranged above the cell area and electrically connected with the grid electrode bus and is used for leading out the grid electrode bus; the gate pad is located at a position corresponding to the first cell structure to compensate for delay caused by gate signal transmission. According to the characteristics of the grid electrode bonding pad, the emitter electrode bonding pad and the grid electrode bus, at least two cell structures are arranged in a chip (alternately arranged), and the grid electrode bonding pad is positioned above a first cell structure with larger switching delay time, so that the difference of electrical properties among different cell structures compensates the transmission delay of grid electrode signals in the device, the electrical stress born by each part of the device is more balanced, cell switches at different positions can be synchronous, and the working reliability of the device is enhanced.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

fig. 1 is a schematic diagram of a gate signal transmission equivalent circuit of a conventional trench gate IGBT device;

fig. 2-5 are schematic top-down front views of a trench gate IGBT device according to an exemplary embodiment of the disclosure;

fig. 6-8 are front top schematic views of another trench gate IGBT device shown in an exemplary embodiment of the present disclosure;

fig. 9 is a schematic top-down front view of another trench gate IGBT device shown in an exemplary embodiment of the disclosure;

fig. 10-11 are front top schematic views of another trench gate IGBT device shown in an exemplary embodiment of the present disclosure;

fig. 12 is a schematic top-down front view of another trench gate IGBT device shown in an exemplary embodiment of the disclosure;

fig. 13 to 14 are schematic cross-sectional structures of two cell structures according to an exemplary embodiment of the present disclosure;

fig. 15 to 17 are schematic cross-sectional structures and schematic cross-sectional structures of two other cell structures according to an exemplary embodiment of the present disclosure;

FIG. 18 is a schematic top plan view of two other cell structures shown in an exemplary embodiment of the present disclosure;

in the drawings, wherein like parts are designated by like reference numerals throughout, the drawings are not to scale;

a-a first cell structure; b-a second cell structure; c-third cell structure; d-fourth cell structure; 101-emitter pads; 102-gate bus; 103-gate pads; 201-emitter pads; 202-gate bus; 203-gate pads; 301-emitter pads; 302-gate bus; 303-gate pad; 401-a first substrate; 402-a first buffer layer; 403-a first collector region; 404-a first well region; 405-a first source region; 406-a first trench gate; 407-a second trench gate; 408-a first interlayer dielectric layer; 409-a first emitter; 410-a first collector; 501-a second substrate; 502-a second buffer layer; 503-a second collector region; 504-a second well region; 505-a second source region; 506-a third trench gate; 507-fourth trench gate; 508-a second interlayer dielectric layer; 509-a second emitter; 510-a second collector; 601-a third substrate; 602-a third buffer layer; 603-a third collector region; 604-a third well region; 605-a third source region; 606-fifth trench gate; 607-a first storage area; 608-a third interlayer dielectric layer; 609-third emitter; 610-a third collector; 701-a fourth substrate; 702-a fourth buffer layer; 703-a fourth collector region; 704-a fourth well region; 705-fourth source region; 706-sixth trench gates; 707-a second storage area; 708-fourth interlayer dielectric layer; 709-fourth emitter; 710-fourth collector 805-fifth source region; 807-sixth source region; 806-seventh trench gate; 905-seventh source region; 906-eighth trench gate; 907-eighth source region.

Detailed Description

The embodiments of the present disclosure will be described in detail below with reference to the drawings and examples, so as to solve the technical problem by applying technical means to the present disclosure, and the implementation process for achieving the corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present disclosure and various features in the embodiments may be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

It will be understood that spatially relative terms, such as "above," "located above," "below," "located below," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as connected with another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions illustrated herein, but include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

For a thorough understanding of the present disclosure, detailed structures and steps will be presented in the following description in order to illustrate the technical solutions presented by the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

Example 1

As shown in fig. 2 to 5, the embodiment of the present disclosure provides a trench gate IGBT device including a cell region (not labeled in the drawing), an emitter PAD 101 (emitter PAD), a gate bus 102, and a gate PAD 103 (gate PAD).

The cell area comprises a plurality of first cell structures A and second cell structures B, the first cell structures A and the second cell structures B are alternately arranged along a preset direction, and the switching delay time of the first cell structures A is longer than that of the second cell structures B. As shown in fig. 2 and 3, the preset direction may be the same as the groove direction (the direction indicated by the arrow in the figure); or may be perpendicular to the direction of the trenches as shown in fig. 4 and 5. The static characteristics of the first cell structure a and the second cell structure B are identical.

An emitter PAD 101 (emitter PAD) is disposed above the cell region for connection with the emitters of the first and second cell structures a and B to draw out the emitters of the first and second cell structures a and B.

The gate bus line 102 is disposed above the cell region and around the emitter pad 101, and is used to connect with the trench gates of the first cell structure a and the second cell structure B, so as to lead out the gates of the first cell structure a and the second cell structure B.

To improve the gate turn-on capability, different numbers of emitter pads 101 may be provided, depending on the chip size and the actual requirements, with a gate bus 102 around each emitter pad 101. In this embodiment, a trench gate IGBT device is provided that includes two emitter pads 101.

A gate pad 103 is disposed above the cell region and electrically connected to the gate bus line 102 for extracting the gate bus line 102. Wherein the gate pad 103 is located at a corresponding position of the first cell structure a (cell structure with a larger switching delay time) to compensate for delay caused by gate signal transmission.

The gate pad 103 may be located at an arbitrary position of the emitter pad 101, at a corner of the emitter pad 101 as shown in fig. 2, at an edge center position of the emitter pad 101 as shown in fig. 3, and at a device center position as shown in fig. 5. When the gate pad 103 is located at the center of the device, the gate pad 103 needs to be connected through the gate bus 102 at the middle of the device. Then, the cell layout is set according to the positions of the gate pads 103, so as to ensure that the gate pads 103 are located at the corresponding positions of the first cell structures a.

The external control circuit controls the on and off of the device sequentially through the gate pad 103 and the gate bus 102, and there is a certain difference in electrical performance between different cell structures, such as a switching delay time. However, the present embodiment is not limited to the difference of the switching delay time, and may be parameters such as static conduction voltage drop, dv/dt, di/dt, etc. Different cell structures are selected at different locations of the device depending on the size of the device and the layout of the gate pad 103. Through the optimized cell layout, the difference of electrical properties among different cell structures compensates the transmission delay of the gate signals in the device, so that the distribution of electric stress is more balanced when the device works normally.

The layout of the cell structures in the device is designed according to the transmission path of the gate signal, and when the difference of the switching delay time between the first cell structure a and the second cell structure B is small, the layout manner as shown in fig. 2 to 5 may be adopted, and the partial area close to the gate pad 103 adopts the first cell structure a, and the rest adopts the second cell structure B.

When the switching delay time difference between the first cell structure a and the second cell structure B is large and cannot be matched well with the gate signal transmission delay, the layout manner as shown in fig. 6 to 8 may be adopted, the number of the first cell structures a is 2 or more, and the area of the single first cell structure a and the area of the second cell structure B are small. Fig. 6, 7 and 8 are cell layouts when the gate pad 103 is located at different positions, respectively.

Further, as shown in fig. 9, the first cell structures a and the second cell structures B with smaller densities may be alternately arranged near the gate pad 103, and the first cell structures a and the second cell structures B with larger densities may be alternately arranged far from the gate pad 103. That is, the area of each first cell structure a within the preset range of the gate pad 103 is larger than the area of each first cell structure a outside the preset range. The area of each second cell structure B within the preset range of the gate pad 103 is larger than the area of each second cell structure B outside the preset range.

When the trench gate IGBT device is in a switching state, all parts in the device have the same electric stress. Compared with the existing trench gate IGBT layout, the trench gate IGBT device provided by the embodiment has a stronger safe working area, does not need extra process steps in manufacturing, and only needs to perform cell structure layout in layout design. The static characteristics of the designed cell structure are basically consistent, and only the difference in the switching characteristics is achieved, so that the steady-state and dynamic balanced electric stress distribution of the chip is realized.

The embodiment provides a reverse-conducting IGBT power integration module, which comprises a cell area; the cell area comprises a plurality of first cell structures A and second cell structures B which are alternately arranged, and the switching delay time of the first cell structure A is longer than that of the second cell structure B; a gate pad 103 disposed above the cell region and electrically connected to the gate bus line 102, for extracting the gate bus line 102; wherein the gate pad 103 is located at a corresponding position of the first cell structure a to compensate for delay caused by gate signal transmission. According to the characteristics of the emitter pad 101, the gate bus 102 and the gate pad 103, two cell structures are arranged in a chip (alternately), and the gate pad 103 is positioned above the first cell structure A with larger switching delay time, so that the difference of electrical properties among different cell structures compensates the transmission delay of gate signals in the device, the electrical stress born by each part of the device is more balanced, cell switches at different positions can be synchronous, and the working reliability of the device is enhanced.

Example two

As shown in fig. 10 and 11, on the basis of the first embodiment, the present disclosure provides another trench gate IGBT device including a cell region, an emitter PAD 201 (emitter PAD), a gate bus line 202, and a gate PAD 203 (gate PAD).

The cell area comprises a plurality of first cell structures A and second cell structures B, the first cell structures A and the second cell structures B are alternately arranged along a preset direction, and the switching delay time of the first cell structures A is longer than that of the second cell structures B. As shown in fig. 10, the preset direction may be the same as the groove direction (the direction indicated by the arrow in the figure); or may be perpendicular to the direction of the trench as shown in fig. 11. The static characteristics of the first cell structure a and the second cell structure B are identical.

An emitter PAD 201 (emitter PAD) is disposed over the cell region for connection with the emitters of the first and second cell structures a and B to draw out the emitters of the first and second cell structures a and B.

A gate bus line 202 is disposed above the cell region and around the emitter pad 201 for connection with the trench gates of the first and second cell structures a and B to lead out the gates of the first and second cell structures a and B.

To improve the gate turn-on capability, different numbers of emitter pads 201 may be provided, depending on the chip size and the actual requirements, with a gate bus 202 around each emitter pad 201. In this embodiment, a trench gate IGBT device is provided that includes four emitter pads 201.

A gate pad 203 is disposed above the cell region and electrically connected to the gate bus line 202 for extracting the gate bus line 202. Wherein the gate pad 203 is located at a corresponding position of the first cell structure a (cell structure with a larger switching delay time) to compensate for delay caused by gate signal transmission.

The gate pad 203 may be located at any position of the emitter pad 201, such as at a corner of the emitter pad 201, at an edge center position of the emitter pad 201, or at a device center position, and when the gate pad 203 is located at the device center position, the gate pad 203 is connected through the gate bus line 202 at a device center position. Then, the cell layout is set according to the positions of the gate pads 203, so as to ensure that the gate pads 203 are located at the corresponding positions of the first cell structures a.

The external control circuit controls the on and off of the device sequentially through the gate pad 203 and the gate bus 202, and there is a certain difference in electrical performance between different cell structures, such as a switching delay time. However, the present embodiment is not limited thereto, and may be parameters such as static conduction voltage drop, dv/dt, di/dt, and the like. Different cell structures are selected at different locations of the device depending on the size of the device and the layout of the gate pad 203. Through the optimized cell layout, the difference of electrical properties among different cell structures compensates the transmission delay of the gate signals in the device, so that the distribution of electric stress is more balanced when the device works normally.

In this embodiment, the layout of the cell structures in the device is not limited to the layout shown in fig. 10 and 11, and the layout of the cells can be referred to as the layout in the first embodiment.

The embodiment provides a reverse-conducting IGBT power integration module, which comprises a cell area; the cell area comprises a plurality of first cell structures A and second cell structures B which are alternately arranged, and the switching delay time of the first cell structure A is longer than that of the second cell structure B; a gate pad 203 disposed above the cell region and electrically connected to the gate bus 202, for extracting the gate bus 202; wherein the gate pad 203 is located at a corresponding position of the first cell structure a to compensate for delay caused by gate signal transmission. According to the characteristics of the emitter pad 201, the gate bus 202 and the gate pad 203, two cell structures are arranged in a chip (alternatively), and the gate pad 203 is positioned above the first cell structure A with larger switching delay time, so that the difference of electrical properties among different cell structures compensates the transmission delay of gate signals in the device, the electrical stress born by each part of the device is more balanced, cell switches at different positions can be synchronous, and the working reliability of the device is enhanced.

Example III

As shown in fig. 12, the embodiment of the present disclosure provides a trench gate IGBT device including a cell region, an emitter PAD 301 (emitter PAD), a gate bus 302, and a gate PAD 303 (gate PAD).

The cell area comprises a plurality of first cell structures A, second cell structures B, third cell structures C and fourth cell structures D, wherein the first cell structures A, the second cell structures B, the third cell structures C and the fourth cell structures D are alternately arranged along a preset direction, and the switching delay time of the first cell structures A is greater than the switching delay time of the second cell structures B, the switching delay time of the third cell structures C is greater than the switching delay time of the fourth cell structures D. The preset direction may be the same as the trench direction or may be perpendicular to the trench direction. The static characteristics of the first cell structure A, the second cell structure B, the third cell structure C and the fourth cell structure D are consistent.

An emitter PAD 301 (emitter PAD) is disposed above the cell region and is used to connect with the emitters of the first, second, third and fourth cell structures a, B, C and D to lead out the emitters of the first, second, third and fourth cell structures a, B, C and D.

The gate bus 302 is disposed above the cell region and around the emitter pad 301, and is used to connect with the trench gates of the first, second, third and fourth cell structures a, B, C and D, so as to lead out the gates of the first, second, third and fourth cell structures a, B, C and D.

To improve the gate turn-on capability, different numbers of emitter pads 301 may be provided, depending on the chip size and the actual requirements, with a gate bus 302 around each emitter pad 301. In this embodiment, a trench gate IGBT device is provided that includes two emitter pads 301.

A gate pad 303 is disposed above the cell region and electrically connected to the gate bus line 302 for extracting the gate bus line 302. Wherein the gate pad 303 is located at a corresponding position of the first cell structure a (cell structure with a larger switching delay time) to compensate for delay caused by gate signal transmission.

The gate pad 303 may be located at any position of the emitter pad 301, such as at a corner of the emitter pad 301, at an edge center position of the emitter pad 301, or at a device center position, and when the gate pad 303 is located at the device center position, the gate pad 303 is connected through the gate bus 302 at a device center position. Then, the cell layout is set according to the positions of the gate pads 303, so as to ensure that the gate pads 303 are located at the corresponding positions of the first cell structures a.

The external control circuit controls the on and off of the device through the gate pad 303 and the gate bus 302 in sequence, and there is a certain difference in electrical performance between different cell structures, such as a switching delay time. However, the present embodiment is not limited thereto, and may be parameters such as static conduction voltage drop, dv/dt, di/dt, and the like. Different cell structures are selected at different locations of the device depending on the size of the device and the layout of the gate pads 303. Through the optimized cell layout, the difference of electrical properties among different cell structures compensates the transmission delay of the gate signals in the device, so that the distribution of electric stress is more balanced when the device works normally.

It should be noted that the types of cell structures in the present disclosure are not limited to 2 types and 4 types, and any of cell structures of 2 types or more may be used.

The embodiment provides a reverse-conducting IGBT power integration module, which comprises a cell area; the cell area comprises a plurality of first cell structures A, a second cell structure B, a third cell structure C and a fourth cell structure D which are alternately arranged, wherein the switching delay time of the first cell structure A is longer than that of the second cell structure B, the switching delay time of the second cell structure B is longer than that of the third cell structure C, and the switching delay time of the third cell structure C is longer than that of the fourth cell structure D; a gate pad 303 disposed above the cell region and electrically connected to the gate bus line 302, for extracting the gate bus line 302; wherein the gate pads 303 are located at corresponding positions of the first cell structure a to compensate for delays caused by gate signal transmission. According to the characteristics of the emitter bonding pad 301, the gate bus 302 and the gate bonding pad 303, two cell structures are arranged in a chip (alternatively arranged), and the gate bonding pad 303 is positioned above the first cell structure A with larger switching delay time, so that the difference of electrical properties among different cell structures compensates the transmission delay of gate signals in the device, the electrical stress born by each part of the device is more balanced, cell switches at different positions can be synchronous, and the working reliability of the device is enhanced.

Example IV

As shown in fig. 13 and 14, the present embodiment provides two cell structures, a first cell structure a and a second cell structure B.

As shown in fig. 13, the first cell structure a includes a first substrate 401, a first buffer layer 402, a first collector region 403, a first well region 404, a first source region 405, a first trench gate structure, a second trench gate structure, a first interlayer dielectric layer 408, a first emitter 409, and a first collector 410.

The first substrate 401 is a semiconductor substrate of a first conductivity type.

The first buffer layer 402 is a doped layer of the first conductivity type, and the first buffer layer 402 is located under the first substrate 401.

The first collector region 403 is a doped region of the second conductivity type, and the first collector region 403 is located under the first buffer layer 402.

A plurality of first trench gate structures and second trench gate structures are disposed in the surface of the first substrate 401, where the first trench gate structures include a first trench (not labeled in the figure), a first gate insulating layer (not labeled in the figure) disposed at the bottom and sidewalls of the first trench, and a first trench gate 406 filled in the first trench. The second trench gate structure includes a second trench (not shown), a second gate insulating layer (not shown) disposed at the bottom and sidewalls of the second trench, and a second trench gate 407 filled in the second trench.

The first well region 404 is a well region of the second conductivity type, the first well region 404 is disposed at two sides of each trench gate (between two adjacent trench gates), the first well region 404 is located in the surface of the first substrate 401, the upper surface of the first well region is flush with the upper surface of the first substrate 401, and the depth of the first well region 404 is smaller than the depth of the first trench and the second trench.

The first source region 405 is a source region of a first conductivity type, and is disposed in the surface of the first well region 404, and the upper surface thereof is flush with the upper surface of the first well region 404, and the depth of the first source region 405 is smaller than the depth of the first well region 404.

Both the first trench gate structure (first gate insulating layer in) and the second trench gate structure (second gate insulating layer) are in contact with the first well region 404 and the first source region 405.

A first interlayer dielectric layer 408 is located over the first trench gate structure and the second trench gate structure.

The first emitter 409 is located above the first interlayer dielectric layer 408, and the first emitter 409 is in contact with the first source region 405 and the second trench gate 407 through a contact hole (not shown in the figure), i.e. the second trench gate 407 is electrically connected to an emitter pad of the IGBT device, and is a dummy gate. And the first trench gate 406 is connected to the gate bus line as a true gate (active gate).

The first collector 410 is located below the first collector region 409 and is in contact with the first collector region 409.

As shown in fig. 14, the second cell structure B includes a second substrate 501, a second buffer layer 502, a second collector region 503, a second well region 504, a second source region 505, a third trench gate structure, a fourth trench gate structure, a second interlayer dielectric layer 508, a second emitter 509, and a second collector 510.

The second substrate 501 is a semiconductor substrate of the first conductivity type.

The second buffer layer 502 is a doped layer of the first conductivity type, and the second buffer layer 502 is located under the second substrate 501.

The second collector region 503 is a doped region of a second conductivity type, and the second collector region 503 is located under the second buffer layer 502.

A plurality of third trench gate structures and fourth trench gate structures are disposed in the surface of the second substrate 501, and the third trench gate structures include a third trench (not labeled in the figure), a third gate insulating layer (not labeled in the figure) disposed at the bottom and sidewalls of the third trench, and a third trench gate 506 filled in the third trench. The fourth trench gate structure includes a fourth trench (not shown), a fourth gate insulating layer (not shown) disposed at the bottom and sidewalls of the fourth trench, and a fourth trench gate 507 filled in the fourth trench.

The second well region 504 is a well region of the second conductivity type, the second well region 504 is disposed at two sides of each trench gate, the second well region 504 is located in the surface of the second substrate 501, the upper surface of the second well region 504 is flush with the upper surface of the second substrate 501, and the depth of the second well region 504 is smaller than the depths of the third trench and the fourth trench.

The second source region 505 is a source region of the first conductivity type, and is disposed in the surface of the second well region 504, and the upper surface thereof is flush with the upper surface of the second well region 504, and the depth of the second source region 505 is smaller than the depth of the second well region 504.

The third trench gate structure (the third gate insulating layer in) and the fourth trench gate structure (the fourth gate insulating layer) are both in contact with the second well region 504 and the second source region 505.

A second interlayer dielectric layer 508 is located over the third trench gate structure and the fourth trench gate structure.

The second emitter 509 is located above the second interlayer dielectric layer 508, and the second emitter 509 is in contact with the second source region 505 and the fourth trench gate 507 through a contact hole (not shown in the figure), i.e. the fourth trench gate 507 is electrically connected to an emitter pad of the IGBT device, and is a dummy gate. And the third trench gate 506 is connected to the gate bus line and is a true gate (active gate).

The second collector 510 is located below the second collector region 503 and is in contact with the second collector region 503.

Wherein the number of the fourth trench gates 507 between two adjacent third trench gates 506 in the second cell structure B (e.g., 2 in fig. 14) is greater than the number of the second trench gates 407 between two adjacent first trench gates 406 in the first cell structure a (e.g., 1 in fig. 13).

According to the embodiment, the input and output capacitance of the cell is regulated by regulating the number of the false gates among the true gates, so that the aim of regulating the delay time of switching of the cell is fulfilled.

It should be noted that the static characteristics of the cell structures shown in fig. 13 and 14 are substantially identical: when the chip is in an on state, the channel density is the same, the longitudinal distribution of carrier concentration in the substrate is consistent, namely the on voltage drop under the same current is the same; when the chip is in the blocking state, the electric field distribution in the substrate is the same, i.e. the same blocking voltage.

But the dynamic characteristics of the two cell structures are different. Since the number of the fourth trench gates 507 between the adjacent two third trench gates 506 is greater than the number of the second trench gates 407 between the adjacent two first trench gates 406, the number of the dummy gates between the adjacent true gates in the first cell structure a is smaller than the number of the dummy gates between the adjacent true gates in the second cell structure B, and the input and output capacitances in the first cell structure a are greater than the input and output capacitances of the second cell structure B, the switching delay time of the first cell structure a is greater than that of the second cell structure B.

Correspondingly, the first conductivity type is opposite to the second conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P type, the second conductivity type is N type.

The embodiment provides two cell structures, and the quantity of false gates between true gates in the trench gate IGBT cell structure is regulated and controlled to regulate and control the input and output capacitance of the cells, so that the aim of regulating and controlling the delay time of switching the cells is achieved, and the characteristic difference between different cell schemes is matched with the cell layout.

Example five

As shown in fig. 15, 16 and 17, the present embodiment provides another two cell structures, a first cell structure a and a second cell structure B.

As shown in fig. 15, the first cell structure a includes a third substrate 601, a third buffer layer 602, a third collector region 603, a third well region 604, a third source region 605, a fifth trench gate structure, a first storage region 607, a third interlayer dielectric layer 608, a third emitter 609, and a third collector 610.

The third substrate 601 is a semiconductor substrate of the first conductivity type.

The third buffer layer 602 is a doped layer of the first conductivity type, and the third buffer layer 602 is located under the third substrate 601.

The third collector region 603 is a doped region of the second conductivity type, and the third collector region 603 is located under the third buffer layer 602.

A plurality of fifth trench gate structures are disposed in the surface of the third substrate 601, and the fifth trench gate structures include a fifth trench (not labeled in the figure), a fifth gate insulating layer (not labeled in the figure) disposed at the bottom and sidewalls of the fifth trench, and a fifth trench gate 606 filled in the fifth trench.

The third well region 604 is a well region of the second conductivity type, the third well region 604 is disposed at two sides of each trench gate (between two adjacent trench gates), the third well region 604 is located in the surface of the third substrate 601, the upper surface of the third well region is flush with the upper surface of the third substrate 601, and the depth of the third well region 604 is smaller than the depth of the fifth trench.

The third source region 605 is a source region of the first conductivity type, and is disposed in the surface of the third well region 604, the upper surface of the third source region is flush with the upper surface of the third well region 604, and the depth of the third source region 605 is smaller than the depth of the third well region 604.

The fifth trench gate structure (fifth gate insulating layer in) is in contact with the third well region 604 and the third source region 605.

The first storage region 607 is a doped region of the first conductivity type, and is located under the third well region 604.

A third interlayer dielectric layer 608 is located over the fifth trench gate structure.

The third emitter 609 is located above the third interlayer dielectric layer 608, the third emitter 609 is in contact with the third source region 605 through a contact hole (not shown in the figure), and the fifth trench gate 606 is connected to the gate bus line, and is a true gate (active gate).

The third collector 610 is located below the third collector region 609 and is in contact with the third collector region 609.

As shown in fig. 16, the second cell structure B includes a fourth substrate 701, a fourth buffer layer 702, a fourth collector region 703, a fourth well region 704, a fourth source region 705, a sixth trench gate structure, a second storage region 707, a fourth interlayer dielectric layer 708, a fourth emitter 709, and a fourth collector 710.

The fourth substrate 701 is a semiconductor substrate of the first conductivity type.

The fourth buffer layer 702 is a doped layer of the first conductivity type, and the fourth buffer layer 702 is located under the fourth substrate 701.

The fourth collector region 703 is a doped region of the second conductivity type, and the fourth collector region 703 is located under the fourth buffer layer 702.

A number of sixth trench gate structures are disposed in the surface of the fourth substrate 701, and the sixth trench gate structures include a sixth trench (not labeled in the figure), a sixth gate insulating layer (not labeled in the figure) disposed at the bottom and sidewalls of the sixth trench, and a sixth trench gate 706 filled in the sixth trench.

The fourth well region 704 is a well region of the second conductivity type, the fourth well region 704 is disposed at two sides of each trench gate, the fourth well region 704 is located in the surface of the fourth substrate 701, the upper surface of the fourth well region is flush with the upper surface of the fourth substrate 701, and the depth of the fourth well region 704 is smaller than the depth of the sixth trench.

The fourth source region 705 is a source region of the first conductivity type, and is disposed in the surface of the fourth well region 704, the upper surface of the fourth source region is flush with the upper surface of the fourth well region 704, and the depth of the fourth source region 705 is smaller than the depth of the fourth well region 704.

The sixth trench gate structure (the sixth gate insulating layer in) is in contact with the fourth well region 704 and the fourth source region 705.

The second storage region 707 is a doped region of the first conductivity type, and is located under the fourth well region 704.

A fourth interlayer dielectric layer 708 is located over the sixth trench gate structure.

The fourth emitter 709 is located above the fourth interlayer dielectric layer 708, and the fourth emitter 709 is in contact with the fourth source region 705 through a contact hole (not shown in the drawing). And the sixth trench gate 706 is connected to the gate bus line and is a true gate (active gate).

The fourth collector 710 is located below the fourth collector region 703 and is in contact with the fourth collector region 703.

The ion doping concentration NW2 of the second storage region is smaller than the ion doping concentration NW1 of the first storage region.

According to the embodiment, the input capacitance and the output capacitance of the cell are regulated and controlled through the regulation and control of the ion doping concentration of the storage area, so that the aim of regulating and controlling the delay time of the cell switch is fulfilled.

Since the ion doping concentration NW2 of the second storage region is smaller than the ion doping concentration NW1 of the first storage region, the switching delay time of the first cell structure a is longer than that of the second cell structure B.

For example, the cell layout may be as shown in fig. 17, but is not limited thereto, and specific layouts may be referred to embodiment one to embodiment three.

The embodiment provides two cell structures, and the input capacitance and the output capacitance of the cells are regulated and controlled through the regulation and control of the ion doping concentration of the storage area, so that the aim of regulating and controlling the delay time of the cells is fulfilled, and the characteristic difference between different cell schemes is matched with the cell layout.

Example six

As shown in fig. 18, the present embodiment provides another two cell structures, a first cell structure a and a second cell structure B.

The first unitary structure a includes a fifth substrate, a fifth buffer layer, a fifth collector region, a fifth well region, a fifth source region 805, a sixth source region 807, a seventh trench gate structure, a fifth interlayer dielectric layer, a fifth emitter, and a fifth collector.

To illustrate the positional relationship of the fifth source region 805, the sixth source region 807, fig. 18 shows only the fifth source region 805, the sixth source region 807, and the seventh trench gate 806 in the seventh trench gate structure, and the positions of the other portions can be referred to fig. 15.

The fifth substrate is a semiconductor substrate of the first conductivity type.

The fifth buffer layer is a doped layer of the first conductivity type and is positioned below the fifth substrate.

The fifth collector region is a doped region of the second conductivity type, and is located under the fifth buffer layer.

A plurality of seventh trench gate structures are disposed in the surface of the fifth substrate, and the seventh trench gate structures include a seventh trench (not labeled in the figure), a seventh gate insulating layer (not labeled in the figure) disposed at the bottom and the sidewall of the seventh trench, and a seventh trench gate filled in the seventh trench.

The fifth well region is a well region of the second conductivity type, the fifth well region is arranged on two sides of each trench gate (between two adjacent trench gates), the fifth well region is positioned in the surface of the fifth substrate, the upper surface of the fifth well region is flush with the upper surface of the fifth substrate, and the depth of the fifth well region is smaller than that of the seventh trench.

The fifth source region 805 is a source region of the first conductivity type, the sixth source region 807 is a source region of the second conductivity type, the fifth source region 805 and the sixth source region 807 are alternately arranged longitudinally in the surface of the fifth well region, the upper surface thereof is flush with the upper surface of the fifth well region, and the depths of the fifth source region 805 and the sixth source region 807 are smaller than the depth of the fifth well region.

The seventh trench gate structure (the seventh gate insulating layer in) is in contact with the fifth well region, the fifth source region 805, and the sixth source region 807.

The fifth interlayer dielectric layer is located above the seventh trench gate structure.

The fifth emitter is located above the fifth interlayer dielectric layer, the fifth emitter contacts the fifth source region through a contact hole (not shown in the figure), and the seventh trench gate 806 is connected to the gate bus and is a true gate (active gate).

The fifth collector is located below the fifth collector region and is in contact with the fifth collector region.

The second cell structure B includes a sixth substrate, a sixth buffer layer, a sixth collector region, a sixth well region, a seventh source region 905, an eighth source region 907, an eighth trench gate structure, a sixth interlayer dielectric layer, a sixth emitter, and a sixth collector.

Similarly, fig. 18 shows only the seventh source region 905, the eighth source region 907, and the eighth trench gate 906 in the eighth trench gate structure in order to show the positional relationship of the seventh source region 905 and the eighth source region 907, and the positions of the other portions may be referred to fig. 15.

The sixth substrate is a semiconductor substrate of the first conductivity type.

The sixth buffer layer is a doped layer of the first conductivity type, and is located under the sixth substrate.

The sixth collector region is a doped region of the second conductivity type, and is located under the sixth buffer layer.

The eighth trench gate structures are disposed in the surface of the sixth substrate, and each eighth trench gate structure includes an eighth trench (not labeled in the figure), an eighth gate insulating layer (not labeled in the figure) disposed at the bottom and on the sidewalls of the eighth trench, and an eighth trench gate filled in the eighth trench.

The sixth well region is a well region of the second conductivity type, the sixth well region is arranged at two sides of each trench gate (between two adjacent trench gates), the sixth well region is positioned in the surface of the sixth substrate, the upper surface of the sixth well region is flush with the upper surface of the sixth substrate, and the depth of the sixth well region is smaller than that of the eighth trench.

The seventh source region 905 is a source region of the first conductivity type, the eighth source region 907 is a source region of the second conductivity type, the seventh source region 905 and the eighth source region 907 are alternately arranged in the surface of the sixth well region in the longitudinal direction, the upper surface of the seventh source region 905 and the eighth source region 907 are flush with the upper surface of the sixth well region, and the depth of the seventh source region 905 and the depth of the eighth source region 907 are smaller than the depth of the sixth well region.

The eighth trench gate structure (the eighth gate insulating layer in) is in contact with the sixth well region, the seventh source region 905, and the eighth source region 907.

The sixth interlayer dielectric layer is located above the eighth trench gate structure.

The sixth emitter is located above the sixth interlayer dielectric layer, the sixth emitter contacts the sixth source region through a contact hole (not shown in the figure), and the eighth trench gate is connected to the gate bus and is a true gate (active gate).

The sixth collector is located below the sixth collector region and is in contact with the sixth collector region.

The longitudinal width ratio of the seventh source region and the eighth source region in the second cell structure B is greater than the longitudinal width ratio of the fifth source region and the sixth source region in the first cell structure a.

Illustratively, when the first conductivity type is N-type and the second conductivity type is P-type, the longitudinal width ratio of the seventh source region (n+) to the eighth source region (p+) in the second cell structure B is greater than the longitudinal width ratio of the fifth source region (n+) to the sixth source region (p+) in the first cell structure a.

Therefore, the device can have better current sharing characteristic when in work, wherein the first cell structure A has small current, slow on and fast off, and the second cell structure B has large current, fast on and slow off. The switching delay time of the first cell structure a is greater than that of the second cell structure B.

The embodiment achieves the aim of regulating and controlling the cell switch delay time by regulating and controlling the longitudinal width ratio of the N+ source region and the P+ source region.

The cell layout in this embodiment is not limited to that shown in fig. 18, and reference is made to embodiments one to three for specific layout.

The embodiment provides two cell structures, and the purpose of regulating and controlling the cell switching delay time is achieved through regulating and controlling the longitudinal width ratio of the N+ source region and the P+ source region, so that the characteristic difference between different cell schemes is matched with the cell layout.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. While the embodiments of the present disclosure are described above, the disclosure is not limited to the embodiments employed for the convenience of understanding the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that numerous modifications and variations in form and detail can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is still subject to the scope of the appended claims.

Claims

1. A trench gate IGBT device, comprising:

a cell region; the cell area comprises a plurality of first cell structures and second cell structures which are alternately arranged along a preset direction, and the switching delay time of the first cell structures is longer than that of the second cell structures; the switch delay time is the transmission delay time of the grid signal;

the grid electrode bonding pad is arranged above the cell area and electrically connected with the grid electrode bus and is used for leading out the grid electrode bus; the gate pad is only located at a position corresponding to the first cell structure to compensate for gate signal transmission delay.

2. The trench gate IGBT device of claim 1 wherein the area of each of the first cell structures within a preset range of the gate pad is greater than the area of each of the first cell structures outside the preset range.

3. The trench gate IGBT device of claim 2 wherein the area of each of the second cell structures within the predetermined range of the gate pad is greater than the area of each of the second cell structures outside the predetermined range.

4. The trench gate IGBT device of claim 1 wherein the cell region further comprises a third cell structure and a fourth cell structure;

5. The trench gate IGBT device of claim 1 wherein the first cell structure comprises a first conductivity type first substrate, a number of first trench gates and a number of second trench gates disposed within a surface of the first substrate, and a second conductivity type first well region disposed on both sides of each trench gate and a first conductivity type first source region within a surface of the first well region;

6. The trench gate IGBT device of claim 5 wherein the second cell structures each comprise a first conductivity type second substrate, a number of third trench gates and a number of fourth trench gates disposed within a surface of the second substrate, and a second conductivity type second well region disposed on both sides of each trench gate and a first conductivity type second source region within a surface of the second well region;

7. The trench gate IGBT device of claim 1 wherein the first cell structure comprises a first conductivity type third substrate, a number of fifth trench gates disposed in a surface of the third substrate, and a second conductivity type third well region disposed on both sides of each of the fifth trench gates, a first conductivity type third source region located in a surface of the third well region, and a first conductivity type first storage region located below the third well region;

Wherein the fifth trench gate is electrically connected to the gate bus.

8. The trench gate IGBT device of claim 7 wherein the second cell structure comprises a fourth substrate of the first conductivity type, a number of sixth trench gates disposed in the fourth substrate surface, and a fourth well region of the second conductivity type disposed on either side of each of the sixth trench gates, a fourth source region of the first conductivity type located in the fourth well region surface, and a second storage region of the first conductivity type located below the fourth well region;

9. The trench gate IGBT device of claim 1 wherein the first cell structure comprises a fifth substrate of the first conductivity type, a number of seventh trench gates disposed in a surface of the fifth substrate, and fifth well regions of the second conductivity type disposed on both sides of each of the seventh trench gates, fifth source regions of the first conductivity type and sixth source regions of the second conductivity type disposed longitudinally alternating in a surface of the fifth well regions;

Wherein the seventh trench gate is electrically connected to the gate bus.

10. The trench gate IGBT device of claim 9 wherein the second cell structure comprises a sixth substrate of the first conductivity type, a number of eighth trench gates disposed in the surface of the sixth substrate, and a sixth well region of the second conductivity type disposed on both sides of each of the eighth trench gates, a seventh source region of the first conductivity type and an eighth source region of the second conductivity type disposed longitudinally alternating in the surface of the sixth well region;

wherein the eighth trench gate is electrically connected to the gate bus;