CN103779403A - IGBT chip structure - Google Patents

IGBT chip structure Download PDF

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Publication number
CN103779403A
CN103779403A CN201410033274.0A CN201410033274A CN103779403A CN 103779403 A CN103779403 A CN 103779403A CN 201410033274 A CN201410033274 A CN 201410033274A CN 103779403 A CN103779403 A CN 103779403A
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CN
China
Prior art keywords
chip
grid
igbt
grid bus
gate pads
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Pending
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CN201410033274.0A
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Chinese (zh)
Inventor
红梅
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JIAXING STARPOWER MICROELECTRONICS CO Ltd
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JIAXING STARPOWER MICROELECTRONICS CO Ltd
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Priority to CN201410033274.0A priority Critical patent/CN103779403A/en
Publication of CN103779403A publication Critical patent/CN103779403A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An IGBT chip structure mainly comprises a grid bonding pad, an emitter bonding pad and a grid bus. The IGBT chip structure is characterized in that a layout of an IGBT hip is of a centrally symmetrical structure, and the grid bonding pad is arranged in the center of the front face of the IGBT chip. The grid bus is arranged at the transverse center and the longitudinal center of the chip and is connected with the grid bonding pad at the position of the transverse center and the longitudinal center of the chip. The grid bus is arranged on the periphery of the chip to form an annular shape and connected with the grid bus led out by the grid bonding pad at the position of the transverse center and the longitudinal center of the chip. An emitter is arranged in an area defined by the grid bus and the grid bonding pad, and four emitter bonding pads are symmetrically formed.

Description

A kind of igbt chip structure
Technical field
What the present invention relates to is a kind of igbt chip structure, and especially a kind of igbt chip structure of grid uniform conducting is mainly used in the layout designs of igbt chip.
Background technology
as the main representative of Novel power semiconductor device, IGBT is widely used in industry, information, new forms of energy, medical science, traffic, military affairs and aviation field.At present, the IGBT device on market withstand voltage up to 6500V, single die electric current is up to 200A, and frequency reaches 300KHz.In high-frequency high-power field, also can replace it without any other device at present.Along with the continuous progress of semi-conducting material and processing technology, the current density of IGBT, withstand voltage and frequency constantly get a promotion, and meanwhile also improve constantly for reliability requirement.
When igbt chip area is less be current class hour, require not high for uniform conducting; But for the larger chip of large electric current area, must make grid uniform conducting.Because there is certain pressure drop and parasitic capacitance from gate pads to cellular far away, cause cellular switch asynchronous.In the time that chip is opened, from the first conducting of the cellular close to gate pads, due to the existence of parasitic capacitance dead resistance, even have the situation of not conducting from conducting after the cellular away from gate pads.In the time that chip turn-offs, the cellular close to gate pads first turn-offs, and due to the existence of parasitic capacitance dead resistance, after the cellular away from gate pads, turn-offs the situation about burning out that even has.Inhomogeneous conducting, makes device in reliability, have hidden danger.Therefore the IGBT layout design of grid uniform conducting, improves in reliability and has very important effect for large electric current chip.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of igbt chip structure of grid uniform conducting is provided, it is for the large-area chip of large electric current, can guarantee in chip that each cellular can uniform conducting, improves the reliability of device.
The technical solution used in the present invention is: described igbt chip structure, it mainly comprises gate pads, emitter pad, grid bus, symmetrical structure centered by the laying out pattern of described igbt chip is, described gate pads is arranged at the front central authorities of igbt chip; Grid bus is arranged on chip transverse center, longitudinal center and connects gate pads at chip transverse center, place of longitudinal center; Grid bus is arranged on chip periphery and forms ring-type, and is connected with place of longitudinal center the grid bus that gate pads extracts in chip transverse center; Described emitter be arranged on grid bus and gate pads around region in, and symmetrical output four emitter pads.
Advantage of the present invention is: a kind of IGBT layout design structure of grid uniform conducting is provided, for the large-area chip of large electric current, can guarantees each cellular uniform conducting in chip, improve the reliability of device.
Accompanying drawing explanation
Fig. 1 is a kind of igbt chip layout distribution structure figure of the prior art.
Fig. 2 is another kind of igbt chip layout distribution structure figure of the prior art.
Fig. 3 is igbt chip layout distribution structure figure of the present invention.
embodiment:
Below in conjunction with drawings and Examples, the invention will be further described.IGBT: the abbreviation of insulated gate bipolar transistor, a kind of electric field controls type power device, is generally applied as high-voltage switch gear.Cellular: form the elementary cell of igbt chip, multiple cellulars formation in parallel igbt chip.Gate pads: be connected with the grid of all cellulars in igbt chip by polysilicon, be connected with device external gate terminal pin by lead-in wire.
It shown in Fig. 1, is the typical igbt chip layout distribution structure of one in currently available technology, seen in fig. 1 is the front of igbt chip, comprise gate pads, emitter pad, gate pads is positioned at a jiao of igbt chip layout distribution structure, and emitter pad exists a large amount of cellulars under top layer.Have the IGBT of this kind of layout distribution structure in the time opening, the signal of external circuit is passed to the polysilicon gate of the cellular in chip, the unlatching of each cellular by polysilicon gate control by gate pads; Because the cellular of same igbt chip inside is not exclusively equal from the distance of gate pads, on polysilicon, exist certain voltage to fall, cause the unlatching of each cellular asynchronous.In the use procedure of igbt chip, have certain hidden danger, especially, in the large large-area chip of electric current, this impact is more obvious.
Fig. 2 is another kind of igbt chip layout distribution structure of the prior art, in the front of igbt chip, gate pads is positioned at the middle of chip layout layout structure, this kind of structure applications is in the time of the large large-area igbt chip of electric current, have a shortcoming: the cellular conducting from gate pads close to is very fast, from gate pads away from is that the cellular conducting of chip edge is slower.
Shown in Fig. 3, the present invention mainly comprises: gate pads 1, emitter pad 2, grid bus 3, and symmetrical structure centered by described igbt chip layout distribution structure, described gate pads is arranged at the positive central authorities of igbt chip.Grid bus is arranged on chip transverse center, longitudinal center and connects gate pads at chip transverse center, place of longitudinal center.Grid bus is arranged on chip periphery and forms ring-type, and is connected with place of longitudinal center the grid bus that gate pads extracts in chip transverse center.Described emitter be arranged on grid bus and gate pads around region in symmetrical output four emitter pads.The improvement project that the present invention proposes, in igbt chip layout distribution structure, design adds grid bus, grid bus are arranged on chip transverse center, longitudinal center and connect gate pads at chip transverse center, place of longitudinal center.Grid bus is arranged on chip periphery and forms ring-type, and is connected with place of longitudinal center the grid bus that gate pads extracts in chip transverse center.

Claims (1)

1. an igbt chip structure, it mainly comprises gate pads, emitter pad, grid bus, symmetrical structure centered by the laying out pattern that it is characterized in that described igbt chip is, described gate pads is arranged at the front central authorities of igbt chip; Grid bus is arranged on chip transverse center, longitudinal center and connects gate pads at chip transverse center, place of longitudinal center; Grid bus is arranged on chip periphery and forms ring-type, and is connected with place of longitudinal center the grid bus that gate pads extracts in chip transverse center; Described emitter be arranged on grid bus and gate pads around region in, and symmetrical output four emitter pads.
CN201410033274.0A 2014-01-24 2014-01-24 IGBT chip structure Pending CN103779403A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410033274.0A CN103779403A (en) 2014-01-24 2014-01-24 IGBT chip structure

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Application Number Priority Date Filing Date Title
CN201410033274.0A CN103779403A (en) 2014-01-24 2014-01-24 IGBT chip structure

Publications (1)

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CN103779403A true CN103779403A (en) 2014-05-07

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550567A (en) * 2018-04-16 2018-09-18 全球能源互联网研究院有限公司 A kind of integrated cellular gate resistance layout design of power semiconductor chip
CN111640717A (en) * 2020-05-29 2020-09-08 上海擎茂微电子科技有限公司 Semiconductor power device with high conduction uniformity
CN112687654A (en) * 2020-12-14 2021-04-20 株洲中车时代半导体有限公司 Trench gate IGBT device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4576805B2 (en) * 2002-11-28 2010-11-10 サンケン電気株式会社 Insulated gate semiconductor device and manufacturing method thereof
CN102842610A (en) * 2011-06-22 2012-12-26 中国科学院微电子研究所 Igbt chip and manufacturing method thereof
CN202948448U (en) * 2012-11-08 2013-05-22 中国科学院微电子研究所 IGBT layout
CN203012722U (en) * 2013-01-10 2013-06-19 江苏物联网研究发展中心 IGBT chip layout structure
CN203026511U (en) * 2012-11-08 2013-06-26 中国科学院微电子研究所 IGBT layout
CN203746860U (en) * 2014-01-24 2014-07-30 嘉兴斯达微电子有限公司 IGBT chip structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4576805B2 (en) * 2002-11-28 2010-11-10 サンケン電気株式会社 Insulated gate semiconductor device and manufacturing method thereof
CN102842610A (en) * 2011-06-22 2012-12-26 中国科学院微电子研究所 Igbt chip and manufacturing method thereof
CN202948448U (en) * 2012-11-08 2013-05-22 中国科学院微电子研究所 IGBT layout
CN203026511U (en) * 2012-11-08 2013-06-26 中国科学院微电子研究所 IGBT layout
CN203012722U (en) * 2013-01-10 2013-06-19 江苏物联网研究发展中心 IGBT chip layout structure
CN203746860U (en) * 2014-01-24 2014-07-30 嘉兴斯达微电子有限公司 IGBT chip structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550567A (en) * 2018-04-16 2018-09-18 全球能源互联网研究院有限公司 A kind of integrated cellular gate resistance layout design of power semiconductor chip
CN111640717A (en) * 2020-05-29 2020-09-08 上海擎茂微电子科技有限公司 Semiconductor power device with high conduction uniformity
CN112687654A (en) * 2020-12-14 2021-04-20 株洲中车时代半导体有限公司 Trench gate IGBT device
CN112687654B (en) * 2020-12-14 2024-02-23 株洲中车时代半导体有限公司 Trench gate IGBT device

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Application publication date: 20140507

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