CN206388707U - Domain structure for taking into account IGBT short-circuit capacities and switching speed - Google Patents
Domain structure for taking into account IGBT short-circuit capacities and switching speed Download PDFInfo
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- CN206388707U CN206388707U CN201720012858.9U CN201720012858U CN206388707U CN 206388707 U CN206388707 U CN 206388707U CN 201720012858 U CN201720012858 U CN 201720012858U CN 206388707 U CN206388707 U CN 206388707U
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- bottom plate
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Abstract
The utility model be related to it is a kind of be used for take into account IGBT short-circuit capacities and the domain structure of switching speed, it include chip layout bottom plate, grid runway, first grid groove, second grid groove and grid；Grid runway is deposited with the upper surface of chip layout bottom plate, grid runway is connected with grid, some first grid grooves are offered in the upper surface of chip layout bottom plate, the upper surface of chip layout bottom plate between each two first grid groove offers second grid groove, and first grid groove is in the setting that is connected with grid runway, second grid groove is set in floating, and first grid groove is respectively positioned on inside grid runway with second grid groove.The utility model can effectively reduce input capacitance and miller capacitance as caused by middle groove, so as to improve devices switch speed, reduce switching loss, frequency range can be used in increase device, simultaneously because effective coverage is constant, the saturation voltage drop of device is simultaneously unaffected.
Description
Technical field
The utility model is related to a kind of domain structure, and the utility model is used to take into account the short-circuit energy of IGBT more particularly, to one kind
The domain structure of power and switching speed.
Background technology
Prior art can increase dummy regions to improve shorted devices ability（Without electron channel region）, it is wide
Dummy areas may cause occur warpage during chip manufacture, in order to avoid warpage, can add groove in dummy areas, groove
Increase can cause the increase of input capacitance, and then influence switching speed.The utility model is by making the groove in dummy areas not connect grid
Pole runway, so as to realize the reduction of input capacitance and miller capacitance, and then improves switching speed, frequency model can be used in increase device
Enclose.
Existing structure can increase dummy regions, wide dummy areas may cause chip manufacture to improve short-circuit capacity
During occur warpage, in order to avoid warpage, groove can be added in dummy areas, the increase of groove can cause the increasing of input capacitance
Greatly, switching speed is influenceed.
For in the domain structure of prior art, three gate trench connect grid runway, positioned at middle gate trench
Main function be improve grooved surface in distributing homogeneity, so as to effectively prevent warpage during chip manufacture.
The content of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art effectively to be reduced by centre there is provided one kind
Input capacitance caused by groove and miller capacitance, improve devices switch speed, reduction switching loss be used for take into account IGBT short circuits
The domain structure of ability and switching speed.
The technical scheme provided according to the utility model, it is described to be used to take into account IGBT short-circuit capacities and the domain of switching speed
Structure, it includes chip layout bottom plate, grid runway, first grid groove, second grid groove and grid；In chip layout bottom plate
Upper surface is deposited with grid runway, and grid runway is connected with grid, and some first are offered in the upper surface of chip layout bottom plate
Grid groove, the upper surface of the chip layout bottom plate between each two first grid groove offers second grid groove, and the first grid
Pole groove is with grid runway in the setting that is connected, and second grid groove is set in floating, and first grid groove and the equal position of second grid groove
Inside grid runway.
The first grid groove is equal with the width of second grid groove, and the length direction and second grid of first grid groove
The length direction of groove is set in parallel, and second grid groove is equal with the distance between two first grid grooves, first grid groove
The length direction of length direction and grid runway is vertical setting.
The utility model can effectively reduce input capacitance and miller capacitance as caused by dummy region trenches, so as to carry
High devices switch speed, reduces switching loss, and frequency range can be used in increase device.
Brief description of the drawings
Fig. 1 is structural representation of the present utility model.
Embodiment
With reference to specific embodiment, the utility model is described in further detail.
This is used to take into account IGBT short-circuit capacities and the domain structure of switching speed, and it includes chip layout bottom plate 1, grid and run
Road 2, first grid groove 3, second grid groove 4 and grid 5；Grid runway 2, grid are deposited with the upper surface of chip layout bottom plate 1
Pole runway 2 is connected with grid 5（I.e. grid runway 2 is ultimately connected to grid 5）, offered in the upper surface of chip layout bottom plate 1
Some first grid grooves 3, the upper surface of the chip layout bottom plate 1 between each two first grid groove 3 offers second grid
Groove 4, and first grid groove 3 is in the setting that is connected with grid runway 2, second grid groove 4 is set in floating, and first grid groove 3
It is respectively positioned on second grid groove 4 inside grid runway 2.
The first grid groove 3 is equal with the width of second grid groove 4, and the length direction of first grid groove 3 and second
The length direction of grid groove 4 is set in parallel, equal, the first grid of the distance between second grid groove 4 and two first grid grooves 3
The length direction of the length direction of pole groove 3 and grid runway 2 is vertical setting.
The material of the grid runway 2 is polysilicon.
Second grid groove 4 and its both sides half domain form two points of dummy areas, first grid groove 3 and its both sides
One of region form effective conduction region.
In the utility model, second grid groove 4 is located between two first grid grooves 3, and second grid groove 4 does not connect grid race
Road 2, can effectively reduce input capacitance and miller capacitance as caused by second grid groove 4, so as to improve devices switch speed, drop
Frequency range can be used in low switching losses, increase device, simultaneously because effective coverage is constant, the saturation voltage drop of device is not by shadow
Ring.
Claims (2)
1. a kind of be used to take into account IGBT short-circuit capacities and the domain structure of switching speed, it is characterized in that：It includes chip layout bottom
Plate（1）, grid runway（2）, first grid groove（3）, second grid groove（4）With grid（5）；In chip layout bottom plate（1）It is upper
Surface deposition has grid runway（2）, grid runway（2）With grid（5）It is connected, in chip layout bottom plate（1）Upper surface open up
There are some first grid grooves（3）, in each two first grid groove（3）Between chip layout bottom plate（1）Upper surface offer
Second grid groove（4）, and first grid groove（3）With grid runway（2）Set in connected, second grid groove（4）Set in floating
Put, and first grid groove（3）With second grid groove（4）It is respectively positioned on grid runway（2）It is internal.
2. as claimed in claim 1 be used to take into account IGBT short-circuit capacities and the domain structure of switching speed, it is characterized in that：It is described
First grid groove（3）With second grid groove（4）Width it is equal, and first grid groove（3）Length direction and second grid groove
（4）Length direction be set in parallel, second grid groove（4）With two first grid grooves（3）The distance between equal, the first grid
Pole groove（3）Length direction and grid runway（2）Length direction be vertical setting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720012858.9U CN206388707U (en) | 2017-01-05 | 2017-01-05 | Domain structure for taking into account IGBT short-circuit capacities and switching speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720012858.9U CN206388707U (en) | 2017-01-05 | 2017-01-05 | Domain structure for taking into account IGBT short-circuit capacities and switching speed |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206388707U true CN206388707U (en) | 2017-08-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720012858.9U Active CN206388707U (en) | 2017-01-05 | 2017-01-05 | Domain structure for taking into account IGBT short-circuit capacities and switching speed |
Country Status (1)
| Country | Link |
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| CN (1) | CN206388707U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783977A (en) * | 2017-01-05 | 2017-05-31 | 江苏中科君芯科技有限公司 | Domain structure for taking into account IGBT short-circuit capacities and switching speed |
-
2017
- 2017-01-05 CN CN201720012858.9U patent/CN206388707U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783977A (en) * | 2017-01-05 | 2017-05-31 | 江苏中科君芯科技有限公司 | Domain structure for taking into account IGBT short-circuit capacities and switching speed |
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