CN105655386A - Super-junction device - Google Patents
Super-junction device Download PDFInfo
- Publication number
- CN105655386A CN105655386A CN201610064238.XA CN201610064238A CN105655386A CN 105655386 A CN105655386 A CN 105655386A CN 201610064238 A CN201610064238 A CN 201610064238A CN 105655386 A CN105655386 A CN 105655386A
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- Prior art keywords
- post
- well
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- wells
- pillars
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- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 abstract 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a super-junction device. P pillars and P wells are arranged in an N-type epitaxy; P pillars are in the form of parallel slots; an area between the P wells is arranged as a JFET area; a grid is arranged on the surface of the epitaxy between the P wells; the grid is parallel to the P pillar slots; P pillars and P wells are not in contact with each other in the epitaxy and are spaced for a certain distance; the P wells are grounded through a source region; the P pillars are connected with the P wells through resistors. According to the super-junction device, the P pillars are connected with the P wells by introducing the resistors, the potential difference of the epitaxy of P pillars and P wells is reduced, the time of P pillars being fully reverse exhausted is reduced, the cut-off turn-off time of the device is delayed and the purpose of adjusting the switching characteristic of the device is achieved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of super-junction device.
Background technology
Super junction power device be one quickly grow, widely used Novel power semiconductor. It is on the basis of double-diffused metal oxide semiconductor (DMOS), by introducing super junction (SuperJunction) structure, except possessing that DMOS input impedance is high, switching speed is fast, operating frequency is high, except thermally-stabilised good, the feature such as drive circuit simple, is easily integrated, also overcome the conducting resistance of DMOS along with breakdown potential and be pressed into the shortcoming that 2.5 power relations increase. Current super junction DMOS is widely used to the power supply towards PC, notebook computer, net book, mobile phone, illumination (high-voltage gas discharging light) product and the consumption electronic product such as television set (liquid crystal or plasma TV) and game machine or adapter.
The preparation technology of current super junction power device is largely divided into two big classes, and a kind of is that the mode utilizing repeatedly extension and injection forms P post in N-type epitaxial substrate; Another is that the mode filled at the deep plough groove etched P of adding post is formed.
Existing shallow/deep groove type super-junction device, as it is shown in figure 1, have P post at substrate or outer Yanzhong, is p-well on P post, and P post is positioned at the center of p-well and forms the symmetrical state of a kind of balance. It is JFET region between p-well, is grid between p-well on extension. Fig. 2 is the top view of device. In order to reduce conducting resistance further, it is necessary to more low-resistance epitaxial substrate, simultaneously in order to keep breakdown voltage not decline, it is necessary to the spacing of deep trouth is constantly shortened, ensures that depletion region can be fully deployed between groove.
As shown in Figure 2, it is shown that super-junction device when reversely ending, depletion region launch state. Shallow/deep groove type super junction product, the switching speed of the relatively conventional VDMOSFET of switching speed to be substantially reduced, and is primarily due to the introducing of P rod structure, causes that depletion region development distance to be relatively greatly shortened by VDMOSFET. Switching speed inconsistent, causes super junction product in some applications, due to switching speed and not mating of system, current oscillation can occur, and produces the problems such as EMI variation. Fig. 3 is the simple and easy schematic diagram of tradition VDMOSFET, and when reversely ending, the distance that depletion region launches is as shown in Figure 4. Fig. 5 is Crss-Coss (reverse transfer capacitance-output capacitance) capacitance curve of super-junction device, it can be seen that when in leakage, voltage is less than 50V, P post and N-type epitaxial region are completely depleted, and device reaches cut-off state.Relative VDMOSFET product, super-junction device reaches the N-type extension complete depletion of time will soon nearly more than one times, namely the turn-off time also want fast again more than.
Summary of the invention
The technical problem to be solved is to provide a kind of super-junction device, and its switching speed is adjustable.
For solving the problems referred to above, the present invention provides a kind of super-junction device, has P post and p-well in the outer Yanzhong of N-type, and P post is parallel groove type; Region between p-well is JFET region, and the epitaxial surface between p-well has grid, and described grid is parallel with P post channel; Described P post and p-well Yanzhong outside are not in contact with each other, and are spaced a distance, and p-well is between P post; P-well passes through source region ground connection, and P post is connected by resistance with p-well.
Further, described p-well and P post are not in contact with each other, and are by increasing the distance between P post and p-well, or increase spacer medium between P post and p-well.
Further, described p-well directly contacts connection with source region.
The present invention adopts P post channel physically to separate with p-well, introduce resistance to be connected with p-well by P post, reduce P post and the electric potential difference of N-type extension, delayed P post to reach to be completely reversed the time exhausted, it is delayed the cut-off turn-off time of device, reaches the purpose of adjusting means switching characteristic. By the selection to resistance R size, it is possible to adjust complete depletion of time delay, accurately control switch time.
Accompanying drawing explanation
Fig. 1 is the profile of existing super-junction device.
Fig. 2 be super-junction device when reversely ending depletion region launch schematic diagram.
Fig. 3 is the generalized section of VDMOSFET.
Fig. 4 be VDMOSFET when reversely ending depletion region launch schematic diagram.
Fig. 5 is super-junction device Crss-Coss capacitance curve.
Fig. 6 is the structural representation of device of the present invention.
Description of reference numerals
1 is substrate or extension, and 2 is p-well, and 3 is P post, and 4 is grid.
Detailed description of the invention
The present invention provides a kind of super-junction device, as shown in Figure 6, has P post 3 and p-well 2, P post 3 in parallel groove type in N-type extension 1; Region between p-well 2 is JFET region, and the epitaxial surface between p-well 2 has grid 4, and described grid 4 is parallel with P post 3 groove; Described P post 3 is not in contact with each other in extension 1 with p-well 2, is spaced a distance, and p-well 2 directly contacts connection and by source region ground connection with source region, P post 3 is connected by resistance R with p-well 2, selection to resistance R size, it is possible to adjust complete depletion of time delay, accurately control switch time. Described p-well 2 is not in contact with each other with P post 3, it is possible to by increasing the distance between P post 3 and p-well 2, or increase spacer medium realizes between P post 3 and p-well 2.
The present invention adopts P post channel physically separating with p-well, and p-well is connected with zero potential by source region. P post is then electrically connected with p-well by resistance R, and by the dividing potential drop effect of resistance, thus it is possible to vary the relative potentials of P post and p-well, before P post does not have completely depleted expansion, the electromotive force of P post will lower than p-well electromotive force. And the degree of exhaustion of P post is relevant to the electric potential difference of P post and type N extension, if according to original structure, need between P post and N-type extension to be added to voltage V, P post and N-type extension just can be made completely depleted, and in present configuration, then need to be added to higher voltage in N-type extension, make after deducting the ohmically back-pressure of R, when the electric potential difference of P post and N-type extension reaches V, could be completely depleted, namely extend the turn-off time of device. By the selection to resistance R size, it is possible to adjust complete depletion of time delay, accurately control switch time.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention. For a person skilled in the art, the present invention can have various modifications and variations. All within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (3)
1. a super-junction device, has P post and p-well in the outer Yanzhong of N-type, and P post is parallel groove type; Region between p-well is JFET region, and the epitaxial surface between p-well has grid, and described grid is parallel with P post channel; It is characterized in that: described P post and p-well Yanzhong outside are not in contact with each other, and are spaced a distance, and p-well is between P post; P-well passes through source region ground connection, and P post is connected by resistance with p-well.
2. super-junction device as claimed in claim 1, it is characterised in that: described p-well and P post are not in contact with each other, and are by increasing the distance between P post and p-well, or increase spacer medium between P post and p-well.
3. super-junction device as claimed in claim 1, it is characterised in that: described p-well directly contacts connection with source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610064238.XA CN105655386A (en) | 2016-01-29 | 2016-01-29 | Super-junction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610064238.XA CN105655386A (en) | 2016-01-29 | 2016-01-29 | Super-junction device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105655386A true CN105655386A (en) | 2016-06-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610064238.XA Pending CN105655386A (en) | 2016-01-29 | 2016-01-29 | Super-junction device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105655386A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847920A (en) * | 2017-01-12 | 2017-06-13 | 中国科学院微电子研究所 | A kind of superjunction devices |
| CN108269858A (en) * | 2017-01-04 | 2018-07-10 | 深圳尚阳通科技有限公司 | A kind of super-junction device, chip and its manufacturing method |
-
2016
- 2016-01-29 CN CN201610064238.XA patent/CN105655386A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108269858A (en) * | 2017-01-04 | 2018-07-10 | 深圳尚阳通科技有限公司 | A kind of super-junction device, chip and its manufacturing method |
| CN106847920A (en) * | 2017-01-12 | 2017-06-13 | 中国科学院微电子研究所 | A kind of superjunction devices |
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Application publication date: 20160608 |