CN106449741B - A kind of insulated-gate bipolar transistor device structure - Google Patents
A kind of insulated-gate bipolar transistor device structure Download PDFInfo
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- CN106449741B CN106449741B CN201510477924.5A CN201510477924A CN106449741B CN 106449741 B CN106449741 B CN 106449741B CN 201510477924 A CN201510477924 A CN 201510477924A CN 106449741 B CN106449741 B CN 106449741B
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 230000005611 electricity Effects 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000005265 energy consumption Methods 0.000 description 7
- 230000005516 deep trap Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010992 reflux Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Abstract
A kind of insulated-gate bipolar transistor device structure, top includes active primitive unit cell and virtual primitive unit cell, active primitive unit cell is made of two adjacent active grooves and its adjacent semiconductor layers, the right and left of active primitive unit cell is all virtual primitive unit cell, virtual primitive unit cell includes virtual groove, virtual primitive unit cell is using virtual groove as boundary, all at least penetrating component CS layers of all grooves and part N- drift layer；Top device includes three kinds of p-type base areas, the first p-type base area is located in active primitive unit cell region, but is not present between two active grooves, is additionally provided with N+ emitter region and the contact zone P+ above, and be connected with metal emitting by the window in dielectric layer；Second of p-type base area is located between two active grooves in active primitive unit cell region, and is all that current potential is hanging；The third p-type base area is located in virtual primitive unit cell region.
Description
Technical field
The invention belongs to power semiconductor device technology field, be related to MOS (Metal-Oxide-Semiconductor,
Metal-oxide semiconductor (MOS)) grid-control bipolar device more particularly to insulated gate bipolar transistor (IGBT).
Background technique
Not only power is high for mos gate controlled bipolar device, and can be controlled with small signal.IGBT structure design is a variety of more
Sample, wherein the structure with virtual primitive unit cell region (dummy cell) is more commonly used (referring to for example, United States Patent (USP)
8633510, hereinafter referred to as " patent document 1 ").
Typical case's IGBT structure described in patent document 1 is as shown in Figure 1.The structure include: the back side metal collector 13,
P-type collector 12, N-type field stop layer 11 and the drift region N- 10.It include active primitive unit cell and virtual primitive unit cell at the top of transistor.Active original
Born of the same parents and virtual primitive unit cell are separated by trench gate.Trench gate structure is by the polygate electrodes 6 to contact with each other and 9 groups of gate oxide
At.Active primitive unit cell includes N+ emitter region 1 and the contact zone P+ 2, they are connected by the window of dielectric layer 4 with metal emitting 5.Have
P type trap zone 7 in the primitive unit cell of source is connected by the contact zone P+ 2 with emitter electrode.Also have below P type trap zone in active primitive unit cell
There is N-type CS (carrier stored, carrier storage) layer 8.Virtual primitive unit cell includes p-type deep trap 19.P-type deep trap 19 is got along well any
Electrode is connected, and current potential is hanging.
Fig. 1 structure is characterized in that the p-type deep trap 19 of virtual primitive unit cell, and benefit is can to reduce gate capacitance.But it is this
The gate capacitance of structure is still not small enough.Therefore it turns off energy consumption and turn-off delay time is still bigger.
Thus, it is necessary to improve this IGBT structure, gate capacitance is reduced, reduces shutdown energy consumption and turn-off delay time.
Summary of the invention
For the above-mentioned problems in the prior art, the present invention provides a kind of semiconductor device structure, can reduce
Gate capacitance reduces shutdown energy consumption and turn-off delay time.And it can be applied in all mos gate controlled bipolar devices,
Including but not limited to, field terminates IGBT Field-Stop IGBT, inverse conductivity type IGBT reverse-conducting IGBT, inverse
Resistance type IGBT reverse-blocking IGBT and mos gate control thyristor MOS-controlled thyristor etc..
Specifically, the invention adopts the following technical scheme:
A kind of insulated-gate bipolar transistor device structure, have the back side and front, the device since the back side successively
It include: to be leaned in the drift region N- 10 including metal collector 13, p-type collector 12, N-type field stop layer 11 and the drift region N- 10
Nearly positive part is provided with N-type CS layer 8, and top device includes active primitive unit cell 40 and virtual primitive unit cell 51,52 two kind of region, wherein
Active 40 two sides of primitive unit cell are arranged in virtual primitive unit cell 51,52 and the relative position of basis and active primitive unit cell 40 is referred to as left virtual former respectively
Born of the same parents 51 and right virtual primitive unit cell 51, it is characterised in that: there are two a grooves that active primitive unit cell 40 is included and the two grooves are
Adjacent, they are referred to as active groove 37；The groove structure of active groove 37 is by the active groove polysilicon 6 and grid that contact with each other
Oxide layer 9 forms, and wherein active groove polysilicon 6 is connected with gate electrode 30；Active primitive unit cell region 40 is by the two active grooves
It 37 and is formed with the close adjacent semiconductor layer of active groove 37, the right and left of active primitive unit cell 40 is all virtual primitive unit cell
51,52, the groove that virtual primitive unit cell 51,52 is included is referred to as virtual groove 38；The groove structure of virtual groove 38 is by phase mutual connection
The virtual trench polisilicon 3 and gate oxide 9 of touching form, wherein virtual trench polisilicon 3 is connected with emitter electrode；It is virtual former
With virtual groove 38 for its boundary, all grooves all at least break through part CS layer 8 and part N- drift layer in born of the same parents region 51,52
10；Top device further includes three kinds of p-type base areas, they are all located at the top of CS layer 8；The first p-type base area 7a is located at active original
It in born of the same parents region 40, but is not present between two active grooves 37, is additionally provided with N+ emitter region 1 and P above the 7a of the first p-type base area
+ contact zone 2, and be connected by the window 20 in dielectric layer with metal emitting 5；Second of p-type base area 7b is located at active original
It between two active grooves 37 in born of the same parents region 40, and is all that current potential is hanging；The third p-type base area 7c is located at virtual primitive unit cell
In region 51,52.
Preferably, second of p-type base area 7b, which can be, continuously can also be divided into discontinuous knot by the drift region N- 10
Structure, the third p-type base area 7c can be can also be continuously divided into discontinuous structure, and the third by the drift region N- 10
One or more of p-type base area 7c or entirely current potential are hanging, or are connected with emitter electrode.
Preferably, above second of p-type base area 7b and/or the third p-type base area 7c also comprising the contact zone P+ 2 or comprising
Both N+ emitter region 1 and the contact zone P+ 2.
It preferably, include also the region N+ 14 in p-type collector 12, thus replace part p-type collector 12, the region N+ 14
Upper end and N-type field stop layer 11 are in contact, and the lower end in the region N+ 14 and are in contact with metal collector 13.
In addition, the number of grooves that left virtual primitive unit cell region 51 and right virtual primitive unit cell region 52 are included can be equal, it can also
With unequal.
Further, the ratio for the number of grooves that the virtual primitive unit cell region 51,52 of active primitive unit cell 40 and left and right is included is variable
's.
In above-described insulated-gate bipolar transistor device structure, used semiconductor material is silicon, carbonization
Silicon, gallium nitride.
Invention additionally discloses another insulated-gate bipolar transistor device structures, have the back side and front, the device
It successively include: including metal collector 13, p-type collector 12, the drift region N- 10 and N-type CS layer 8 since the back side, top includes
Active primitive unit cell 40 and virtual primitive unit cell 51,52 two kind of region, it is characterised in that: the groove that active primitive unit cell 40 is included only there are two and
And the two grooves be it is adjacent, they are referred to as active groove 37；The groove structure of active groove 37 is active by what is contacted with each other
Trench polisilicon 6 and gate oxide 9 form, and wherein active groove polysilicon 6 is connected with gate electrode 30；Active primitive unit cell region 40 by
It the two active grooves 37 and is formed with the close adjacent semiconductor layer of active groove 37, the right and left of active primitive unit cell 40
It is all virtual primitive unit cell 51,52, wherein the virtual primitive unit cell 51,52 of this right and left is according to the relative position point with active primitive unit cell 40
Not Bei Chengwei left virtual primitive unit cell 51 and right virtual primitive unit cell 51, the groove that virtual primitive unit cell 51,52 is included be referred to as virtual groove 38；
The groove structure of virtual groove 38 is made of the virtual trench polisilicon 3 and gate oxide 9 to contact with each other, wherein virtual groove is more
Crystal silicon 3 is connected with emitter electrode；With virtual groove 38 for its boundary, all grooves are all at least worn in virtual primitive unit cell region 51,52
Part CS layer 8 and part N- drift layer 10 thoroughly；Top device further includes three kinds of p-type base areas being formed simultaneously, they are all located at
The top of CS layer 8；The first p-type base area 7a is located in active primitive unit cell region 40, but is not present between two active grooves 37；
Second of p-type base area 7b, which can be, is continuously also possible to discontinuous, two active ditches in active primitive unit cell region 40
Between slot 37；The third p-type base area 7c can be continuously be also possible to it is discontinuous, be located at virtual primitive unit cell region 51,52 in；
It is additionally provided with N+ emitter region 1 and the contact zone P+ 2 above the 7a of the first p-type base area, and passes through the window 20 and metal hair in dielectric layer
Emitter-base bandgap grading 5 is connected；Second of p-type base area 7b is that current potential is hanging；The third each p-type base area 7c or be that current potential is hanging
Or be connected with emitter electrode；The p-type ring 15 that the positive drift region N- has multiple current potentials hanging, the p-type collector at the back side
12 extend to front upwards.
The beneficial effects of the present invention are:
Gate capacitance, shutdown energy consumption and the turn-off delay time ratio Fig. 1 structure of device of the present invention significantly reduce.
Detailed description of the invention
Fig. 1 is a kind of traditional IGBT structure figure；
Fig. 2 is a kind of example device junction composition of the invention；
Fig. 3 is a kind of example device junction composition of the invention；
Fig. 4 is a kind of example device junction composition of the invention；
Fig. 5 is a kind of example device junction composition of the invention；
Fig. 6 is a kind of example device junction composition of the invention；
Fig. 7 is a kind of example device junction composition of the invention；
Fig. 8 is a kind of example device junction composition of the invention；
Fig. 9 is a kind of example device junction composition of the invention；
Figure 10 is the miller capacitance comparison diagram of two kinds of IGBT structures (Fig. 1 and Fig. 2 structure)；
Figure 11 is the switching circuit for testing；
Figure 12 is the shutdown waveform of two kinds of IGBT structures (Fig. 1 and Fig. 2 structure).
In figure: 1, N+ emitter region；2, the contact zone P+；3, virtual trench polisilicon；4, dielectric layer；5, metal emitting；
6, active groove polysilicon；7, P type trap zone；7a, the first p-type base area；7b, second of p-type base area；7c, the third p-type base
Area；8, N-type CS layers；9, gate oxide；10, the drift region N-；11, N-type field stop layer；12, p-type collector；13, metal current collection
Pole；14, the region N+；15, p-type ring；19, p-type deep trap；20, window；30, gate electrode；37, active groove；38, virtual groove；
40, active primitive unit cell；51, left virtual primitive unit cell；52, right virtual primitive unit cell.
Specific embodiment
The present invention solves the above-mentioned problems in the prior art using a kind of new structure.
Structure of the invention specifically:
A kind of semiconductor devices, including metal collector, p-type collector, N-type field stop layer, the drift region N- and N-type CS
Layer, top includes two kinds of regions of active primitive unit cell and virtual primitive unit cell, in which: there are two a grooves that active primitive unit cell is included and this
Two grooves be it is adjacent, they are referred to as active groove；The groove structure of active groove is by the polysilicon and grid oxygen that contact with each other
Change layer composition, polysilicon is connected with gate electrode；Active primitive unit cell region is close by the two active grooves and with active groove
Adjacent semiconductor layer is formed, and the right and left of active primitive unit cell is all virtual primitive unit cell, and the groove that virtual primitive unit cell is included is claimed
For virtual groove；The groove structure of virtual groove is made of the polysilicon and gate oxide to contact with each other, polysilicon and transmitting
Pole electrode is connected；With virtual groove for its boundary, all grooves all at least break through part CS layers and part in virtual primitive unit cell region
N- drift layer；Top device further includes three kinds of p-type base areas, they are all located at CS layers of top；The first p-type base area is continuous
, it is located in active primitive unit cell region, but be not present between two active grooves；Second of p-type base area be it is continuous, positioned at having
Between two active grooves in the primitive unit cell region of source；The third p-type base area is continuously, to be located in virtual primitive unit cell region；Three kinds of P
N+ emitter region and the contact zone P+ are designed with above type base area, the N+ emitter region above the first p-type base area and the third p-type base area
Be connected by the window in dielectric layer with metal emitting with the contact zone P+, second of p-type base area and its above N+ transmitting
Area and the contact zone P+ are that current potential is hanging.
As a further improvement of the present invention, N+ emitter region and the contact zone P+ can be not provided with above second of p-type base area；
It can be not provided with N+ emitter region above the third p-type base area, the contact zone P+ above can extend.
As a further improvement of the present invention, the contact zone P+ can be not provided with above the third p-type base area.
As a further improvement of the present invention, the third p-type base area can be hanging with current potential.
As a further improvement of the present invention, the third p-type base area can be discontinuous, the third p-type base area Yan Gou
The direction of slot is divided into discontinuous region by the drift region N-；The third each p-type base area region otherwise current potential it is hanging or and
Emitter is connected.
As a further improvement of the present invention, second of p-type base area can be discontinuous, second of p-type base area Yan Gou
The direction of slot is divided into discontinuous region by the drift region N-, and each second of p-type base area is that current potential is hanging.
As a further improvement of the present invention, the region N+ can be inserted in p-type collector region, the upper end in the region N+ and
It is in contact, the lower end in the region N+ and is in contact with metal collector with N-type field stop layer.
As a further improvement of the present invention, N-type field stop layer is entirely eliminated, the p-type that front has multiple current potentials hanging
The collector of ring, the back side extends to front upwards.
As a further improvement of the present invention, it positioned at two virtual primitive unit cell regions of active primitive unit cell the right and left, is wrapped
The number of grooves contained can be equal, can also be unequal.
As a further improvement of the present invention, the number of grooves ratio that active primitive unit cell and insertion primitive unit cell region are included is can
Become, can be determined according to design requirement.
As a further improvement of the present invention, used semiconductor material is silicon, silicon carbide, gallium nitride.
As a further improvement of the present invention, N-type field stop layer is entirely eliminated, the p-type that front has multiple current potentials hanging
The collector of ring, the back side extends to front upwards.
The present invention is described in further detail below in conjunction with the accompanying drawings.
The first example of the invention is as shown in Figure 2: the device successively includes: metal collector 13, P since the back side
Type collector 12, N-type field stop layer 11 and the drift region N- 10 are provided with CS layer 8 close to positive part in the drift region N- 10,
Top device includes active primitive unit cell 40 and virtual primitive unit cell 51,52 two kind of region.Active primitive unit cell 40 includes two adjacent grooves 37,
Hereinafter referred to as active groove.Active groove 37 is made of the active groove polysilicon 6 and gate oxide 9 to contact with each other, active
Trench polisilicon 6 is connected with the gate electrode 30 of device.Virtual primitive unit cell is left virtual according to being known as with the relative position of active primitive unit cell 40
Primitive unit cell 51 and right virtual primitive unit cell 52, virtual primitive unit cell 51,52 include multiple grooves 38, hereinafter referred to as virtual groove 38.Virtual ditch
Slot 38 is made of the virtual trench polisilicon 3 and gate oxide 9 to contact with each other, virtual trench polisilicon 3 and emitter electrode phase
Even.Device includes three kinds of p-type base areas 7a, 7b and 7c.Wherein the first p-type base area 7a and second of p-type base area 7b is located at active
Within primitive unit cell, the third p-type base area 7c is located within virtual primitive unit cell.In the inner upper of p-type base area 7a, 7c, there are N+ transmittings
Area 1 and the contact zone P+ 2, they are connected by the window 20 in dielectric layer 4 with metal emitting 5.P-type base area 7b current potential is outstanding
Sky, there is also the hanging N+ emitter region 1 of current potential and the contact zones P+ 2 for inner upper.
Fig. 3 is a kind of example device junction composition of the invention.The upper surface of p-type base area 7b is not provided with N+ emitter region 1 and P+ connects
Touch area 2；The upper surface of p-type base area 7c is not provided with N+ emitter region 1, and the contact zone P+ 2 above the 7c of p-type base area extends.
Fig. 4 is a kind of example device junction composition of the invention.The upper surface of p-type base area 7b is not provided with N+ emitter region 1 and P+ connects
Touch area 2；The upper surface of p-type base area 7c is also not provided with N+ emitter region 1 and the contact zone P+ 2.
Fig. 5 is a kind of example device junction composition of the invention.The dielectric layer 4 in virtual primitive unit cell region does not have window 20, because
The current potential of this p-type base area 7c is hanging.
Fig. 6 is a kind of example device junction composition of the invention.P-type base area 7c be it is discontinuous, p-type base area 7c is along groove
Direction is divided into discontinuous region by the drift region N- 10, and each p-type base area 7c or current potential is hanging or and emitter
Electrode is connected.
Fig. 7 is a kind of example device junction composition of the invention.P-type base area 7b be it is discontinuous, p-type base area 7b is along groove
Direction is divided into discontinuous region by the drift region N- 10, and each p-type base area 7b is that current potential is hanging.
Fig. 8 is a kind of example device junction composition of the invention.Structure of the invention has been used in an inverse conductivity type IGBT: part
P-type collector 12 is replaced by the region N+ 14, the upper end in the region N+ 14 and is in contact with N-type field stop layer 11, under the region N+ 14
It holds and is in contact with metal collector 13.
Fig. 9 is a kind of example device junction composition of the invention.Structure of the invention has been used in a reverse blocking IGBT: N-type
Field stop layer 11 is entirely eliminated, and the p-type ring 15 that front has multiple current potentials hanging, the collector 12 at the back side extends to upwards
Front.
In structures described above example, the number of grooves and ratio that active primitive unit cell and virtual primitive unit cell region are included are can
Become, can according to design requirement corresponding change.
When making devices, silicon can also be replaced by other semiconductors with silicon carbide, gallium nitride etc..
Working principle of the present invention is as follows:
In conventional IGBT structure shown in Fig. 1, all grooves are all active grooves, therefore gate capacitance is bigger.In Fig. 2
Shown in structure, have many virtual grooves, therefore gate capacitance reduces, turn off energy consumption and turn-off delay time also accordingly subtracts
It is few.
For the performance of quantitative several structures of comparison, next to the performance of Fig. 1 structure and Fig. 2 structure of the invention into
Three-Dimensional Numerical Simulation and comparison are gone.Two kinds of device layers doping parameters of simulation are identical, and all with 650V
For IGBT.
Figure 10 is that the miller capacitance of two kinds of IGBT structures (Fig. 1 structure and Fig. 2 structure of the invention) compares figure.It therefrom can be with
Find out, when junction temperature (Tj) is 125 DEG C, miller capacitance (Cres) is as shown in the table.
| Fig. 1 structure | Fig. 2 structure | |
| Cres (Vce=2V) | 9.7nFcm-2 | 2.7nFcm-2 |
It can be seen that comparing with Fig. 1 structure, Fig. 2 structure provided by the invention can significantly reduce miller capacitance.
In order to compare the dynamic switching characteristic of two kinds of IGBT, the Three-dimensional simulation of switching circuit has also been carried out.Figure 11 is
For hard switching (hard switching) circuit tested.Circuit is by IGBT and reflux diode (free wheeling
Diode), load inductance (LLoad) and busbar voltage (Vbus) composition.The grid of IGBT passes through grid by driving circuit (driver)
Resistance (Rg) control.IGBT also has parasitic inductance (Lg, Lc and Le).
Figure 12 is the Three-dimensional simulation of the IGBT shutdown waveform of two kinds of structures (Fig. 1 structure and Fig. 2 structure of the invention)
As a result.Used two kinds of igbt chip effective areas are 1cm2, busbar voltage=300V, load current 200A has been furnished with
Exactly the same reflux diode.The value of grid resistance is by optimization, so that the shutdown due to voltage spikes of two kinds of IGBT is all relatively low.
The junction temperature (Tj) of all devices is all 125 DEG C.
Turn-off performance, including shutdown energy consumption (Eoff), turn off due to voltage spikes (Vce peak) and turn-off delay time
(Turnoff delay time) is as shown in the table.
| Fig. 1 structure | Fig. 2 structure | |
| Eoff | 14.592mJ | 9.951mJ |
| Vce peak | 470V | 461V |
| Turnoff delay time | 2.0229μs | 0.5513μs |
It can be seen that comparing than Fig. 1 structure, the shutdown energy consumption of Fig. 2 structure provided by the invention reduces 32%, and shutdown is prolonged
The slow time reduces 73%.In addition the shutdown due to voltage spikes of structure of the invention is lower, is conducive to the reliability for improving device.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention.It is all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Embodiments of the present invention are described in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementations
Mode, technical field those of ordinary skill within the scope of knowledge, present inventive concept can also not departed from
Under the premise of make a variety of changes.
Claims (8)
1. a kind of insulated-gate bipolar transistor device structure, has the back side and front, the device is successively wrapped since the back side
It includes: including metal collector (13), p-type collector (12), N-type field stop layer (11) and the drift region N- (10), in the drift region N-
(10) be provided with N-type CS layers (8) close to positive part in, top device include active primitive unit cell (40) and virtual primitive unit cell (51,
52) two kinds of regions, wherein virtual primitive unit cell (51,52) be arranged in active primitive unit cell (40) two sides and respectively according to and active primitive unit cell (40)
Relative position be known as left virtual primitive unit cell (51) and right virtually primitive unit cell (52), it is characterised in that: active primitive unit cell (40) included
Groove only there are two and also the two grooves be it is adjacent, they are referred to as active groove (37)；The groove knot of active groove (37)
Structure is made of the active groove polysilicon (6) and gate oxide (9) to contact with each other, wherein active groove polysilicon (6) and grid electricity
Pole (30) is connected；Active primitive unit cell region (40) by the two active grooves (37) and with active groove (37) close adjacent half
Conductor layer is formed, and the right and left of active primitive unit cell (40) is all virtual primitive unit cell (51,52), and virtual primitive unit cell (51,52) is included
Groove be referred to as virtual groove (38)；The groove structure of virtual groove (38) is by the virtual trench polisilicon (3) that contacts with each other
It is formed with gate oxide (9), wherein virtual trench polisilicon (3) is connected with emitter electrode；Virtual primitive unit cell region (51,52) with
Virtual groove (38) is its boundary, and all grooves all at least break through part CS layers (8) and part N- drift layer (10)；Device top
Portion further includes three kinds of p-type base areas, they are all located at the top of CS layers (8)；The first p-type base area (7a) is located at active primitive unit cell region
(40) it in, but is not present between two active grooves (37), the first p-type base area (7a) is additionally provided with N+ emitter region (1) above
With the contact zone P+ (2), and it is connected by the window (20) in dielectric layer with metal emitting (5)；Second of p-type base area (7b)
It between two active grooves (37) in active primitive unit cell region (40), and is all that current potential is hanging；The third p-type base area
(7c) is located in virtual primitive unit cell region (51,52).
2. a kind of insulated-gate bipolar transistor device structure according to claim 1, it is characterised in that: second of p-type
Base area (7b), which can be, continuously can also be divided into discontinuous structure by the drift region N- (10), the third p-type base area (7c)
Can be continuously can also be divided into discontinuous structure by the drift region N- (10), and in the third p-type base area (7c)
One or more is that current potential is hanging, or is connected with emitter electrode.
3. a kind of insulated-gate bipolar transistor device structure according to claim 1, it is characterised in that: second of p-type
Base area (7b) and/or the third p-type base area (7c) also include the contact zone P+ (2) or connect comprising N+ emitter region (1) and P+ above
Touch both area (2).
4. a kind of insulated-gate bipolar transistor device structure according to claim 1, it is characterised in that: p-type collector
It (12) include also the region N+ (14) in, to replace part p-type collector (12), the upper end of the region N+ (14) and N-type field are terminated
Layer (11) is in contact, and the lower end of the region N+ (14) and is in contact with metal collector (13).
5. a kind of insulated-gate bipolar transistor device structure according to claim 1, it is characterised in that: left virtual primitive unit cell
The number of grooves that region (51) and right virtual primitive unit cell region (52) are included can be equal, can also be unequal.
6. a kind of insulated-gate bipolar transistor device structure according to claim 1, it is characterised in that: active primitive unit cell
(40) and the ratio of the virtual primitive unit cell region in left and right (the 51,52) number of grooves that is included is variable.
7. a kind of insulated-gate bipolar transistor device structure according to claim 1, it is characterised in that: used half
Conductor material is silicon, silicon carbide, gallium nitride.
8. a kind of insulated-gate bipolar transistor device structure, has the back side and front, the device is successively wrapped since the back side
Include: including metal collector (13), p-type collector (12), the drift region N- (10) and CS layers of N-type (8), top includes active primitive unit cell
(40) and two kinds of regions of virtual primitive unit cell (51,52), in which: the groove that active primitive unit cell (40) is included only there are two and also the two
Groove be it is adjacent, they are referred to as active groove (37)；The groove structure of active groove (37) is by the active groove that contacts with each other
Polysilicon (6) and gate oxide (9) composition, wherein active groove polysilicon (6) is connected with gate electrode (30)；Active primitive unit cell region
(40) it is formed by the two active grooves (37) and with the close adjacent semiconductor layer of active groove (37), active primitive unit cell
(40) the right and left is all virtual primitive unit cell (51,52), wherein this right and left virtual primitive unit cell (51,52) according to it is active
The relative position of primitive unit cell (40) is known respectively as left virtual primitive unit cell (51) and right virtual primitive unit cell (51), virtual primitive unit cell (51,52) institute
The groove for including is referred to as virtual groove (38)；The groove structure of virtual groove (38) is by the virtual trench polisilicon that contacts with each other
(3) it is formed with gate oxide (9), wherein virtual trench polisilicon (3) is connected with emitter electrode；Virtual primitive unit cell region (51,
52) with virtual groove (38) for its boundary, all grooves all at least break through part CS layers (8) and part N- drift layer (10)；
Top device further includes three kinds of p-type base areas being formed simultaneously, they are all located at the top of CS layers (8)；The first p-type base area (7a)
In active primitive unit cell region (40), but it is not present between two active grooves (37)；Second of p-type base area (7b) can be
Continuously be also possible to it is discontinuous, be located at active primitive unit cell region (40) in two active grooves (37) between；The third p-type
Base area (7c) can be continuously be also possible to it is discontinuous, be located at virtual primitive unit cell region (51,52) in；The first p-type base area
(7a) is additionally provided with N+ emitter region (1) and the contact zone P+ (2) above, and passes through the window (20) and metal emitting in dielectric layer
(5) it is connected；Second of p-type base area (7b) is all that current potential is hanging；The third each p-type base area (7c) or be that current potential is hanging
Or be connected with emitter electrode；The p-type ring (15) that the positive drift region N- has multiple current potentials hanging, the p-type current collection at the back side
Pole (12) extends to front upwards.
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| CN107634094B (en) * | 2017-08-29 | 2020-01-21 | 中山汉臣电子科技有限公司 | Insulated gate bipolar transistor structure and manufacturing method thereof |
| CN109545847A (en) * | 2018-11-08 | 2019-03-29 | 国电南瑞科技股份有限公司 | A kind of virtual trench gate structure |
| CN110416283B (en) * | 2019-07-17 | 2022-11-01 | 国电南瑞科技股份有限公司 | IGBT device structure |
| CN110429133B (en) * | 2019-07-17 | 2022-11-01 | 国电南瑞科技股份有限公司 | Insulated gate bipolar transistor |
| CN111106043B (en) * | 2019-12-23 | 2022-08-19 | 珠海格力电器股份有限公司 | Power semiconductor device cell structure, preparation method thereof and power semiconductor device |
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| CN101582443A (en) * | 2008-05-13 | 2009-11-18 | 三菱电机株式会社 | Semiconductor device |
| JP2011165928A (en) * | 2010-02-10 | 2011-08-25 | Toyota Central R&D Labs Inc | Insulated gate bipolar transistor |
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| CN104518015A (en) * | 2013-10-01 | 2015-04-15 | 株式会社东芝 | Semiconductor device |
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| DE102009005914B4 (en) * | 2008-01-28 | 2014-02-13 | Denso Corporation | Semiconductor device with insulated gate semiconductor element and insulated gate bipolar transistor |
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| CN101582443A (en) * | 2008-05-13 | 2009-11-18 | 三菱电机株式会社 | Semiconductor device |
| JP2011165928A (en) * | 2010-02-10 | 2011-08-25 | Toyota Central R&D Labs Inc | Insulated gate bipolar transistor |
| CN104145342A (en) * | 2012-03-16 | 2014-11-12 | 富士电机株式会社 | Semiconductor device |
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