JP7022148B2 - Vertical FET structure - Google Patents

Description

[0001] The present invention relates to a vertical field effect transistor (FET) structure.

[0002] Silicon Carbide (SIC) -based Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) offer significant advantages over MOSFET silicon (Si) -based counterparts in high power applications. However, one advantage of Si-based MOSFETs over SiC-based MOSFETs is the larger internal gate-source capacitance _CGS . Having a larger _CGS leads to preventing Si-based MOSFETs from being accidentally turned on due to transients in the drain bias. Therefore, there is a need for space-efficient and effective techniques for increasing the effective _CGS for SiC MOSFETs.

[0003] A vertical field effect transistor (FET) structure is disclosed. A vertical FET is a silicon carbide substrate having an upper surface and an opposite lower surface of the upper surface, a drain / collector contact on the lower surface of the silicon carbide substrate, and an epitaxial structure on the upper surface of the silicon carbide substrate. It includes an epitaxial structure in which a first source / emitter implant is formed. The gate dielectric is provided on a portion of the epitaxial structure. Place the first source / emitter contact pieces on the first source / emitter injectate, spaced from each other so that the gate dielectric is not below the first source / emitter contact pieces. Isolate. The first elongated gate contact and the second elongated gate contact are on the gate dielectric and the first source / emitter injectate is of the first elongated gate contact and the second elongated gate contact. It is located below and is laid so as to be between the first elongated gate contact and the second elongated gate contact. The first plurality of inter-gate plates from at least one of the first elongated gate contact and the second elongated gate contact of the first plurality of source / emitter contact pieces. It extends into the space formed between them. Additional internal capacitance is provided, each of the first plurality of intergate plates overlaps a portion of the first source / emitter injectate, and the intergate plates are separated by a gate dielectric. The epitaxial structure may be formed from silicon carbide or other suitable material system.

[0004] Each of the first plurality of intergate plates passes through the space formed between adjacent pairs of the first plurality of source / emitter contact pieces with the first elongated gate contact and the second. It may extend well between the elongated gate contacts of the. Further, the first elongated gate contact, the second elongated gate contact, and the first plurality of intergate plates may be formed from the same material in the same or different planes.

[0005] In one embodiment, the vertical FET forms at least a first transistor cell and a second transistor cell, and a first elongated gate contact forms part of the first transistor cell. , The second elongated gate contact may be included to form part of the second transistor cell. The first source / emitter injection may be shared by the first transistor cell and the second transistor cell. The first transistor cell and the second transistor cell may be a metal oxide semiconductor field effect transistor (PWM) cell, an insulated gate bipolar transistor (IGBT) cell, and the like.

[0006] The epitaxial structure may further include a first source / emitter well in which the first source / emitter injectate is provided. For MOSFET configurations, the substrate and source / emitter injectate are doped with a material having a first polarity, and the first source well is a doping material with a second polarity that is the opposite polarity of the first polarity. Dope with. For IGBT configurations, the substrate and source / emitter wells are doped with a material having a first polarity and the first source / emitter injectate has a second polarity, which is the opposite polarity of the first polarity. Dope with a doping material.

[0007] The vertical FET has a gate-source / emitter capacitance and a gate-drain / collector capacitance, and the ratio of the gate-source / emitter capacitance to the gate-drain capacitance is due to the gate-to-gate plate. Greater than 170, 200, 250, 300, 350, or more. Further, the vertical FET includes a gate-source / emitter capacitance and a gate-drain / collector capacitance, and the ratio of the gate-source / emitter capacitance to the gate-drain / collector capacitance is between 200 and 750. Further, the vertical FET includes a gate-source / emitter capacitance and a gate-drain / collector capacitance, and the ratio of the gate-source / emitter capacitance to the gate-drain / collector capacitance is between 300 and 1,000. be.

[0008] The adjectives source / emitter and drain / collector are referred to as MOSFETs, IGBTs, taking into account the similarities between the source and emitter elements and between the drain and collector elements of MOSFETs and IGBT devices. And used to describe the corresponding elements for similar devices in general. For example, an elongated drain / collector contact is defined herein to include both an elongated drain contact and an elongated collector contact. The source / emitter region is defined herein to include both the source region and the emitter region. Source / emitter wells are defined herein to include both source wells and emitter wells. Source / emitter injects are defined herein to include both source and emitter injects, and so on. The gate-source / emitter capacity is, depending on the circumstances, the capacity between the gate of the device and either the source or the emitter. The gate-drain / collector capacity is, depending on the circumstances, the capacity between the gate and either the drain or the collector of the device.

[0009] Those skilled in the art will recognize the scope of the present disclosure and understand additional aspects of the present disclosure by reading the subsequent detailed description of the preferred embodiments, associated with the figures of the accompanying drawings. There will be.
[0010] The accompanying drawings incorporated herein and forming part of this specification serve to illustrate, explain, and explain the principles of the present disclosure, along with illustrations of some aspects of the present disclosure. do.

[0011] FIG. 6 is a cross-sectional view of a MOSFET cell at a first location according to one embodiment of the present disclosure. [0012] It is a top view of the conventional MOSFET cell. [0013] Top view of the MOSFET cell of FIG. 1 according to one embodiment of the present disclosure. [0014] FIG. 3 is a cross-sectional view of the MOSFET cell of FIG. 1 at a second location according to one embodiment of the present disclosure. [0015] It is a graph which plots the capacity with respect to the drain-source voltage for the conventional MOSFET cell. It is a graph which plots the capacity with respect to the drain-source voltage about the MOSFET cell of FIG. [0016] FIG. 6 is a cross-sectional view of an IGBT cell at a first location according to one embodiment of the present disclosure. [0017] FIG. 6 is a cross-sectional view of the IGBT cell of FIG. 7 at a second location according to one embodiment of the present disclosure.

[0018] The embodiments described below represent the necessary information to enable one of ordinary skill in the art to practice the embodiments and illustrate the best embodiments in which the embodiments are practiced. By reading the following description in the light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will not be specifically focused on herein. Will be recognized. It should be understood that these concepts and applications are within the scope of this disclosure and the accompanying claims.

[0019] Terms, first, second, and others may be used herein to describe various elements, but these elements should not be restricted by these terms. You will understand that. These terms are used simply to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any combination of one or more of the relevant listed items.

[0020] When an element such as a layer, area, or substrate is referred to as being "on" another element or extending "on" another element, that element is on top of that other element. It will be understood that there may be elements that are directly present or that can extend directly onto another element, or that intervene. In contrast, when referring to an element as being "directly above" another element or extending "directly above" another element, there are no intervening elements. Similarly, when an element such as a layer, area, or substrate is referred to as extending "directly above" or "directly above" another element, that element is the other. Understand that there may be elements that are directly above an element, or that can extend directly above another element, or that intervene. become. In contrast, when referring to an element as being "directly above" another element or extending "directly directly above" another element, there are no intervening elements. When an element is referred to as "connecting" or "joining" to another element, that element can be directly connected to, connected to, or intervening with the other element. You will even understand that there are things. In contrast, when referring to an element as "directly connecting" or "directly joining" to another element, there are no intervening elements.

[0021] Terms such as "downward" or "upper" or "upper" or "lower" or "horizontal" or "vertical" are used herein, as illustrated in the drawings. It may be used to describe the relationship between one element, layer, or region to another element, layer, or region. It will be understood that these terms, and the terms discussed above, are intended to comprehensively include different orientations of the device in addition to the orientations illustrated in the figure.

[0022] The terminology used herein is solely for the purpose of describing a particular embodiment and is not intended to be restrictive to the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural form as well, unless explicitly stated in the context. The terms "prepare (third person singular present tense)", "prepare (present tense)", "include (third person singular present tense)", and / or "include (present tense)" as used herein. Specifies the presence of the feature, integer, step, action, element, and / or component being described, but one or more other features, integer, step, action, element, component, and /. Or you will further understand that you do not rule out the existence or addition of those groups.

[0023] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Have. The terms used herein should be construed as having a meaning consistent with the context of this specification and the meaning of those terms in the relevant art, idealized or. It is further understood that an overly formal meaning is not to be construed unless explicitly defined as such herein.

[0024] A vertical FET structure is disclosed herein. The vertical FET structure consists of a silicon carbide substrate having an upper surface and an opposite lower surface of the upper surface, a drain / collector contact on the lower surface of the silicon carbide substrate, and an epitaxial structure on the upper surface of the silicon carbide substrate. It includes an epitaxial structure in which a first source / emitter injectate is formed in the epitaxial structure. The gate dielectric is provided on a portion of the epitaxial structure. The first source / emitter contact pieces are spaced apart from each other on the first source / emitter injectate. The first elongated gate contact and the second elongated gate contact are on the gate dielectric and the first source / emitter injectate is of the first elongated gate contact and the second elongated gate contact. It is located below and so as to be between the first elongated gate contact and the second elongated gate contact. The intergate plate extends from at least one of the first elongated gate contact and the second elongated gate contact into the space formed between the first source / emitter contact pieces. Additional internal capacitance is provided, each of the first multi-gate intergate plates overlapping a portion of the first source / emitter injectate and separated by a gate dielectric. The epitaxial structure may be formed from silicon carbide or other suitable material system. Details are provided below.

[0025] With reference to FIG. 1, a cross section of a cell with respect to a Power MOSFET (Double Injection Metal Oxide Semiconductor Field Effect Transistor) is illustrated. The cells are generally labeled with MOSFET cells 10 and reference numerals. MOSFET cells 10 are used to illustrate various concepts, which are applicable to virtually any type of vertical FET structure, including isolated gate bipolar transistors (IGBTs), and the like. Is.

[0026] In one embodiment, MOSFET cells 10 are formed in 4H- or 6H-silicon carbide (SiC) using a dual ion implantation process. In particular, the MOSFET cell 10 includes a SiC substrate 12 that is heavily doped with an N-type dopant (N +). The SiC epitaxial structure is directly above the substrate 12 so as to provide the drift region 14, and two source regions 16 are formed in the upper portion of the epitaxial structure by a double injection process. Although SiC material systems are used for epitaxial structures and substrates 12, other material systems such as gallium nitride (GaN) may benefit from the concepts disclosed herein. The drift region 14 is doped with an N-type dopant at a low concentration (N−). Each source region 16 is moderately doped with a P-type dopant (P), with the source well 18 and the source injectate 20 located in the source well 18 and biased towards the upper surface of the source well 18. including. The source injectate 20 is heavily doped with an N-type dopant (N +). Source regions 16 are spaced along the upper surface of the epitaxial structure, spaced from each other so that JFET (junction FET) regions are formed between the source regions.

[0027] The gate dielectric 22 is on the upper surface of the epitaxial structure. The elongated gate contact 24 is directly above the gate dielectric 22. The source contact piece 26 is directly above each portion of the source region 16. In particular, each source contact piece 26 is directly above the outer portion of the corresponding source well 18 and source injectate 20. The gate dielectric 22 extends between the source contact pieces 26, and the elongated gate contact 24 is directly above the gate dielectric 22 and between the source contact pieces 26. However, the elongated gate contact 24 does not come into contact with the source contact piece 26 and only extends directly above the inner portion of the source well 18 and the source injectate 20. As illustrated, the elongated gate contact 24 extends directly above only a small portion of the source injectate 20. An elongated drain contact 28 is provided on the lower side of the substrate 12.

[0028] In operation, a high voltage across the elongated drain contact 28 and source contact piece 26 is sustained by the MOSFET cell 10 when a bias below the threshold voltage is applied to the elongated gate contact 24. When a positive bias is applied to the elongated gate contact 24, current will flow from the source contact piece 26 to the elongated drain contact 28. As illustrated by the dashed line in FIG. 1, the current is elongated from the source contact piece 26 through the source injectate 20 and the source well 18 sideways and then vertically through the drift region 14 and the substrate 12. Will flow to the drain contact 28 of.

[0029] For certain embodiments adapted for high power applications, the substrate 12 may range in thickness from 50 um to 600 um and in concentration from 1 × 10 ¹⁸ cm ^-3 to 1. May be doped between × 10 ²⁰ cm ^-3 . The drift region 14 may range in thickness from 3 um to 150 um and may be doped in concentration between 1 × 10 ¹⁴ cm ^-3 and 1 × 10 ¹⁸ cm ^-3 . The source well 18 can range in thickness from 0.2 um to 2 um and can be doped in concentration between 1 × 10 ¹⁵ cm ^-3 and 1 × 10 ¹⁹ cm ^-3 . The source injectate 20 may range in thickness from 0.1 um to 0.5 um and is doped in concentration between 1 × 10 ¹⁹ cm ^-3 and 5 × 10 ²¹ cm ^-3 . There is. The gate dielectric 22 may be formed from high dielectric constant dielectrics such as silicon dioxide, silicon nitride, hafnium oxide, and the like. The elongated gate contact 24, source contact piece 26, and elongated drain contact 28 may be formed from a metal such as polysilicon, aluminum, metal silicide, and the like. Exemplary N-type dopants include nitrogen and phosphorus. Exemplary P-type dopants include aluminum and boron. In addition, the doping polarities of the various layers and regions may be reversed or modified, depending on the application of the MOSFET cell 10 and the desired operation.

[0030] With reference to FIG. 2, a top view of a conventional layout design for a conventional MOSFET cell 10'is illustrated. In particular, FIG. 2 illustrates three conventional MOSFET cells 10', which are elongated from left to right. Three elongated gate contacts 24, two elongated source injections 20, and two elongated source contacts 30 are illustrated. For clarity, the gate dielectric 22 is not illustrated. This conventional arrangement design does not use the source contact piece 26, but instead uses a continuous elongated source contact 30. A close pair of elongated gate contacts 24 is directly above the opposite portion of the source injectate 20. The elongated source contact 30 is directly above the central portion of the source injectate 20 and is spaced apart from the elongated gate contact 24, as noted above.

The discussion that follows extends to various measurements, including capacitance and voltage, as measured between any two of the drain, gate, and source of the MOSFET cell 10. These measurements are made between the corresponding contacts associated with the drain (elongated drain contact 28), gate (elongated gate contact 24), and source (source contact piece 26) of the MOSFET cell 10. For example, the gate-source capacitance _CGS is the capacitance measured between the gate (slender gate contact 24) and the source (source contact piece 26), and the gate-drain capacitance _CGD is the gate (slender gate). The capacitance measured between the contact 24) and the drain (elongated drain contact 28), and so on. For IGBT embodiments, these measurements are made between the collector, the gate (slender gate contact 24), and the corresponding contacts associated with the emitter. For example, as further described below, the gate-emitter capacitance CGE is the capacitance measured between the gate and emitter, and the gate-collector capacitance CGC is the capacitance measured between the gate and collector. be.

[0032] The MOSFET cell _10'has an internal capacitance including a gate-source capacitance CGS and a gate-drain capacitance _CGD . The charge in the gate-source capacitance _CGS determines when the device will turn on and off. The charge in the gate-drain capacitance _CGD determines the drain-source voltage VDS. Rapid changes in drain bias, which can be caused by fast turn-off transients, tend to send large amounts of charge towards the gate due to the gate-drain capacitance _CGD . Gate drives usually absorb most of this charge, but not all of it. Moreover, the charge is not absorbed instantaneously. The non-absorbed charge is instantaneously shared with respect to the gate-source capacitance _CGS . The charge shared with the gate-source capacitance _{CGS increases the gate-source voltage VGS .} When the _{VGS rises} above the threshold voltage, the MOSFET cell 10'will erroneously turn on. Efforts to avoid this phenomenon are to use external capacitors outside the structure of MOSFET cell _10'to add external capacitance between the gate and source to increase the gate-source capacitance CGS. Has focused on. Unfortunately, these efforts have proven to be largely ineffective, increasing the size of the module in which the MOSFET cell 10'is incorporated, increasing the number of parts, which in turn increases the reliability of the module. May have a negative impact on.

Looking at FIG. 3 here, a top view of the layout design for the MOSFET cell 10 of the present disclosure is illustrated. Instead of the elongated source contact 30, a series of source contact pieces 26 are provided directly above the middle portion of each source injectate 20. As a result, an open area is formed directly above each source injectate 20 between adjacent source contact pieces 26. Gate-to-gate plates 32 are provided in these areas. In one embodiment, the intergate plate 32 is an extension of the elongated gate contact 24, and each intergate plate 32 effectively connects adjacent ones of the elongated gate contact 24. Therefore, elongated gate contacts 24 and intergate plates 32 may be formed from the same material in the same plane and in the same process step. In one embodiment, the elongated gate contact 24 and the intergate plate 32 may be formed from a metal such as polysilicon, aluminum, metal silicide, and the like. Alternatively, the intergate plates 32 may be formed from different materials in the same or different planes and in the same or different process steps.

[0034] FIG. 4 illustrates a cross section of a MOSFET cell 10 (cut BB in FIG. 3) taken through an intergate plate 32, where the elongated gate contact 24 and the intergate plate 32 are gates. It is formed from a continuous conductive structure directly above the dielectric 22. For comparison, FIG. 1 corresponds to a cross section of MOSFET cell 10 (cut AA in FIG. 3) taken through one of the source contact pieces 26.

The addition of the intergate plate 32 adds capacity between the gate and source of each MOSFET cell 10. Additional capacity,
The intergate plate 32 is provided directly above the source well 18 and the source injectate 20 in the source region 16 and
The intergate plate 32 is formed by separating the source area 16 from the source well 18 and the source injectate 20 with a gate dielectric 22. In essence, each intergate plate 32 provides a first capacitive plate, an overlapping portion of the source region 16 provides a second capacitive plate, and the gate dielectric 22 provides a first capacitive plate. A dielectric material that separates the sex plate and the second capacitive plate is provided to provide additional internal capacitance within the MOSFET cell 10. By using the intergate plate 32 to provide additional internal capacitance, the performance of the MOSFET cell 10 is significantly increased with little or no increase in the size of the modular network in which the MOSFET cell 10 is used. Increase. In particular, in this mode, increasing the gate-source capacitance _CGS from within the MOSFET cell 10 suppresses false turn-on events during high speed turn-off without increasing the effective on-resistance of the MOSFET cell 10. It helps.

[0036] The intergate plate 32 does not need to extend sufficiently between the elongated gate contacts 24 of the adjacent MOSFET cells 10. For example, the intergate plate 32 may simply be akin to a tab extending from the elongated gate contact 24 into the area between the source contact pieces 26. Further, the intergate plate 32 does not have to be rectangular and may have various shapes, sizes, and contours based on device geometry and performance goals. Similarly, the source region 16, the source well 18, and the source injectate 20 may have varying patterns and shapes, and thus need not be the simple elongated valleys illustrated in FIG. Any of these entities may be any combination of continuous elongated valleys, ladder shapes, and the like. Moreover, these entities may be elongated and nevertheless discontinuous, depending on the application.

The graphs of FIGS. 5 and 6, respectively, compare the various capacities of a SiC transistor device that mounts a MOSFET cell 10 with and without the intergate plate 32, respectively. Specifically, each graph cuts off 1200V, passes 20A, and drain-source voltage for a power silicon carbide MOSFET device rated to have an on-state resistance (Rds-on) of 80 milliohms. Plot the _{Ciss, C ossi ,} and C _rss in picofarad units for VDS. C _iss is equal to the sum of the gate-source capacity C _GS and the gate-drain capacity C _GD (C _iss = C _GS + C _GD ). _Crss is equal to the gate-drain capacitance _CGD . C _oss is equal to the sum of drain-source capacity CDS and gate-drain capacity C _GD (C _oss = CDS + C _GD ). _Crss is equal to the gate-drain capacitance _CGD . From these measurements, the _CGS to _CGD ratio ( _CGS / _CGD ) can be derived.

[0038] In particular, C _GS = C _iss -C _GD and C _iss = C _GS plus C _GD . Between 900 and 1,000 volts, the CGS to _CGD ratio is approximately 124 for conventional devices that do not include the _intergate plate 32. The CGS to _CGD ratio for similar devices that include the _intergate plate 32 is 385, which is more than three times higher than conventional devices that do not include the intergate plate 32. While silicon-based devices can achieve _{CGS to CGD ratios} within this range, silicon carbide-based devices were not possible prior to the implementation of the intergate plate 32 of the present disclosure. By the concepts disclosed herein, silicon carbide-based devices achieve a _{CGS to CGD ratio} comparable to silicon-based devices, while silicon carbide-based devices are silicon-based compatible with those silicon-based devices. You can enjoy all of the additional benefits that you can win and offer. Depending on the embodiment, the _CGS to _CGD ratio greater than 150, 175, 200, 250, 300, 350, and even 400 is now relative to the silicon carbide MOSFET cell 10 (without the need for external capacitance). It is possible. These ranges may be bounded by CGS to _{CGD ratios} of 500, 750, and 1000 in different embodiments.

[0039] As noted above, these concepts can be applied not only to the MOSFET cell 10 but also to any vertical FET device such as an IGBT. FIG. 7 illustrates a cross section of an exemplary IGBT cell 34. In one embodiment, the IGBT cell 34 is formed in 4H- or 6H-silicon carbide (SiC) using a dual ion implantation process. In particular, the IGBT cell 34 contains a SiC substrate 36 that is heavily doped with a P-type dopant (P +), which represents the major difference between the IGBT cell 34 and the MOSFET cell 10. In the MOSFET cell 10, the substrate 36 is heavily doped with an N-type dopant. The epitaxial structure is directly above the substrate 36 so as to provide the drift region 38, and the two emitter regions 40, which are similar to the source region 16 of the MOSFET cell 10, are the upper part of the epitaxial structure by the double injection process. Formed inside. The drift region 38 is doped with an N-type dopant at a low concentration (N−). Each emitter region 40 is a (P) emitter well 42 moderately doped with a P-type dopant and an emitter injection 44 that resides in the emitter well 42 and is biased towards the upper surface of the emitter well 42. And include. The emitter injection 44 is heavily doped with an N-type dopant (N +). Emitter regions 40 are spaced along the upper surface of the epitaxial structure, spaced from each other so that JFET (junction FET) regions are formed between them.

[0040] The gate dielectric 46 is on the upper surface of the epitaxial structure. The elongated gate contact 48 is directly above the gate dielectric 46. The emitter contact piece 50 is directly above each portion of the emitter region 40. In particular, each emitter contact piece 50 is directly above the outer portion of the corresponding emitter well 42 and emitter injector 44. The gate dielectric 46 extends between the emitter contact pieces 50, and the elongated gate contact 48 is directly above the gate dielectric 46 and between the emitter contact pieces 50. However, the elongated gate contact 48 does not come into contact with the emitter contact piece 50 and only extends directly above the inner portion of the emitter well 42 and the emitter injectate 44. As illustrated, the elongated gate contact 48 extends directly above only a small portion of the emitter injectate 44. An elongated collector contact 52 is provided on the lower side of the substrate 36.

[0041] For certain embodiments adapted for high power applications, the substrate 36 may range in thickness from 1 um to 400 um and in concentration from 1 × 10 ¹⁸ cm ^-3 to 1. May be doped between × 10 ²¹ cm ^-3 . The drift region 38 can range in thickness from 10 um to 250 um and can be doped in concentration between 1 × 10 ¹³ cm ^-3 and 5 × 10 ¹⁶ cm ^-3 . Emitter wells 42 can range in thickness from 0.2 um to 2 um and can be doped in concentration between 1 × 10 ¹⁵ cm ^-3 and 1 × 10 ¹⁹ cm ^-3 . The emitter injectate 44 may range in thickness from 0.1 um to 0.5 um and is doped in concentration between 1 × 10 ¹⁹ cm ^-3 and 5 × 10 ²¹ cm ^-3 . There is. The gate dielectric 46 may be formed from high dielectric constant dielectrics such as silicon dioxide, silicon nitride, hafnium oxide, and the like. The elongated gate contact 48, emitter contact piece 50, and elongated collector contact 52 may be formed from a metal such as polysilicon, aluminum, metal silicide, and the like. Again, the doping polarities of the various layers and regions may be reversed or modified, depending on the application of the IGBT cell 34 and the desired operation.

The top view of the device on which the IGBT cell 34 is mounted is the same as the top view illustrated in FIG. 3, where the source injectate 20 corresponds to the emitter injector 44 and the source contact piece 26 is a source contact piece 26. Corresponds to the emitter contact piece 50. Therefore, FIG. 7 corresponds to the cross section AA of FIG. 3, and FIG. 8 corresponds to the cross section BB of FIG. The intergate plate 32 for the IGBT cell 34 is illustrated in FIG. 8, where the intergate plate 32 is an extension of the elongated gate contact 48.

[0043] The adjectives source / emitter and drain / collector are referred to as MOSFETs, IGBTs, taking into account the similarities between the source and emitter elements and between the drain and collector elements of MOSFETs and IGBT devices. And used to describe the corresponding elements for similar devices in general. For example, an elongated drain / collector contact is defined herein to include both an elongated drain contact and an elongated collector contact. The source / emitter region is defined herein to include both the source region and the emitter region. Source / emitter wells are defined herein to include both source wells and emitter wells. Source / emitter injects are defined herein to include both source and emitter injects, and so on. The gate-source / emitter capacity is, depending on the circumstances, the capacity between the gate of the device and either the source or the emitter. The gate-drain / collector capacity is, depending on the circumstances, the capacity between the gate and either the drain or the collector of the device.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and amendments are believed to be included in the concepts disclosed herein and in the claims that follow.

Claims (27)

A silicon carbide substrate having an upper surface and a lower surface opposite to the upper surface.
The drain / collector contact on the lower surface of the silicon carbide substrate,
The epitaxial structure on the upper surface of the silicon carbide substrate, wherein the first source / emitter well in which the first source / emitter injection is provided is formed in the epitaxial structure. When,
-The gate dielectric on a part of the epitaxial structure and
The first plurality of source / emitter contact pieces, each spaced from each other so that the gate dielectric is not below the first plurality of source / emitter contact pieces. 1 .
A first elongated gate contact and a second elongated gate contact that are on the gate dielectric and the first source / emitter injectate is the first elongated gate contact and said first. A first elongated gate contact and a second elongated gate contact located below the two elongated gate contacts and between the first elongated gate contact and the second elongated gate contact. Gate contact and
• Extends from at least one of the first elongated gate contact and the second elongated gate contact into the space formed between the first plurality of source / emitter contact pieces. The first plurality of intergate plates and
The first plurality of intergate plates are separated from a portion of the first source / emitter injection by the gate dielectric, a vertical field effect transistor (FET) structure. At least the first transistor cell and the second transistor cell, the first elongated gate contact forms a part of the first transistor cell, and the second elongated gate contact is the first. Further included to form part of the transistor cell of 2, additional internal capacitance is provided, each of the first plurality of intergate plates with said portion of the first source / emitter injection. The vertical FET structure according to claim 1, which overlaps. The vertical FET structure according to claim 2, wherein the first source / emitter injection material is shared by the first transistor cell and the second transistor cell. The vertical FET structure according to claim 3, wherein the first transistor cell and the second transistor cell are metal oxide semiconductor field effect transistor (MOSFET) cells. The vertical FET structure according to claim 3, wherein the first transistor cell and the second transistor cell are insulated gate bipolar transistor (IGBT) cells. The silicon carbide substrate and the first source / emitter injectate are doped with a material having the first polarity, and the first source / emitter well is made of a second polarity opposite to the first polarity. The vertical FET structure according to claim 1, which is doped with a doping material having the same polarity as. The silicon carbide substrate and the first source / emitter well are doped with a material having the first polarity, and the first source / emitter injectate is a second polarity opposite to the first polarity. The vertical FET structure according to claim 1, which is doped with a doping material having the same polarity as. Each of the first plurality of gate-to-gate plates passes through a space formed between adjacent pairs of the first plurality of source / emitter contact pieces to the first elongated gate contact and the first. The vertical FET structure according to claim 1, which extends between the elongated gate contact of 2. The vertical FET structure according to claim 1, wherein the first elongated gate contact, the second elongated gate contact, and the first plurality of intergate plates are made of the same material. The first elongated gate contact, the second elongated gate contact, and the first plurality of intergate plates are formed from the same material on a common plane, according to claim 1. Vertical FET structure. The vertical FET structure according to claim 1, wherein the epitaxial structure is formed of silicon carbide. A portion of the first elongated gate contact overlaps the first portion of the first source / emitter injection and a portion of the second elongated gate contact is the first source / emitter injection. The vertical FET structure according to claim 1, which overlaps with the second part of the above. The gate-source / emitter capacity and the gate-drain / collector capacity are further provided, and the ratio of the gate-source / emitter capacity to the gate-drain / collector capacity is in the range of 170 to 1000, claim 1. The vertical FET structure described. The gate-source / emitter capacity and the gate-drain / collector capacity are further provided, and the ratio of the gate-source / emitter capacity to the gate-drain / collector capacity is in the range of 250 to 1000, claim 1. The vertical FET structure described. The gate-source / emitter capacity and the gate-drain / collector capacity are further provided, and the ratio of the gate-source / emitter capacity to the gate-drain / collector capacity is in the range of 350 to 1000, claim 1. The vertical FET structure described. The gate-source / emitter capacity and the gate-drain / collector capacity are further provided, and the ratio of the gate-source / emitter capacity to the gate-drain / collector capacity is between 200 and 750, claim 1. The vertical FET structure described. A gate-source / emitter capacity and a gate-drain / collector capacity are further provided, and the ratio of the gate-source / emitter capacity to the gate-drain / collector capacity is between 300 and 1,000. The vertical FET structure according to 1. The epitaxial structure further comprises a second source / emitter injectate that is spaced apart from the first source / emitter injectate.
The second source of the second source / emitter contact pieces, spaced from each other so that the gate dielectric is not below the second source / emitter contact pieces. / A second plurality of source / emitter contact pieces isolated on the emitter injector,
A third elongated gate contact that is on the gate dielectric and the second source / emitter injectate is below the first elongated gate contact and the third elongated gate contact. A third elongated gate contact, which is located between the first elongated gate contact and the third elongated gate contact.
• Extends from at least one of the first elongated gate contact and the third elongated gate contact into the space formed between the second plurality of source / emitter contact pieces. A second plurality of gate-to-gate plates, provided with additional internal capacitance, each of the second plurality of gate-to-gate plates overlapping a portion of the second source / emitter injectate, said second. The vertical FET structure according to claim 1, wherein the plurality of intergate plates of 1 further includes a second plurality of intergate plates separated by the gate dielectric. Each of the first plurality of intergate plates passes through a space formed between adjacent pairs of the first plurality of source / emitter contact pieces to the first elongated gate contact and said. Extending between the second elongated gate contact,
Each of the second plurality of gate-to-gate plates passes through a space formed between adjacent pairs of the second plurality of source / emitter contact pieces to the first elongated gate contact and said. Extends between the third elongated gate contact,
The vertical FET structure according to claim 18. The vertical FET structure according to claim 18, wherein the first elongated gate contact, the second elongated gate contact, and the first plurality of intergate plates are made of the same material. 18. The first elongated gate contact, the second elongated gate contact, and the first plurality of intergate plates are formed from the same material on a common plane, according to claim 18. Vertical FET structure. The vertical FET structure according to claim 21, wherein the epitaxial structure is formed of silicon carbide. The gate-source / emitter capacity and the gate-drain / collector capacity are further provided, and the ratio of the gate-source / emitter capacity to the gate-drain / collector capacity is between 200 and 750, claim 1. The vertical FET structure described. A silicon carbide substrate having an upper surface and a lower surface opposite to the upper surface.
・ The drain contact on the lower surface and
A first source / emitter well of a silicon carbide epitaxial structure on the upper surface of the silicon carbide substrate, wherein a first source / emitter injectate is provided therein. The silicon carbide epitaxial structure formed and
A plurality of source contact pieces, wherein the plurality of source contact pieces are directly on a continuous portion of the first source / emitter well and on a continuous portion of the first source / emitter injectate. With a plurality of source contact pieces, each spaced apart from each other on the silicon carbide epitaxial structure, as directly present in.
A gate contact on the silicon carbide epitaxial structure, the extending portion of the gate contact extends onto the silicon carbide epitaxial structure in a space formed between adjacent pairs of the plurality of source contact pieces. Being there
A gate dielectric layer between the gate contact and the silicon carbide epitaxial structure, the gate dielectric layer is also disposed between the extending portion of the gate contact and the silicon carbide epitaxial structure. With a gate dielectric layer,
The ratio of gate-source capacity as measured between the gate contact and the plurality of source contact pieces to gate-drain capacity as measured between the gate contact and the drain contact is 250. Metal oxide semiconductor field effect transistor (MOSFET) structure in the range from 1000 to 1000. 24. The MOSFET structure of claim 24, wherein the ratio of gate-source capacity to gate-drain capacity ranges from 350 to 1000. 24. The MOSFET structure of claim 24, wherein the ratio of gate-source capacity to gate-drain capacity is between 250 and 750. 24. The MOSFET structure of claim 24, wherein the ratio of gate-source capacity to gate-drain capacity is between 300 and 1,000.

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