CN107863383B - Insulated gate bipolar transistor device structure with semi-closed primitive cell - Google Patents
Insulated gate bipolar transistor device structure with semi-closed primitive cell Download PDFInfo
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- CN107863383B CN107863383B CN201610840694.9A CN201610840694A CN107863383B CN 107863383 B CN107863383 B CN 107863383B CN 201610840694 A CN201610840694 A CN 201610840694A CN 107863383 B CN107863383 B CN 107863383B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
An insulated gate bipolar transistor device structure with a semi-closed primitive cell comprises an active groove and a virtual groove on the top; the active groove and the virtual groove form a semi-closed structure; a gap is formed between the active groove and the virtual groove; all trenches penetrate at least part of the CS layer to reach the N-drift layer and extend for a certain distance in part of the N-drift layer; a P-type base region is arranged above the CS layer; an N + emitter region and a P + contact region are also arranged on the P-type base region and are connected with the emitter electrode through a contact window.
Description
Technical Field
The invention belongs to the technical field of power Semiconductor devices, and relates to a Metal-Oxide-Semiconductor (MOS) gated bipolar device, in particular to an Insulated Gate Bipolar Transistor (IGBT).
Background
The MOS gate-controlled bipolar device not only has high power, but also can be controlled by small signals. IGBT structures are designed in a wide variety of ways, with the trench-FS (trench gate-field termination) structure being the most common result. A stripe cell structure is more common in the trench gate structure. There are also those that use a closed cell structure: such as square shaped cells, hexagonal cells, etc.
A typical IGBT structure with closed cells is shown in fig. 1. The structure includes: a backside metal collector 13, a P-type collector 12, an N-type field stop layer 11 and an N-drift region 10. The trench gate structure is composed of a polysilicon gate electrode 6 and a gate oxide layer 9 which are in contact with each other. The trench gate 6 forms a closed square and the polysilicon 6 is connected to the gate electrode. The top portion comprises an N + emitter region 1 and a P + contact region 2 which are connected to the emitter electrode via a contact window 20. The P-well region 7 is connected to the emitter electrode via the P + contact region 2. Also below the P-type well region is an N-type CS (carrier stored) layer 8. Because of the closed structure of fig. 1, the P-well region 7 and the CS layer 8 cannot be drawn, and specific locations thereof can be referred to fig. 2.
The closed cell structure shown in FIG. 1 has the advantages of reducing the electric field intensity in the cell and increasing the breakdown voltage compared with the stripe-shaped cell. However, the gate capacitance of this structure is relatively large. Therefore, there is a need for an improved IGBT structure with reduced gate capacitance.
Disclosure of Invention
In view of the above problems in the prior art, the present invention provides a semiconductor device structure that can reduce gate capacitance. And it can be applied to all MOS-gated bipolar devices including, but not limited to, Field-terminated IGBTs (Field-Stop IGBTs), reverse-conducting IGBTs (reverse-conducting IGBTs), reverse-blocking IGBTs (reverse-blocking IGBTs), and MOS-gated thyristors (MOS-controlled thyristors).
Specifically, the invention adopts the following technical scheme:
an insulated gate bipolar transistor device structure having a semi-closed cell, having a back side and a front side, the device comprising in order from the back side: the N-type collector electrode comprises a metal collector electrode 13, a P-type collector electrode 12, an N-type field stop layer 11 and an N-drift region 10, wherein an N-type CS layer 8 is arranged on the N-drift region 10 close to the front side; a P-type base region 7 is arranged above the CS layer 8; an N + emitter region 1 and a P + contact region 2 are also arranged on the P-type base region 7 and are connected with an emitter electrode through a contact window 20; the method is characterized in that: the top of the device comprises two types of trenches, namely an active trench 37 and a dummy trench 38; the trench structure of the active trench 37 is composed of active trench polysilicon 6 and a gate oxide layer 9 which are mutually contacted, wherein the active trench polysilicon 6 is connected with a gate electrode; the groove structure of the virtual groove 38 is composed of virtual groove polycrystalline silicon 3 and a gate oxide layer 9 which are mutually contacted, wherein the virtual groove polycrystalline silicon 3 is connected with an emitter electrode; the active trench 37 and the dummy trench 38 constitute a semi-closed structure; a gap 40 is arranged between the active trench 37 and the dummy trench 38; all trenches penetrate at least part of the CS layer 8 to reach the N-drift region 10 and extend a distance in part of the N-drift region 10.
In the above device, preferably, the width of the gap 40 between the active trench 37 and the dummy trench 38 is adjustable. More preferably, the width of the gap 40 between the active trench 37 and the dummy trench 38 is less than 2 μm. Further, the width of the gap 40 between the active trench 37 and the dummy trench 38 is less than 1 μm.
In the above device structure, the semi-closed structure constituted by the active trench 37 and the dummy trench 38 is a semi-closed square.
In another preferred embodiment, the semi-closed structure formed by the active trenches 37 and the dummy trenches 38 is in a semi-closed shape other than a semi-closed square. Other shapes of the semi-enclosed structure include semi-enclosed hexagons, triangles, circles, or the like.
In the above-described igbt device structure, the semiconductor material used is silicon, silicon carbide, or gallium nitride.
The invention has the beneficial effects that:
the gate capacitance of the device of the present invention is significantly reduced over the structure of figure 1.
Drawings
FIG. 1 is a block diagram of an IGBT with closed cells;
FIG. 2 is a diagram of an exemplary device of the present invention having semi-closed cells;
fig. 3 is a miller capacitance comparison graph of two IGBT structures (fig. 1 and 2 structures).
In the figure: 1. an N + emission region; 2. a P + contact region; 3. virtual groove polysilicon; 6. active trench polysilicon; 7. a P-type well region; 8. An N-type CS layer; 9. a gate oxide layer; 10. an N-drift region; 11. an N-type field stop layer; 12. a P-type collector; 13. a metal collector; 20. A contact window; 37. an active trench; 38. a dummy trench.
Detailed Description
The present invention adopts a new structure to solve the above-mentioned problems in the prior art.
Referring to fig. 2, the structure of the present invention is specifically:
a semiconductor device comprises a metal collector, a P-type collector, an N-type field stop layer and an N-drift region, wherein an N-type CS layer is arranged in the N-drift region close to the front surface; the top of the device comprises an active groove and a virtual groove; the groove structure of the active groove consists of active groove polycrystalline silicon and a gate oxide layer which are mutually contacted, wherein the active groove polycrystalline silicon is connected with the gate electrode; the groove structure of the virtual groove consists of virtual groove polycrystalline silicon and a gate oxide layer which are mutually contacted, wherein the virtual groove polycrystalline silicon is connected with an emitter electrode; the active groove and the virtual groove form a semi-closed square; a gap is formed between the active groove and the virtual groove; all the grooves penetrate at least part of the CS layer and part of the N-drift region; a P-type base region is arranged above the CS layer; an N + emitter region and a P + contact region are also arranged on the P-type base region and are connected with the emitter electrode through a contact window.
It should be understood that although the present invention is illustrated in fig. 2 as having a square-shaped semi-closed trench, it should be understood that in practical applications, the semi-closed structure may also have any other shape, such as a circle, a hexagon, a bar, a triangle, etc., as long as it is suitable for the intended application of the device, and the specific exemplary square shape illustrated in fig. 2 of the present invention should not limit the scope of the present invention.
In the semi-closed shape enclosed by the active trench and the dummy trench, the width of the gap between the active trench and the dummy trench can be adjusted. As a further improvement of the present invention, the width of the gap between the active trench and the dummy trench is less than 2 μm. As a further improvement of the present invention, the width of the gap between the active trench and the dummy trench is less than 1 μm.
As a further improvement of the invention, the active trenches and the dummy trenches form a semi-closed hexagon, a triangle, or other semi-closed shapes such as a circle.
As a further improvement of the invention, the semiconductor material used is silicon, silicon carbide, gallium nitride.
The present invention will be described in further detail with reference to the accompanying drawings.
A first example of the invention is shown in figure 2: the device comprises, in order from the back: the N-type collector electrode comprises a metal collector electrode 13, a P-type collector electrode 12, an N-type field stop layer 11 and an N-drift region 10, wherein an N-type CS layer 8 is arranged in the N-drift region 10 close to the front side; the top of the device comprises two types of trenches, namely an active trench 37 and a dummy trench 38; the trench structure of the active trench 37 is composed of active trench polysilicon 6 and a gate oxide layer 9 which are mutually contacted, wherein the active trench polysilicon 6 is connected with a gate electrode; the groove structure of the virtual groove 38 is composed of virtual groove polycrystalline silicon 3 and a gate oxide layer 9 which are mutually contacted, wherein the virtual groove polycrystalline silicon 3 is connected with an emitter electrode; the active trench 37 and the dummy trench 38 constitute a semi-closed square; a gap 40 is arranged between the active trench 37 and the dummy trench 38; all trenches penetrate at least part of the CS layer 8 and part of the N-drift region 10; a P-type base region 7 is arranged above the CS layer 8; an N + emitter region 1 and a P + contact region 2 are also arranged on the P-type base region 7 and are connected with an emitter electrode through a contact window 20.
In the above-described structure example, the width of the gap between the active trench and the dummy trench is variable, and may be varied according to design requirements.
In the above-mentioned structure example, the semi-closed shape formed by the active trenches and the dummy trenches may be a hexagon, a triangle, or other semi-closed shapes such as a circle.
In the case of manufacturing a device, silicon may be replaced with another semiconductor such as silicon carbide or gallium nitride.
The working principle of the invention is as follows:
in the conventional IGBT structure shown in fig. 1, all trenches are active trenches, and therefore the gate capacitance is large. In the structure shown in fig. 2, there is a dummy trench, and thus the gate capacitance is reduced.
To quantitatively compare the performance of several structures, three-dimensional numerical simulation analysis and comparison of the performance of the structure of FIG. 1 and the structure of FIG. 2 of the present invention were next performed. The doping parameters of each layer of the two simulated devices are completely the same, and the 1200V IGBT is taken as an example, the areas of the two simulated devices are both 1.5cm2。
Fig. 3 is a miller capacitance comparison graph of two IGBT structures (fig. 1 structure and fig. 2 structure of the present invention). It can be seen that the miller capacitance (Cres) at a junction temperature (Tj) of 125 ℃ is as follows.
The Cres (Vce =25V) value for the structure of fig. 1 is 591pF, while the Cres (Vce =25V) value for the structure of fig. 2 is 173 pF.
It can be seen that the structure of fig. 2 provided by the present invention can significantly reduce the miller capacitance compared to the structure of fig. 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
While the embodiments of the present invention have been described in detail with reference to the drawings, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (4)
1. An insulated gate bipolar transistor device structure having a semi-closed cell, having a back side and a front side, the device comprising in order from the back side: the N-type collector-based drift region comprises a metal collector (13), a P-type collector (12), an N-type field stop layer (11) and an N-drift region (10), wherein an N-type CS layer (8) is arranged on the part, close to the front surface, of the N-drift region (10); a P-type base region (7) is arranged above the CS layer (8); an N + emitter region (1) and a P + contact region (2) are also arranged on the P-type base region (7) and are connected with an emitter electrode through a contact window (20); the method is characterized in that: the top of the device comprises two types of trenches, namely an active trench (37) and a dummy trench (38); the trench structure of the active trench (37) is composed of active trench polysilicon (6) and a gate oxide layer (9) which are mutually contacted, wherein the active trench polysilicon (6) is connected with a gate electrode; the groove structure of the virtual groove (38) is composed of virtual groove polycrystalline silicon (3) and a gate oxide layer (9) which are mutually contacted, wherein the virtual groove polycrystalline silicon (3) is connected with an emitter electrode; the active grooves (37) and the virtual grooves (38) form a semi-closed structure, and the semi-closed structure is semi-closed square, hexagonal, triangular or circular; a gap (40) is arranged between the active groove (37) and the virtual groove (38); the width of the gap (40) between the active trench (37) and the dummy trench (38) is variable and can be changed according to the design requirement; all trenches penetrate at least part of the CS layer (8) to the N-drift region (10) and extend a distance in part of the N-drift region (10).
2. The structure of claim 1, wherein the structure of the igbt device with the semi-closed cell comprises: the width of the gap (40) between the active trench (37) and the dummy trench (38) is less than 2 microns.
3. The structure of claim 2, wherein the structure of the igbt device with the semi-closed cell comprises: the width of the gap (40) between the active trench (37) and the dummy trench (38) is less than 1 micron.
4. The structure of claim 1, wherein the structure of the igbt device with the semi-closed cell comprises: the semiconductor material used is silicon, silicon carbide, gallium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610840694.9A CN107863383B (en) | 2016-09-22 | 2016-09-22 | Insulated gate bipolar transistor device structure with semi-closed primitive cell |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610840694.9A CN107863383B (en) | 2016-09-22 | 2016-09-22 | Insulated gate bipolar transistor device structure with semi-closed primitive cell |
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| CN107863383B true CN107863383B (en) | 2021-05-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109309086A (en) * | 2018-08-24 | 2019-02-05 | 电子科技大学 | A kind of cathode short circuit grid-controlled transistor layout design method |
| CN110429133B (en) * | 2019-07-17 | 2022-11-01 | 国电南瑞科技股份有限公司 | Insulated gate bipolar transistor |
| CN113394277B (en) * | 2020-03-11 | 2022-05-20 | 珠海格力电器股份有限公司 | Cell structure of trench gate IGBT (insulated gate bipolar translator), preparation method of cell structure and trench gate IGBT |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5003365A (en) * | 1988-06-09 | 1991-03-26 | Texas Instruments Incorporated | Bipolar transistor with a sidewall-diffused subcollector |
| KR0159073B1 (en) * | 1995-10-16 | 1998-12-01 | 김광호 | A trench dmos transistor and method of making the same |
| JP2003197912A (en) * | 2001-12-25 | 2003-07-11 | Toshiba Corp | Insulated gate semiconductor device |
| JP2004022941A (en) * | 2002-06-19 | 2004-01-22 | Toshiba Corp | Semiconductor device |
| US8441046B2 (en) * | 2010-10-31 | 2013-05-14 | Alpha And Omega Semiconductor Incorporated | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances |
| CN102194864B (en) * | 2011-05-09 | 2012-11-07 | 电子科技大学 | Groove-grid-type insulated gate bipolar transistor with body electrode |
| CN103956379B (en) * | 2014-05-09 | 2017-01-04 | 常州中明半导体技术有限公司 | Have and optimize the CSTBT device embedding primitive cell structure |
| CN104183634B (en) * | 2014-09-16 | 2017-07-21 | 株洲南车时代电气股份有限公司 | A kind of trench gate igbt chip |
| US9583605B2 (en) * | 2015-02-05 | 2017-02-28 | Changzhou ZhongMin Semi-Tech Co. Ltd | Method of forming a trench in a semiconductor device |
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