CN104183634B - A kind of trench gate igbt chip - Google Patents
A kind of trench gate igbt chip Download PDFInfo
- Publication number
- CN104183634B CN104183634B CN201410473229.7A CN201410473229A CN104183634B CN 104183634 B CN104183634 B CN 104183634B CN 201410473229 A CN201410473229 A CN 201410473229A CN 104183634 B CN104183634 B CN 104183634B
- Authority
- CN
- China
- Prior art keywords
- trench gate
- trench
- igbt chip
- gates
- intersection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001413 cellular effect Effects 0.000 claims abstract description 13
- 238000000926 separation method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000009826 distribution Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 18
- 238000002360 preparation method Methods 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 description 23
- 238000000034 method Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
The invention provides a kind of trench gate igbt chip, including several cellulars parallel with one another, each cellular includes I trench gates and ii trench gate, by the first conductivity regions domain separation between the trench gate, the ii groove is located at the side of the I grooves, the opposite side of the I trench gates is provided with the source area of emitter stage and the second conduction type, the trench gate igbt chip also includes：The ii I trench gates in first conductivity type regions are formed at, the straight line where the grid length of the ii I trench gates and the straight line intersection where the grid length of the ii trench gate.Compared to prior art, the trench gate igbt chip that the present invention is provided is prepared, the technology difficulty and cost of preparation will not be increased.Further, since increased ii I trench gates, add the groove density of trench gate igbt chip, be conducive to improving the pressure-resistant of igbt chip, power consumption and safety operation area performance.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of trench gate igbt chip.
Background technology
At present, most IGBT manufacturers all use trench gate structure technology, to obtain lower power consumption, higher power
Density, faster switching speed.
For trench gate igbt chip, in order to take into account the pressure-resistant of chip, power consumption and safety operation area performance, go out now
The trench gate igbt chip for being provided with empty grid is showed.In the structure of the igbt chip, grid is divided into regular grid and empty grid
Pole.Regular grid is used to carry out switch control, and empty grid is used to improving performance (such as conducting resistance, pressure-resistant and safe of chip
Workspace etc.).The diagrammatic cross-section for being provided with the trench gate igbt chip of empty grid is as shown in Figure 1.In the IGBT cores shown in Fig. 1
The structure cell of piece includes I grooves, ii groove and ii I grooves, and these three grooves are evenly distributed on chip internal.Its
In, emitter stage is provided with the inside of I grooves, so I trench gates are the regular grid of chip, and ii groove and ii I
Groove is located at the outside of I grooves, and does not draw emitter stage in the both sides of ii groove and ii I grooves, so the
II grooves and the empty grid that ii I grooves are chip.
In order to further lift the performance of igbt chip, wherein, a kind of method is the density of the empty grid of increase.At present, can be with
Increase the density of empty grid by the following method.Specific method is as follows：
Continue to increase the quantity of empty grid in direction of the outside of regular grid along original empty grid：In cellular size constancy
In the case of, mean that technology feature size diminishes in the quantity of the empty grid of outside increase of regular grid, and minimum process must
So limited by manufacturing process and equipment, therefore, the quantity increase of empty grid is limited, and the diminution meeting of technology feature size
Increase the technology difficulty and cost of igbt chip.
However, the developing direction that groove density is current trench grid is improved, therefore, it is necessary to provide a kind of trench gate
The new construction of igbt chip, to realize on the basis of technology difficulty and cost is not increased, improves the groove density of igbt chip.
The content of the invention
In view of this, the invention provides a kind of trench gate igbt chip, technology difficulty and cost are not being increased to realize
On the basis of, further improve the groove density of trench gate igbt chip.
In order to reach foregoing invention purpose, present invention employs following technical scheme：
A kind of trench gate igbt chip, including several cellulars parallel with one another, each cellular include I trench gates and the
By the first conductivity regions domain separation between II trench gates, the trench gate, the ii groove is located at the one of the I grooves
Side, the source area of emitter stage and the second conduction type is provided with the opposite side of the I trench gates, the emitter stage and described
The source area of second conduction type is located in the first conduction type base region, and the trench gate igbt chip also includes：It is formed at institute
The ii I trench gates in the first conductivity type regions are stated, the straight line where the grid length of the ii I trench gates and the ii ditch
Straight line intersection where the grid length of groove grid；Wherein, first conduction type is opposite with second conduction type.
Preferably, the ii trench gate is connected with each other with the ii I trench gates.
Preferably, the ii trench gate and the ii I trench gates be it is multiple, it is any in the ii I grooves
One is connected with each other with ii trench gate described at least two.
Preferably, the ii I trench gates are multiple, and the spacing between every two neighboring ii I trench gates is identical.
Preferably, the ii trench gate is multiple, and the spacing between every two neighboring ii trench gate is identical.
Preferably, the groove width of each trench gate is identical, and/or, the gash depth phase of each trench gate
Together.
Preferably, the trench gate igbt chip includes substrate, and the trench gate is formed at the substrate interior, the ditch
Groove grid include the polysilicon being filled in groove, and insulator separation is passed through between the polysilicon and the substrate.
Preferably, the polysilicon being filled in the I trench gates is drawn out to the trench gate igbt chip surface, filling
Polysilicon in the ii groove and the ii I grooves is in suspended state.
Preferably, first conductivity type regions are divided into several the first conduction type subregions, each described
The subregion of first conduction type is in suspended state.
Preferably, the ii trench gate and the ii I trench gates are multiple, and the grid of the ii I trench gates are long
Multiple intersections, the multiple intersection's bag are formed during straight line intersection where the grid length of the straight line at place and the ii groove
Multiple first intersections and multiple second intersections are included, in first intersection, ii I trench gates and the ii trench gate
It is connected with each other, in second intersection, the ii I trench gates and the ii trench gate are mutually isolated.
Preferably, second intersection is multiple, and the multiple second intersection is in array distribution, the array element
Be shaped as rectangle or rhombus；
2 times of spacing between a length of two neighboring ii trench gate in one side of the rectangle, a length of phase in another side
2 times of spacing between adjacent two ii I trench gates；
The long axis length of the rhombus is 4 times of the spacing between the two neighboring ii trench gate, and minor axis length is
2 times of spacing between the two neighboring ii I trench gates, or, the long axis length of the rhombus is two neighboring described
4 times of spacing between ii I trench gates, minor axis length is 2 times of the spacing between the two neighboring ii trench gate.
Preferably, first conductivity type regions are divided into several the first conduction type subregions, the groove
Grid igbt chip also includes：The Windows of second intersection are arranged on, the Windows are used to hand over described second
Each the first conduction type subregion on periphery leads to chip surface at remittance.
Preferably, the Windows region is the first conduction type doped region, the first conduction type doped region
Doping concentration is more than 5e19/cm3。
Preferably, opening is provided with the Windows region, described be open is used for second intersection periphery
Each the first conduction type subregion lead to chip surface.
Compared to prior art, the invention has the advantages that：
The trench gate igbt chip that the present invention is provided, including I trench gates, ii trench gate and ii I trench gates, it is described
Ii trench gate and ii I trench gates are the empty grid of igbt chip.Compared to trench gate igbt chip of the prior art
Structure, the trench gate igbt chip provided in the present invention adds ii I trench gates, so as to add trench gate igbt chip
Groove density.Due to the straight line intersection where the grid length of the straight line where the grid length of ii I trench gates and the ii trench gate,
That is, being upwardly formed ii I trench gates in the side different from ii trench gate.So, compared to prior art, set up
Although ii I trench gates add groove density, but do not reduce the spacing between ii trench gate, so, preparing this
When the trench gate igbt chip provided is provided, existing technology feature size can be used, technology feature size will not be subtracted
It is small.Thus, compared to prior art, the trench gate igbt chip that the present invention is provided is prepared, the technology difficulty of preparation will not be increased
And cost.Further, since increased ii I trench gates, add the groove density of trench gate igbt chip, be conducive to improving
The pressure-resistant of igbt chip, power consumption and safety operation area performance.
Brief description of the drawings
In order to which the technical scheme of prior art and embodiment of the invention is expressly understood, it is described below existing
The accompanying drawing used when the embodiment of technology and the present invention does a brief description.It should be evident that these accompanying drawings are only these
The section Example accompanying drawing of invention, those of ordinary skill of the present invention on the premise of not paying creative work, can also obtain
Other accompanying drawings.
Fig. 1 is the cross-sectional view of half structure cell of trench gate igbt chip of the prior art；
Fig. 2 is the planar structure schematic diagram of half structure cell of the trench gate igbt chip that the embodiment of the present invention one is provided；
Fig. 3 (a) and Fig. 3 (b) are trench gate igbt chip shown in Fig. 2 respectively along x-x ' directions and cuing open along y-y ' directions
Face structural representation；
Fig. 4 is the planar structure schematic diagram of half structure cell of the trench gate igbt chip that the embodiment of the present invention two is provided；
Fig. 5 (a) and Fig. 5 (b) are trench gate igbt chip shown in Fig. 4 respectively along x-x ' directions and cuing open along y-y ' directions
Face structural representation；
Fig. 6 is the planar structure schematic diagram of the structure cell for the trench gate igbt chip that the embodiment of the present invention two is provided；
Hole and electronics flow to schematic diagram between the emitter stage of two adjacent cellulars when Fig. 7 is igbt chip conducting；
Fig. 8 is the rough schematic view of the empty grid structure for the trench gate igbt chip that the embodiment of the present invention three is provided；
Fig. 9 (1) and Fig. 9 (2) are the partial enlarged drawing of the intersection I1 and I2 shown in Fig. 8；
Figure 10 (1) to Figure 10 (3) is distribution schematic diagram of second intersection on chip.
Embodiment
The embodiment to the present invention is described below in conjunction with the accompanying drawings.
It should be noted that trench gate igbt chip includes several cellulars in parallel, the structure of each cellular is generally
It is identical.The trench gate igbt chip that the present invention is provided is mainly the improvement carried out to the structure cell of chip.For protrusion
The improvement of the present invention, embodiment of the invention highlights the structure cell of igbt chip and related to structure cell
Some structures, other structures being not directly dependent upon with structure cell do not describe in detail in embodiments of the present invention.
Embodiment one
Fig. 2 is the floor map of half structure cell of the trench gate igbt chip that the embodiment of the present invention one is provided, Fig. 3
(a) be trench gate igbt chip shown in Fig. 2 half structure cell the diagrammatic cross-section along x-x ' directions, Fig. 3 (b) is Fig. 2
The diagrammatic cross-section along y-y ' directions of half structure cell of shown trench gate igbt chip.
It should be noted that the trench gate igbt chip described in embodiment one is illustrated by taking N-type substrate material as an example
's.
As shown in Fig. 2 half structure cell of the trench gate igbt chip that the embodiment of the present invention one is provided includes I trench gates
201 and ii trench gate 202, isolated between I trench gates 201 and ii trench gate 202 by p type island region domain 203.Half cellular
Structure also includes emitter stage 204 and N+ source areas 205, wherein, N+ source areas 205 are located at the emitter stage 204 and I grooves
Between 201.Wherein, emitter stage 204 and N+ source areas 205 are located at the side of I trench gates 201, and ii trench gate 202 is located at the
The opposite side of I trench gates 201.
Referring to shown in Fig. 3 (a) and Fig. 3 (b), emitter stage 204 and N+ source areas 205 are arranged in P- bases 206.
As shown in Fig. 2 and Fig. 3 (b), igbt chip provided in an embodiment of the present invention still further comprises ii I trench gates
207.As shown in Fig. 2 the straight line where the grid length of ii I trench gates 207 and the straight line where the grid length of ii trench gate 202
It is intersecting.That is, direction of the grid length of ii I trench gates 207 on igbt chip is not the grid along ii trench gate 202
The long direction on igbt chip, but intersect with the direction of ii trench gate 202, so, the setting of ii I trench gates will not
Reduce the spacing of ii trench gate 202.
With continued reference to shown in Fig. 3 (a) and Fig. 3 (b), the polysilicon 301 in I trench gates 201 is by the polycrystalline of chip surface
Silicon is drawn out to chip surface, and the side of the I trench gates 201 is provided with emitter stage and N+ source areas, the I trench gates
201 be the regular grid of trench gate igbt chip.And the polysilicon 301 in ii trench gate 202 and ii I trench gates 207 does not have
Chip surface is drawn out to, the polysilicon in two groove is in suspended state, so ii trench gate 202 and ii I grooves
Grid 207 are suspended grid.And emitter stage is not provided with around the ii trench gate 202 and ii I trench gates 207, so,
Ii trench gate 202 and the empty grid that ii I trench gates 207 are igbt chip.
It should be noted that under normal circumstances, those skilled in the art, in order to increase empty gate groove density, are typically in original
Carry out in the same direction of empty gate groove to set more empty gate grooves.And the present invention breaks through the usual of those skilled in the art and thought
Method, sets more empty gate grooves from another direction, realizes in the case where not reducing ditch separation, increase groove is close
Degree.This set method has significant progress, is in particular in：
1st, due to no diminution ditch separation, so, the technology feature size for preparing the igbt chip does not also reduce, institute
With the quantity of ii I trench gates set up by the smaller of the limit of technology feature size.
2nd, compared to prior art, the trench gate igbt chip that the embodiment of the present invention one is provided is prepared, equipment will not be increased
Technology difficulty and cost.
3rd, furthermore, it is possible to be that the preparation of the higher igbt chip of groove density can be achieved using existing equipment.
4th, further, since being that more empty gate grooves are set up in the side different from original empty grid, so, this increase
The method to set up of empty gate groove density will not be limited by technology feature size and cellular size.Compared to of the prior art
Method, it is higher that the method to set up can reach groove density.
Shown, I trench gates 201, ii trench gate 202 and the shape of ii I trench gates 207 referring to Fig. 3 (a) and Fig. 3 (b)
Into in the inside of substrate 300, three trench gates 201,202 and 207 include the polysilicon 301 being filled in groove, and
Isolated between polysilicon 301 and substrate 300 by insulating barrier 302, the insulating barrier 302 can be earth silicon material.
It is easier in realization for the preparation technology of chip, preferably I trench gates, ii trench gate and ii I ditches
The groove of groove grid has identical gash depth and groove width.
In addition, in embodiments of the present invention, as shown in Fig. 3 (a) and Fig. 3 (b), p type island region domain 203 and P- bases 206 are mixed
Miscellaneous concentration and junction depth are preferably identical.
It should be noted that in embodiments of the present invention, straight line and ii ditch where the grid length of ii I trench gates 207
Straight line preferred vertical where the grid length of groove grid 202 intersects.In addition, in embodiments of the present invention, the grid of ii I trench gates 207
Straight line where length and the straight line intersection where the grid length of ii trench gate 202, are not meant to ii I trench gates 207 and the
II trench gates 202 interconnect.In fact, in embodiments of the present invention, ii I trench gates 207 and ii ditch
Groove grid 202 can interconnect, and can also be not attached to together.When ii trench gate 202 is multiple, ii I
Trench gate 207 optionally can be connected with part ii trench gate 202.
In addition, in order to strengthen conductivity modulation effect of the hole in p type island region domain 203 when chip is in the conduction state, using
Suspended state is preferably in the p type island region domain 203 of isolated groove grid.I.e.：P type island region domain 203 is not drawn out to chip surface,
Grounding is not carried out, in electrical connection, p type island region domain 203 is in suspended state.
The structure of trench gate igbt chip described in above-described embodiment is with an ii trench gate and an ii I groove
Illustrated exemplified by grid.In fact, the groove density in order to increase structure cell, ii trench gate and ii I trench gates are equal
Can be multiple.Referring specifically to embodiment two.
Embodiment two
The structure cell of trench gate igbt chip described in embodiment two and the trench gate igbt chip described in embodiment one
Structure cell have many similarities, for the sake of brevity, the present embodiment is only stressed to its difference.
Fig. 4 is the floor map of half structure cell of the trench gate igbt chip that the embodiment of the present invention two is provided, Fig. 5
(a) be trench gate igbt chip shown in Fig. 4 half structure cell the diagrammatic cross-section along x-x ' directions, Fig. 5 (b) is Fig. 4
The diagrammatic cross-section along y-y ' directions of half structure cell of shown trench gate igbt chip.
As shown in figure 4, half structure cell of the trench gate igbt chip described in embodiment two includes 3 ii trench gates
202 and 4 ii I trench gates 207, the ii trench gate 202 is respectively the trench gate of ii -1 2021, the trench gate of ii -2
2022nd, the trench gate of ii -3 2023.The ii I trench gates 207 are respectively ii I-1 trench gates 2071, ii I-2 trench gates
2072nd, ii I-3 trench gates 2073, ii I-4 trench gates 2074.In the embodiment of the present invention one, per two neighboring ii ditch
Spacing d1 between groove grid is preferably identical, and the spacing d2 between every two neighboring ii I trench gates is it is also preferred that identical.Further
Ground, per the spacing d1 between two neighboring ii trench gate and per two neighboring ii I trench gates between spacing d2 it is also preferred that
Identical, this structure can be under the technique of minimum feature so that the density of trench gate reaches maximum.Thus, advantageously reduce
The conducting resistance of chip, improves the pressure-resistant performance of chip.
It is easier in preparation technology realization to make chip, preferably I trench gates, ii trench gate and ii I grooves
The groove of grid has identical gash depth and groove width.And it is further preferred that the adjacent ii groove of any two
Spacing between the adjacent ii I trench gates of grid, any two is equal.Because, it can so cause at each groove
In under identical etching atmosphere, therefore, the uniformity of technique is fine.Shape, the groove of each groove such as the cell wall of each groove
The radian at bottom is basically identical.
In embodiments of the present invention, preferably any one ii I trench gates 207 with least two ii trench gates 202
Connection.In the planar structure shown in Fig. 4, any one ii I trench gates 207 are connected with three ii trench gates 202, from
And realize the interconnection of ii I trench gates 207 and ii trench gate 202.
It should be noted that when being not provided with ii I trench gates 207 on igbt chip, for isolating ii trench gate
202 p type island region domain 203 is integral region, but when be provided with igbt chip be connected with each other with ii trench gate 202 the
After III trench gates 207, ii trench gate 202 and ii I trench gates 207 constitute the network structure of empty grid.Fig. 6 is shown
The floor map of one structure cell of the igbt chip with ii trench gate and ii I trench gates.Can from Fig. 6
Go out, after ii trench gate 202 and ii I trench gates 207 constitute the network structure of empty grid, if p type island region domain 203 is split into
Dry mutually isolated p-type subregion.It will be understood that passing through ii trench gate 202 and ii I between adjacent p-type subregion
Trench gate 207 is realized mutually isolated.That is, each p-type subregion is surrounded by empty gate groove grid.
When each all p-type subregion are in suspended state, when chip is turned on, stronger hole barrier can be formed
Effect.Specific reason is as follows：
Hole and electronics flow to schematic diagram between the emitter stage of two adjacent cellulars when Fig. 7 is igbt chip conducting.
From fig. 6 it can be seen that when chip is turned on, converge from back injected holes with the electronics from Channeling implantation in N- bases,
Conductance modulation is formed, conducting resistance is reduced.The concentration of electron-hole pair is bigger, and conductance modulation is stronger.Motion road from hole
Footpath understands, it is curve, it is necessary to bypassing trench gate can just be extracted away, exactly the process (hole barrier) of this " around ", makes
Accumulated into hole at chip front side near surface, that is, improve the hole concentration at chip front side surface, and in order to maintain
Charge balance, then have more electronics from Channeling implantation, therefore just enhance conductance modulation.If in the emitter stage of two cellulars
There are multiple empty grid between emitter stage, then the moving line in hole is accomplished by bypassing multiple empty grid, further around regular grid is crossed,
It can be extracted, therefore can just accumulate more holes on the way, therefore say that empty grid can strengthen conductance modulation.And empty grid
Groove density is bigger, and conductance modulation is stronger.
In addition, when each all p-type subregion be in suspended state when, can speed up igbt chip reversely it is pressure-resistant when
Depleted of electrons, therefore, it is possible to improve the pressure-resistant performance of chip.Because：Empty grid structure can reduce suspension p-type subregion
Electric-field intensity.When being provided with empty grid structure in igbt chip, the electric field concentration phenomenon of regular grid bottom can be eased, because
And be conducive to improving the pressure-resistant performance of chip.And the empty grid density set is bigger, and the raising of pressure-resistant performance is more obvious.
It should be noted that the igbt chip described in above-described embodiment two includes 3 ii trench gates and 4 ii I
Trench gate, in fact, above-described embodiment is only an example of the embodiment of the present invention, should not be construed as to the embodiment of the present invention
Limitation.In fact, including n (n >=1, n is integer) individual ii trench gate and m (m >=1, m is integer) individual ii I trench gates
Igbt chip is within the scope of the present invention.
P type island region domain 203 is divided into several mutually isolated p-type sub-districts in igbt chip described in above-described embodiment two
Domain, and these p-type subregions are in suspended state.When chip is turned on, conductivity modulation effect, reduction conducting can be strengthened
Resistance, but when chip is turned off, a large amount of holes being injected into raceway groove add the extraction time, reduce turn-off speed, increase
Add turn-off power loss, have impact on the safety operation area performance of chip.In order to overcome drawbacks described above, present invention also offers embodiment
Three.
Embodiment three
Turn-off speed can be reduced when being in suspended state due to p-type subregion, increases turn-off power loss, the safety of chip is influenceed
Workspace performance.It is therefore desirable to which p-type subregion is drawn out into the grounding connection of chip surface realization electrically.But, when empty grid
After trench gate formation network structure, each p-type subregion being divided to form is mutually isolated, if each p-type subregion is equal
Electric grounding connection is realized, conventionally, it is necessary to set one on each suspension p-type subregion by p-type sub-district
Domain is drawn out to the Windows of chip surface, so may result under the limitation of equipment and technological level, can be because extraction window
The presence of mouth causes the groove number in unit area to reduce, that is, reduces groove density, so as to be unfavorable for reducing the conducting of chip
Resistance.
In order to not reduce the groove density of the trench gate igbt chip described in embodiment two, the embodiment of the present invention three is carried
A kind of new construction of trench gate igbt chip is supplied.
Trench gate igbt chip described in embodiment three has many similar to the trench gate igbt chip described in embodiment two
Part, for the sake of brevity, the present embodiment are only stressed to its difference.Similarity refers to embodiment two
Description.
In embodiments of the present invention, the empty grid knot being interconnected to constitute by ii trench gate 202 and ii I trench gates 207
Structure is network structure.It should be noted that in embodiments of the present invention, the institute of ii I trench gates 207 not with its grid length direction
There is ii trench gate 202 mutually to link together, but selectively linked together with part ii trench gate 202.Implement
The plan and profile of the structure cell of trench gate igbt chip described in example three and the igbt chip described in embodiment two
The plan and profile of structure cell are essentially identical, for the sake of brevity, the present embodiment be not described in detail its plan and
Profile, specifically refers to the accompanying drawing of embodiment two.
For the empty grid structure of network structure being more clearly understood from the embodiment of the present invention, below by the letter of empty grid structure
Turn to structure as shown in Figure 8.In the empty grid structure shown in Fig. 8, every straight line represents a trench gate, horizontal direction it is straight
Line is ii I trench gates, and the straight line of vertical direction is ii trench gate, and the grid of the bearing of trend respective grooves of every straight line are rectangular
To.From figure 8, it is seen that represent ii I trench gates straight line with expression ii trench gate straight line intersection when form it is multiple
Intersection point, these intersection points are the intersection of ii I trench gates and ii trench gate.In fig. 8, the white space between straight line is
P type island region domain 203 on igbt chip, it is divided into several p-type subregions by ii I trench gates.
It should be noted that in embodiments of the present invention, these intersections of formation include the first intersection and second and handed over
At remittance, in the first intersection, ii I trench gates and ii trench gate interconnect, and are real intersection, and are handed over second
At remittance, ii I trench gates with ii trench gate is mutually isolated be not attached to together with, be empty intersection.In the structure shown in Fig. 8
In, the intersection marked with triangle is the second intersection, and the intersection not marked with triangle is the first intersection.
In embodiments of the present invention, shown in partial enlarged drawing such as Fig. 9 (1) of the first intersection I1 shown in Fig. 8, second hands over
At remittance shown in I2 partial enlarged drawing such as Fig. 9 (2).
In Fig. 9 (1), ii I trench gates and ii trench gate interconnect, on the first intersection periphery
Four p-type subregions a, b, c, d are mutually isolated.This four p-type subregions are separate.
In the position of the second intersection shown in Fig. 9 (2), ii I trench gates and ii trench gate are not attached to together,
Four p-type subregion a ', b ', c ', the d ' on the second intersection periphery link together in the second intersection.That is,
Second intersection, four p-type subregion a ', b ', c ', the d ' on periphery form local interlinkage.Formed to split in chip
All p-type subregions realize electric grounding connection, in the igbt chip in the embodiment of the present invention three, in addition to：If
Put the Windows w in the second intersection.The p-type subregion on its periphery can be drawn out to chip surface by Windows w, real
Now electric grounding connection.
In the second intersection, because four p-type subregion a ', b ', c ', the d ' on periphery form local interlinkage, so, P
Type subregion a ', b ', c ', d ' are overall p type island region domain, and therefore, the Windows w for being arranged on the second intersection can be by four
Individual p-type subregion a ', b ', c ', d ' are drawn out to chip surface.It is required to compared to each p-type subregion in the prior art
The scheme that one Windows is drawn, igbt chip provided in an embodiment of the present invention reduces the quantity of Windows, Neng Goushi
In the case of not reducing groove density now, all p-type subregions are drawn into chip surface.
With continued reference to Fig. 9 (2), the Windows w and ii trench gate and ii I trench gates of the second intersection are arranged on not
It is connected.
Describe for convenience, ii trench gate and ii I trench gates are referred to as empty grid, it is specific as one of the present invention
The spacing at embodiment, Windows w edges and the edge of empty gate groove grid is more than or equal to the width of empty gate groove.
The shape of the Windows can have any shape, when the Windows are when being shaped as square, the extraction window
The mouth w length of side is 2-4 times of empty gate groove width.It is high concentration P+ doping in Windows w, doping concentration is more than 5e19/
cm3, to reduce the contact resistance of extraction.Opening w1 is set in Windows w center, neighbouring is hanged by opening w1
Floating p-type subregion is drawn out to chip surface, facilitates grounding.In embodiments of the present invention, the opening w1 of setting size is
The 50%~80% of Windows w regions.
It should be noted that any one when the second intersection can be for ii trench gate and intersecting ii I trench gates
Intersection.But, in order to can be achieved with all p-type subregions being drawn out to core using Windows as few as possible
Piece surface is grounded connection, in embodiments of the present invention, and the location of second intersection can make the p-type of every four neighbours
Subregion formation local interlinkage.It is further preferred that distribution of second intersection on chip is in array distribution, wherein, array
Unit is shaped as rectangle or rhombus.When setting Windows in the second intersection of this distributed architecture, it can realize every
The p-type subregion of four mutual near neighbors shares a Windows.
When array element is when being shaped as rectangle, floor map such as Figure 10 (1) of the empty grid structure of igbt chip is shown,
Now, 2 times of the spacing between a length of two neighboring ii trench gate in one side of the rectangle, another side a length of adjacent two
2 times of spacing between the individual ii I trench gates.Further, when the spacing between two neighboring ii trench gate is equal to
During spacing between the two neighboring ii I trench gates, array element is shaped as square.
When array element is when being shaped as rhombus, floor map such as Figure 10 (2) and figure of the empty grid structure of igbt chip
Shown in 10 (3).When the shape of array element of the shape as shown in Figure 10 (2) of array element, the major axis of the rhombus parallel to
Ii trench gate, now, the long axis length of rhombus are 4 times of the spacing between the two neighboring ii trench gate, and short axle is long
Spend for 2 times of the spacing between the two neighboring ii I trench gates.
When array element of the shape as shown in Figure 10 (3) of array element, the major axis of rhombus is parallel to ii I grooves
Grid, now, the long axis length of rhombus are 4 times of the spacing between the two neighboring ii I trench gates, and minor axis length is adjacent
2 times of spacing between two ii trench gates.
It should be noted that what the igbt chip described in above-described embodiment one to three illustrated by taking N-type substrate material as an example,
In fact, as the extension embodiment of the present invention, igbt chip can also be with P type substrate material.When igbt chip is P-type material
When, various conductivity type regions described above need to make corresponding change.Due to P type substrate material formation igbt chip with
The igbt chip of N-type substrate material formation is the difference of conduction type, and other structures are identical, those skilled in the art only need by
Conduction type does the igbt chip that corresponding conversion can obtain P type substrate material, so, it is for the sake of brevity, no longer detailed herein
The igbt chip of thin description P type substrate formation.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (13)
1. a kind of trench gate igbt chip, including several cellulars parallel with one another, each cellular include I trench gates and ii
By the first conductivity regions domain separation between trench gate, the trench gate, the ii groove is located at the one of the I grooves
Side, the source area of emitter stage and the second conduction type is provided with the opposite side of the I trench gates, the emitter stage and described
The source area of second conduction type is located in the first conduction type base region, it is characterised in that the trench gate igbt chip is also wrapped
Include：It is formed at the ii I trench gates in first conductivity type regions, the straight line where the grid length of the ii I trench gates
With the straight line intersection where the grid length of the ii trench gate；Wherein, first conduction type and second conduction type
Conversely；
The ii trench gate and the ii I trench gates be it is multiple, straight line where the grid length of the ii I trench gates with
Multiple intersections are formed during straight line intersection where the grid length of the ii groove, the multiple intersection includes multiple first and handed over
At remittance and multiple second intersections, in first intersection, ii I trench gates are connected with each other with the ii trench gate,
Second intersection, the ii I trench gates and the ii trench gate are mutually isolated.
2. trench gate igbt chip according to claim 1, it is characterised in that the ii trench gate and the ii I
Trench gate is connected with each other.
3. trench gate igbt chip according to claim 1, it is characterised in that the ii trench gate and the ii I
Trench gate is multiple, and any one in the ii I grooves is connected with each other with ii trench gate described at least two.
4. trench gate igbt chip according to claim 1 or 2, it is characterised in that the ii I trench gates be it is multiple,
Spacing between per the two neighboring ii I trench gates is identical.
5. trench gate igbt chip according to claim 1 or 2, it is characterised in that the ii trench gate be it is multiple, often
Spacing between two neighboring ii trench gate is identical.
6. the trench gate igbt chip according to claim any one of 1-3, it is characterised in that the ditch of each trench gate
Well width is identical, and/or, the gash depth of each trench gate is identical.
7. the trench gate igbt chip according to claim any one of 1-3, it is characterised in that the trench gate igbt chip
Including substrate, the trench gate is formed at the substrate interior, and the trench gate includes the polysilicon being filled in groove, described
Pass through insulator separation between polysilicon and the substrate.
8. trench gate igbt chip according to claim 7, it is characterised in that be filled in many in the I trench gates
Crystal silicon is drawn out to the trench gate igbt chip surface, is filled in the polysilicon in the ii groove and the ii I grooves
In suspended state.
9. trench gate igbt chip according to claim 3, it is characterised in that first conductivity type regions are divided
Into several the first conduction type subregions, the subregion of each first conduction type is in suspended state.
10. igbt chip according to claim 1, it is characterised in that second intersection be it is multiple, the multiple the
Two intersections are in array distribution, and the array element is shaped as rectangle or rhombus；
2 times of spacing between a length of two neighboring ii trench gate in one side of the rectangle, another side a length of adjacent two
2 times of spacing between the individual ii I trench gates；
The long axis length of the rhombus is 4 times of the spacing between the two neighboring ii trench gate, and minor axis length is adjacent
2 times of spacing between two ii I trench gates, or, the long axis length of the rhombus is the two neighboring ii I
4 times of spacing between trench gate, minor axis length is 2 times of the spacing between the two neighboring ii trench gate.
11. the trench gate igbt chip according to claim any one of 1-3, it is characterised in that first conduction type
Region is divided into several the first conduction type subregions, and the trench gate igbt chip also includes：It is arranged on described second
The Windows of intersection, the Windows are used for each the first conduction type subregion on second intersection periphery
Lead to chip surface.
12. trench gate igbt chip according to claim 11, it is characterised in that led for first in the Windows region
Electric type doped region, the doping concentration of the first conduction type doped region is more than 5e19/cm3。
13. trench gate igbt chip according to claim 11, it is characterised in that be provided with the Windows region
Opening, it is described to be open for each the first conduction type subregion on second intersection periphery to be led into chip surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410473229.7A CN104183634B (en) | 2014-09-16 | 2014-09-16 | A kind of trench gate igbt chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410473229.7A CN104183634B (en) | 2014-09-16 | 2014-09-16 | A kind of trench gate igbt chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104183634A CN104183634A (en) | 2014-12-03 |
| CN104183634B true CN104183634B (en) | 2017-07-21 |
Family
ID=51964546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410473229.7A Active CN104183634B (en) | 2014-09-16 | 2014-09-16 | A kind of trench gate igbt chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104183634B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160247879A1 (en) * | 2015-02-23 | 2016-08-25 | Polar Semiconductor, Llc | Trench semiconductor device layout configurations |
| CN105226090B (en) * | 2015-11-10 | 2018-07-13 | 株洲中车时代电气股份有限公司 | A kind of igbt and preparation method thereof |
| CN107800294B (en) * | 2016-08-31 | 2019-08-13 | 台达电子企业管理（上海）有限公司 | Crisscross parallel circuit, power integration module and power integrated chip |
| US10620654B2 (en) | 2016-08-31 | 2020-04-14 | Delta Electronics (Shanghai) Co., Ltd | Alternatingly-switched parallel circuit, integrated power module and integrated power package |
| CN107863383B (en) * | 2016-09-22 | 2021-05-07 | 常州中明半导体技术有限公司 | Insulated gate bipolar transistor device structure with semi-closed primitive cell |
| CN108231757B (en) * | 2016-12-14 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN110473918A (en) * | 2019-08-30 | 2019-11-19 | 丽晶美能（北京）电子技术有限公司 | Channel grid structure I GBT |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060747A (en) * | 1997-09-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN1879222A (en) * | 2003-11-12 | 2006-12-13 | 丰田自动车株式会社 | Trench gate field effect devices |
| CN102792448A (en) * | 2010-03-09 | 2012-11-21 | 富士电机株式会社 | Semiconductor device |
| CN203134807U (en) * | 2012-11-23 | 2013-08-14 | 中国科学院微电子研究所 | Insulated gate bipolar transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000058823A (en) * | 1998-08-13 | 2000-02-25 | Toshiba Corp | Semiconductor device and its manufacture |
-
2014
- 2014-09-16 CN CN201410473229.7A patent/CN104183634B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060747A (en) * | 1997-09-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN1879222A (en) * | 2003-11-12 | 2006-12-13 | 丰田自动车株式会社 | Trench gate field effect devices |
| CN102792448A (en) * | 2010-03-09 | 2012-11-21 | 富士电机株式会社 | Semiconductor device |
| CN203134807U (en) * | 2012-11-23 | 2013-08-14 | 中国科学院微电子研究所 | Insulated gate bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104183634A (en) | 2014-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104183634B (en) | A kind of trench gate igbt chip | |
| CN104882477B (en) | Trench gate IGBT device and its manufacture method | |
| JP2000031497A (en) | Lateral igbt and manufacture thereof | |
| CN107293579A (en) | A kind of superjunction IGBT with low conduction voltage drop | |
| CN108933169A (en) | Power semiconductor device with dV/dt controllability and cross trench arrangement | |
| CN103035677B (en) | Super-junction structures, super junction MOS transistor and manufacture method thereof | |
| CN109216432A (en) | Slot type power device and preparation method thereof | |
| CN102130150A (en) | Junction terminal structure of semiconductor device | |
| CN105870178A (en) | Bi-directional insulated gate bipolar transistor (IGBT) device and fabrication method thereof | |
| CN105914231B (en) | Charge storage type IGBT and its manufacturing method | |
| CN105448997B (en) | Improve the superjunction MOS device and its manufacturing method of reverse recovery characteristic and avalanche capacity | |
| CN107170688A (en) | A kind of slot type power device and preparation method thereof | |
| CN106783611A (en) | A kind of trench gate IGBT with the embedded diode of grid and preparation method thereof | |
| CN108091683A (en) | Super-junction structure of semiconductor power device and preparation method thereof | |
| CN109216452A (en) | Slot type power device and preparation method thereof | |
| CN108376713A (en) | A kind of semiconductor devices and preparation method thereof with super-junction structure | |
| CN106847808A (en) | A kind of domain structure for improving super node MOSFET UIS abilities | |
| CN203260580U (en) | Semiconductor device with a plurality of transistors | |
| CN206116403U (en) | Optimize super knot semiconductor device of switching characteristic | |
| CN106298898A (en) | Vertical conduction power device and preparation method thereof | |
| CN107785413A (en) | Transistor device with high current robustness | |
| CN107994067A (en) | The terminal structure and preparation method thereof of semiconductor power device, semiconductor power device | |
| CN107275396A (en) | Trench gate IGBT and manufacturing method thereof | |
| CN114664920A (en) | Super-junction RC-IGBT device structure | |
| CN107785436A (en) | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee after: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CSR TIMES ELECTRIC Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200930 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |