CN104183634B - A kind of trench gate igbt chip - Google Patents

Abstract

The present invention provides a trench gate IGBT chip, comprising several cells connected in parallel, each cell including the first trench gate and the second trench gate, the trench gates are separated by the first conductivity type Regional isolation, the II trench is located on one side of the I trench, and an emitter and a source region of the second conductivity type are arranged on the other side of the gate of the I trench, and the trench The gate IGBT chip further includes: a third trench gate formed in the first conductivity type region, the straight line where the gate length of the third trench gate is located and the straight line where the gate length of the second trench gate is located intersect. Compared with the prior art, the preparation of the trench gate IGBT chip provided by the present invention does not increase the difficulty and cost of the preparation process. In addition, due to the addition of the third trench gate, the trench density of the trench gate IGBT chip is increased, which is conducive to improving the withstand voltage, power consumption and safe operating area performance of the IGBT chip.

Description

A trench gate IGBT chip

technical field

The invention relates to the field of semiconductor devices, in particular to a trench gate IGBT chip.

Background technique

At present, most IGBT manufacturers adopt trench gate structure technology to obtain lower power consumption, higher power density, and faster switching speed.

For trench gate IGBT chips, trench gate IGBT chips with dummy gates appear now in order to take into account the withstand voltage, power consumption and safe operating area performance of the chip. In the structure of the IGBT chip, the gate is divided into a normal gate and a dummy gate. Conventional gates are used for switch control, while virtual gates are used to improve chip performance (such as on-resistance, withstand voltage and safe operating area, etc.). A schematic cross-sectional view of a trench gate IGBT chip provided with a dummy gate is shown in FIG. 1 . The cell structure of the IGBT chip shown in FIG. 1 includes groove I, groove II and groove III, and these three grooves are evenly distributed inside the chip. Wherein, the inner side of the first trench is provided with an emitter, so the gate of the first trench is a conventional gate of the chip, while the second trench and the third trench are located outside the first trench, and the gate of the second trench is There are no emitters drawn on both sides of the third trench and the third trench, so the second trench and the third trench are the virtual gates of the chip.

In order to further improve the performance of the IGBT chip, one method is to increase the density of the dummy gate. Currently, the density of dummy gates can be increased through the following methods. The specific method is as follows:

Continue to increase the number of dummy gates on the outside of the conventional gate along the direction of the original dummy gate: In the case of constant cell size, increasing the number of dummy gates outside the conventional gate means that the process feature size becomes smaller, The minimum process size is bound to be limited by the manufacturing process and equipment. Therefore, there is a limit to the increase in the number of dummy gates, and the reduction of the process feature size will increase the process difficulty and cost of the IGBT chip.

However, increasing the trench density is a development direction of the current trench gate. Therefore, it is necessary to provide a new structure of the trench gate IGBT chip to realize the improvement of the trench gate of the IGBT chip without increasing the difficulty and cost of the process. slot density.

Contents of the invention

In view of this, the present invention provides a trench gate IGBT chip to further increase the trench density of the trench gate IGBT chip without increasing the difficulty and cost of the process.

In order to achieve the above-mentioned purpose of the invention, the present invention adopts following technical scheme:

A trench gate IGBT chip, comprising several cells connected in parallel, each cell comprising a trench gate I and a trench gate II, the trench gates are isolated by regions of the first conductivity type, so The second groove is located on one side of the first groove, and the other side of the gate of the first groove is provided with an emitter and a source region of the second conductivity type, and the emitter and the first The source region of the second conductivity type is located in the first conductivity type base region, and the trench gate IGBT chip further includes: a third trench gate formed in the first conductivity type region, the third trench gate The straight line where the gate length of the trench gate is located intersects the straight line where the gate length of the second trench gate is located; wherein, the first conductivity type is opposite to the second conductivity type.

Preferably, the II trench gate and the III trench gate are connected to each other.

Preferably, both the II trench gate and the III trench gate are multiple, and any one of the III trench gates is connected to at least two of the II trench gates.

Preferably, there are multiple III trench gates, and the distance between every two adjacent III trench gates is the same.

Preferably, there are multiple II trench gates, and the distance between every two adjacent II trench gates is the same.

Preferably, the trench widths of the trench gates are the same, and/or the trench depths of the trench gates are the same.

Preferably, the trench gate IGBT chip includes a substrate, the trench gate is formed inside the substrate, the trench gate includes polysilicon filled in the trench, the polysilicon and the substrate separated by an insulating layer.

Preferably, the polysilicon filled in the first trench gate is led out to the surface of the trench gate IGBT chip, and the polysilicon filled in the second trench II and the third trench is in a suspended state.

Preferably, the region of the first conductivity type is divided into several subregions of the first conductivity type, and each subregion of the first conductivity type is in a suspended state.

Preferably, there are multiple trench gates II and trench gate III, and the straight line where the gate length of the third trench gate is located intersects the straight line where the gate length of the second trench gate is located When forming a plurality of junctions, the plurality of junctions includes a plurality of first junctions and a plurality of second junctions, and at the first junctions, the third trench gate and the second trench gate are connected to each other connected, at the second junction, the III trench gate and the II trench gate are isolated from each other.

Preferably, there are multiple second intersections, the multiple second intersections are distributed in an array, and the shape of the array unit is a rectangle or a rhombus;

The length of one side of the rectangle is twice the distance between two adjacent trench gates II, and the length of the other side is twice the distance between two adjacent trench gates III;

The length of the long axis of the rhombus is 4 times the distance between two adjacent trench gates II, and the length of the short axis is 2 times the distance between two adjacent trench gates III, Or, the length of the long axis of the rhombus is 4 times the distance between the adjacent two third trench gates of the III, and the length of the short axis is 2 times the distance between the adjacent two trench gates of the II. times.

Preferably, the region of the first conductivity type is divided into several sub-regions of the first conductivity type, and the trench gate IGBT chip further includes: a lead-out window arranged at the second intersection, the lead-out window is used for Each sub-region of the first conductivity type around the second junction is led out to the surface of the chip.

Preferably, the extraction window region is a doped region of the first conductivity type, and the doping concentration of the doped region of the first conductivity type is greater than 5e19/cm ³ .

Preferably, openings are provided in the lead-out window region, and the openings are used to lead out each sub-region of the first conductivity type around the second junction to the chip surface.

Compared with the prior art, the present invention has the following beneficial effects:

The trench gate IGBT chip provided by the present invention includes the first trench gate, the second trench gate and the third trench gate, and the second trench gate and the third trench gate are both virtual gates of the IGBT chip . Compared with the trench gate IGBT chip structure in the prior art, the trench gate IGBT chip provided by the present invention adds a third trench gate, thereby increasing the trench density of the trench gate IGBT chip. Since the straight line where the gate length of the third trench gate is intersected with the straight line where the gate length of the second trench gate is, that is to say, the third trench gate is formed in a direction different from that of the second trench gate. Therefore, compared with the prior art, although the added III trench gate increases the trench density, it does not reduce the spacing between the II trench gates. Therefore, when preparing the trench gate IGBT chip provided by the present invention When , the existing process feature size can be used without reducing the process feature size. Therefore, compared with the prior art, the preparation of the trench gate IGBT chip provided by the present invention will not increase the difficulty and cost of the preparation process. In addition, due to the increased third trench gate, the trench density of the trench gate IGBT chip is increased, which is beneficial to improve the withstand voltage, power consumption and safe operating area performance of the IGBT chip.

Description of drawings

In order to clearly understand the technical solutions of the prior art and specific implementations of the present invention, a brief description will be given below of the drawings used in describing the prior art and specific implementations of the present invention. Apparently, these drawings are only some drawings of the embodiments of the present invention, and those of ordinary skill in the present invention can also obtain other drawings without creative work.

1 is a schematic cross-sectional structure diagram of a half-cell structure of a trench gate IGBT chip in the prior art;

2 is a schematic plan view of the half-cell structure of the trench gate IGBT chip provided by Embodiment 1 of the present invention;

Figure 3(a) and Figure 3(b) are schematic cross-sectional structure diagrams of the trench gate IGBT chip shown in Figure 2 along the x-x' direction and along the y-y' direction, respectively;

4 is a schematic plan view of the half-cell structure of the trench gate IGBT chip provided by Embodiment 2 of the present invention;

Figure 5(a) and Figure 5(b) are schematic cross-sectional structure diagrams of the trench gate IGBT chip shown in Figure 4 along the x-x' direction and along the y-y' direction, respectively;

6 is a schematic plan view of the cell structure of the trench gate IGBT chip provided by Embodiment 2 of the present invention;

Figure 7 is a schematic diagram of the flow of holes and electrons between the emitters of two adjacent cells when the IGBT chip is turned on;

FIG. 8 is a simplified schematic diagram of a dummy gate structure of a trench gate IGBT chip provided by Embodiment 3 of the present invention;

Fig. 9 (1) and Fig. 9 (2) are the partial enlargement diagrams of intersection I1 and I2 shown in Fig. 8;

10(1) to 10(3) are schematic diagrams of the distribution of the second junction on the chip.

detailed description

Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings.

It should be noted that the trench gate IGBT chip includes several parallel cells, and the structure of each cell is usually the same. The trench gate IGBT chip provided by the present invention mainly improves the cell structure of the chip. In order to highlight the improvements of the present invention, the specific embodiments of the present invention focus on the cellular structure of the IGBT chip and some structures related to the cellular structure, and other structures that are not directly related to the cellular structure are not described in detail in the embodiments of the present invention. introduce.

Embodiment one

Fig. 2 is a schematic plan view of the half-cell structure of the trench gate IGBT chip provided by Embodiment 1 of the present invention, and Fig. 3 (a) is the half-cell structure of the trench gate IGBT chip shown in Fig. 2 along x-x 'direction schematic cross-section, Figure 3 (b) is a half-cell structure of the trench gate IGBT chip shown in Figure 2 along the y-y' direction cross-sectional schematic.

It should be noted that the trench gate IGBT chip described in Embodiment 1 is described by taking an N-type substrate material as an example.

As shown in Figure 2, the half-cell structure of the trench gate IGBT chip provided by Embodiment 1 of the present invention includes the first trench gate 201 and the second trench gate 202, the first trench gate 201 and the second trench gate 202 are isolated by a P-type region 203 . The half-cell structure further includes an emitter 204 and an N+ source region 205, wherein the N+ source region 205 is located between the emitter 204 and the first trench 201. Wherein, the emitter 204 and the N+ source region 205 are located on one side of the first trench gate 201 , and the second trench gate 202 is located on the other side of the first trench gate 201 .

Referring to FIG. 3( a ) and FIG. 3( b ), the emitter 204 and the N+ source region 205 are disposed in the P-base region 206 .

As shown in FIG. 2 and FIG. 3( b ), the IGBT chip provided by the embodiment of the present invention further includes a third trench gate 207 . As shown in FIG. 2 , the line where the gate length of the third trench gate 207 is located intersects with the line where the gate length of the second trench gate 202 is located. That is to say, the direction of the gate length of the third trench gate 207 on the IGBT chip is not along the direction of the gate length of the second trench gate 202 on the IGBT chip, but intersects with the direction of the second trench gate 202 , Therefore, the arrangement of the third trench gate 202 will not reduce the pitch of the second trench gate 202 .

Continue referring to Fig. 3 (a) and shown in Fig. 3 (b), the polysilicon 301 in the 1st trench gate 201 is drawn to the chip surface by the polysilicon of chip surface, and one side of this 1st trench gate 201 is provided with emitter Pole and N+ source region, the first trench gate 201 is a conventional gate of the trench gate IGBT chip. However, the polysilicon 301 in the II trench gate 202 and the III trench gate 207 is not drawn to the chip surface, and the polysilicon in the two trenches is in a suspended state, so the II trench gate 202 and the III trench gate 207 are Floating grid. And there is no emitter around the II trench gate 202 and the III trench gate 207, so the II trench gate 202 and the III trench gate 207 are virtual gates of the IGBT chip.

It should be noted that, usually, in order to increase the density of dummy gate trenches, those skilled in the art usually arrange more dummy gate trenches in the same direction as the original dummy gate trenches. However, the present invention breaks through the common thinking of those skilled in the art, and sets more dummy gate trenches from another direction, so as to increase the trench density without reducing the trench spacing. This method of setting has significant improvements, as shown in:

1. Since the groove pitch is not reduced, the process feature size for preparing the IGBT chip is not reduced, so the number of added third trench gates is limited by the process feature size.

2. Compared with the prior art, the preparation of the trench gate IGBT chip provided by Embodiment 1 of the present invention will not increase the difficulty and cost of the process of the equipment.

3. Furthermore, existing equipment can be used to realize the preparation of IGBT chips with higher groove density.

4. In addition, since more dummy gate trenches are arranged in a different direction from the original dummy gate, this method of increasing the density of dummy gate trenches will not be limited by process feature size and cell size. Compared with the method in the prior art, the setting method can achieve a higher groove density.

3(a) and 3(b), the first trench gate 201, the second trench gate 202 and the third trench gate 207 are formed inside the substrate 300, and the three trench gates 201 , 202 and 207 all include polysilicon 301 filled in the trench, and the polysilicon 301 is isolated from the substrate 300 by an insulating layer 302, and the insulating layer 302 may be a silicon dioxide material.

In order to make the fabrication process of the chip easier to implement, it is preferable that the trenches of the first trench gate, the second trench gate and the third trench gate have the same trench depth and trench width.

In addition, in the embodiment of the present invention, as shown in FIG. 3(a) and FIG. 3(b), the doping concentration and junction depth of the P-type region 203 and the P-base region 206 are preferably the same.

It should be noted that, in the embodiment of the present invention, the straight line where the gate length of the third trench gate 207 and the straight line where the gate length of the second trench gate 202 is located are preferably vertically intersected. In addition, in the embodiment of the present invention, the straight line where the gate length of the third trench gate 207 intersects the line where the gate length of the second trench gate 202 intersects, which does not mean that the third trench gate 207 and the second trench gate The slot grids 202 are interconnected. Actually, in the embodiment of the present invention, the third trench gate 207 and the second trench gate 202 may or may not be connected together. When there are multiple II trench gates 202 , the III trench gates 207 may be selectively connected to part of the II trench gates 202 .

In addition, in order to enhance the conductance modulation effect of holes in the P-type region 203 when the chip is in the on state, the P-type region 203 used to isolate the trench gate is preferably in a floating state. That is, the P-type region 203 is not drawn out to the chip surface, and is not grounded, and the P-type region 203 is in a floating state in terms of electrical connection.

The structure of the trench gate IGBT chip described in the above embodiments is described by taking one II trench gate and one III trench gate as examples. Actually, in order to increase the trench density of the cell structure, there can be multiple trench gates II and trench gate III. Refer to Embodiment 2 for details.

Embodiment two

The cellular structure of the trench gate IGBT chip described in Embodiment 2 has many similarities with the cellular structure of the trench gate IGBT chip described in Embodiment 1. For the sake of brevity, this embodiment only has the differences Make an emphatic explanation.

Fig. 4 is a schematic plan view of the half-cell structure of the trench gate IGBT chip provided by Embodiment 2 of the present invention, and Fig. 5(a) is the half-cell structure of the trench gate IGBT chip shown in Fig. 4 along x-x 'direction schematic cross-section, Figure 5 (b) is shown in Figure 4 trench gate IGBT chip half-cell structure along the y-y' direction cross-sectional schematic.

As shown in FIG. 4 , the half-cell structure of the trench gate IGBT chip described in the second embodiment includes three II trench gates 202 and four III trench gates 207, and the II trench gates 202 are respectively These are the II-1 trench gate 2021 , the II-2 trench gate 2022 , and the II-3 trench gate 2023 . The III-th trench gates 207 are respectively the III-1st trench gate 2071 , the III-2th trench gate 2072 , the III-3rd trench gate 2073 , and the III-4th trench gate 2074 . In Embodiment 1 of the present invention, the distance d1 between every two adjacent trench gates II is preferably the same, and the distance d2 between every two adjacent trench gates III is also preferably the same. Further, the distance d1 between every two adjacent trench gates II and the distance d2 between every two adjacent trench gates III are preferably the same, and this structure can be used in the minimum line width process, The density of the trench gate is maximized. Therefore, it is beneficial to reduce the on-resistance of the chip and improve the withstand voltage performance of the chip.

In order to make the fabrication process of the chip more convenient, it is preferable that the trenches of the first trench gate, the second trench gate and the third trench gate have the same trench depth and trench width. And further preferably, the distance between any two adjacent trench gates II and any two adjacent trench gates III is equal. This is because, in this way, each trench can be under the same etching atmosphere, so the consistency of the process is very good. For example, the shape of the groove wall of each groove and the radian of the groove bottom of each groove are basically the same.

In the embodiment of the present invention, preferably, any third trench gate 207 is connected to at least two trench gates 202 II. In the planar structure shown in FIG. 4 , any III trench gate 207 is connected to three II trench gates 202 , so that the interconnection between the III trench gate 207 and the II trench gate 202 is realized.

It should be noted that when the third trench gate 207 is not provided on the IGBT chip, the P-type region 203 used to isolate the second trench gate 202 is an entire area, but when the IGBT chip is provided with the second trench gate 207 After the third trench gate 207 where the gates 202 are connected to each other, the second trench gate 202 and the third trench gate 207 form a network structure of dummy gates. FIG. 6 shows a schematic plan view of a cell structure of an IGBT chip with a trench gate II and a trench gate III. It can be seen from FIG. 6 that after the second trench gate 202 and the third trench gate 207 form a network structure of dummy gates, the P-type region 203 is divided into several isolated P-type sub-regions. It is easy to understand that adjacent P-type sub-regions are isolated from each other by the II trench gate 202 and the III trench gate 207 . That is, each P-type sub-region is surrounded by dummy gates and trench gates.

When all the P-type sub-regions are in the floating state, a stronger hole blocking effect can be formed when the chip is turned on. The specific reasons are as follows:

Fig. 7 is a schematic diagram of the flow of holes and electrons between the emitters of two adjacent cells when the IGBT chip is turned on. It can be seen from Figure 6 that when the chip is turned on, the holes injected from the back and the electrons injected from the channel merge in the N-base region to form conductance modulation and reduce the on-resistance. The greater the concentration of electron-hole pairs, the stronger the conductance modulation. From the movement path of holes, it can be seen that it is a curve, and it needs to bypass the trench gate to be extracted. It is this "wrapping" process (hole blocking) that causes holes to accumulate near the front surface of the chip, that is The hole concentration at the front surface of the chip is increased, and in order to maintain the charge balance, more electrons are injected from the channel, thus enhancing the conductance modulation. If there are multiple dummy gates between the emitters of the two cells, the movement route of the holes needs to bypass multiple dummy grids and then the conventional grids to be extracted. More holes can be accumulated, so the virtual gate can enhance the conductance modulation. Moreover, the greater the dummy gate trench density, the stronger the conductance modulation.

In addition, when all the P-type sub-regions are in the floating state, the electron depletion of the IGBT chip in reverse withstand voltage can be accelerated, so the withstand voltage performance of the chip can be improved. This is because: the dummy gate structure can reduce the electric field intensity of the suspended P-type sub-region. When the dummy gate structure is arranged in the IGBT chip, the electric field concentration phenomenon at the bottom of the conventional gate will be alleviated, thus helping to improve the withstand voltage performance of the chip. And the greater the density of the set dummy gate, the more obvious the improvement of the withstand voltage performance.

It should be noted that the IGBT chip described in the second embodiment above includes 3 trench gates II and 4 trench gates III. In fact, the above embodiment is only an example of the embodiment of the present invention, and should not It should be understood as a limitation to the embodiments of the present invention. In fact, IGBT chips including n (n≥1, n is an integer) number II trench gates and m (m≥1, m is an integer) number III trench gates are within the protection scope of the present invention.

The P-type region 203 in the IGBT chip described in the second embodiment above is divided into several mutually isolated P-type sub-regions, and these P-type sub-regions are all in a floating state. When the chip is turned on, it can enhance the conductance modulation effect and reduce the on-resistance, but when the chip is turned off, a large number of holes injected into the channel increase the extraction time, reduce the turn-off speed, increase the turn-off loss, and affect The safe operating area performance of the chip is guaranteed. In order to overcome the above defects, the present invention also provides a third embodiment.

Embodiment three

When the P-type sub-region is in a floating state, the turn-off speed will be reduced, and the turn-off loss will be increased, which will affect the performance of the safe working area of the chip. Therefore, it is necessary to lead out the P-type sub-region to the surface of the chip to realize an electrical ground connection. However, when the dummy gate trench gate forms a network structure, each P-type sub-region formed by division is isolated from each other. If each P-type sub-region is electrically connected to ground, according to the traditional method, it is necessary to connect each P-type sub-region to the ground. A lead-out window for leading the P-type sub-region to the chip surface is set on the suspended P-type sub-region, which will lead to a reduction in the number of grooves per unit area due to the existence of the lead-out window under the limitation of equipment and process level , that is, reducing the trench density, which is not conducive to reducing the on-resistance of the chip.

In order not to reduce the trench density of the trench gate IGBT chip described in the second embodiment, the third embodiment of the present invention provides a new structure of the trench gate IGBT chip.

The trench gate IGBT chip described in Embodiment 3 has many similarities with the trench gate IGBT chip described in Embodiment 2. For the sake of brevity, this embodiment only focuses on the differences. For similarities, please refer to the description of Embodiment 2.

In the embodiment of the present invention, the dummy gate structure formed by connecting the second trench gate 202 and the third trench gate 207 to each other is a mesh structure. It should be noted that, in the embodiment of the present invention, the III trench gate 207 is not connected to all the II trench gates 202 in the gate length direction, but is selectively connected to part of the II trench gate 202 connected together. The plan view and sectional view of the cell structure of the trench gate IGBT chip described in Embodiment 3 are basically the same as the plan view and sectional view of the cell structure of the IGBT chip described in Embodiment 2. For the sake of brevity, this embodiment will not For a detailed description of its plan view and section view, please refer to the accompanying drawings of Embodiment 2 for details.

In order to understand more clearly the dummy gate structure of the mesh structure in the embodiment of the present invention, the dummy gate structure is simplified as shown in FIG. 8 below. In the virtual gate structure shown in Figure 8, each straight line represents a trench gate, the straight line in the horizontal direction is the third trench gate, the straight line in the vertical direction is the second trench gate, and the extension direction of each straight line corresponds to The gate length direction of the trench. It can be seen from FIG. 8 that when the straight line representing the third trench gate intersects with the straight line representing the second trench gate, multiple intersections are formed, and these intersections are the junctions of the third trench gate and the second trench gate. In FIG. 8 , the blank area between the straight lines is the P-type region 203 on the IGBT chip, which is divided into several P-type sub-regions by the third trench gate.

It should be noted that, in the embodiment of the present invention, the junctions formed include a first junction and a second junction, and at the first junction, the third trench gate and the second trench gate are connected together, It is a real junction, and at the second junction, the third trench gate and the second trench gate are isolated from each other and not connected together, which is a virtual junction. In the structure shown in FIG. 8 , the junction marked with a triangle is the second junction, and the junction not marked with a triangle is the first junction.

In the embodiment of the present invention, a partial enlarged view of the first intersection I1 shown in FIG. 8 is shown in FIG. 9(1), and a partial enlarged view of the second intersection I2 is shown in FIG. 9(2).

In FIG. 9(1), the third trench gate and the second trench gate are connected together, and the four P-type sub-regions a, b, c, and d around the first junction are isolated from each other. These four P-type subregions are independent of each other.

At the position of the second junction shown in Figure 9 (2), the third trench gate and the second trench gate are not connected together, and the four P-type sub-regions a', b' around the second junction , c', d' are connected together at the second junction. That is to say, at the second intersection, the surrounding four P-type sub-regions a', b', c', d' form a local interconnection. In order to realize electrical ground connection for all the P-type sub-regions formed by division in the chip, the IGBT chip in Embodiment 3 of the present invention further includes: a lead-out window w arranged at the second junction. The lead-out window w can lead out the P-type sub-region around it to the surface of the chip to realize electrical grounding connection.

At the second intersection, since the four peripheral P-type sub-regions a', b', c', and d' form local interconnections, the P-type sub-regions a', b', c', and d' are An overall P-type region, therefore, the lead-out window w provided at the second junction can lead out the four P-type sub-regions a', b', c', d' to the chip surface. Compared with the solution in the prior art that each P-type sub-region requires a lead-out window, the IGBT chip provided by the embodiment of the present invention reduces the number of lead-out windows, and can achieve All P-type sub-regions lead out of the chip surface.

Continuing to refer to FIG. 9(2), the lead-out window w provided at the second intersection is not connected to the II trench gate and the III trench gate.

For the convenience of description, the trench gate II and the trench gate III are collectively referred to as dummy gates. As a specific embodiment of the present invention, the distance between the edge of the lead-out window w and the edge of the dummy gate trench gate is greater than or equal to that of the dummy gate. The width of the trench.

The shape of the lead-out window can be any shape. When the shape of the lead-out window is square, the side length of the lead-out window w is 2-4 times the width of the dummy gate trench. The lead-out window w is doped with high-concentration P+, and the doping concentration is greater than 5e19/cm ³ , so as to reduce the lead-out contact resistance. An opening w1 is provided in the center of the lead-out window w, through which the adjacent suspended P-type sub-regions are led out to the chip surface to facilitate grounding. In the embodiment of the present invention, the size of the set opening w1 is 50%-80% of the area of the lead-out window w.

It should be noted that the second junction may be any junction where the second trench gate and the third trench gate intersect. However, in order to use as few lead-out windows as possible to lead all the P-type sub-regions to the chip surface for ground connection, in the embodiment of the present invention, the position of the second intersection can make every four neighbors The P-type sub-regions form local interconnects. Further preferably, the distribution of the second junctions on the chip is an array distribution, wherein the shape of the array unit is a rectangle or a rhombus. When the lead-out window is set at the second intersection of such a distribution structure, it can be realized that every four adjacent P-type sub-regions share one lead-out window.

When the shape of the array unit is a rectangle, the schematic plan view of the dummy gate structure of the IGBT chip is shown in Figure 10 (1). At this time, the length of one side of the rectangle is between two adjacent II trench gates. 2 times the distance between the trench gates, and the length of the other side is 2 times the distance between two adjacent third trench gates. Further, when the distance between two adjacent trench gates II is equal to the distance between two adjacent trench gates III, the shape of the array unit is a square.

When the shape of the array unit is diamond, the schematic plan views of the dummy gate structure of the IGBT chip are shown in Fig. 10(2) and Fig. 10(3). When the shape of the array unit is the shape of the array unit as shown in Figure 10 (2), the major axis of the rhombus is parallel to the II groove grid, and at this moment, the major axis length of the rhombus is the length of the two adjacent II trench gates. 4 times the distance between trench gates, and the minor axis length is 2 times the distance between two adjacent third trench gates.

When the shape of the array unit is the array unit shown in Figure 10 (3), the long axis of the rhombus is parallel to the third trench grid, and at this time, the length of the long axis of the rhombus is the length of two adjacent third trench grids 4 times the distance between them, and the minor axis length is 2 times the distance between two adjacent II trench gates.

It should be noted that the IGBT chips described in Embodiments 1 to 3 above are all described with an N-type substrate material as an example. In fact, as an extended embodiment of the present invention, the IGBT chip may also use a P-type substrate material. When the IGBT chip is made of P-type material, the above-mentioned regions of various conductivity types need to be changed accordingly. Because the IGBT chip formed by the P-type substrate material and the IGBT chip formed by the N-type substrate material are only different in conductivity type, and the other structures are the same, those skilled in the art only need to change the conductivity type accordingly to obtain the P-type substrate material Therefore, for the sake of brevity, the IGBT chip formed on the P-type substrate will not be described in detail here.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be It is regarded as the protection scope of the present invention.

Claims (13)

1. A trench gate IGBT chip, comprising several cells connected in parallel, each cell comprising the I trench gate and the II trench gate, the trench gates are isolated by the first conductivity type region , the II groove is located on one side of the I groove, and an emitter and a source region of the second conductivity type are arranged on the other side of the I groove gate, and the emitter and the The source region of the second conductivity type is located in the base region of the first conductivity type, and it is characterized in that the trench gate IGBT chip further includes: a third trench gate formed in the region of the first conductivity type, so The straight line where the gate length of the third trench gate III is located intersects the straight line where the gate length of the second trench gate II is located; wherein, the first conductivity type is opposite to the second conductivity type; Both the II trench gate and the III trench gate are plural, and when the straight line where the gate length of the third trench gate is located intersects with the straight line where the gate length of the II trench gate is located, multiple trench gates are formed. a junction, the plurality of junctions includes a plurality of first junctions and a plurality of second junctions, at the first junctions, the third trench gate and the second trench gate are connected to each other, at At the second intersection, the third trench gate and the second trench gate are isolated from each other. 2 . The trench gate IGBT chip according to claim 1 , wherein the trench gate II and the trench gate III are connected to each other. 3. The trench gate IGBT chip according to claim 1, characterized in that, the II trench gate and the III trench gate are multiple, and any one of the III trench gates interconnected with at least two of the II trench gates. 4. The trench gate IGBT chip according to claim 1 or 2, characterized in that there are multiple third trench gates III, and the distance between every two adjacent trench gates III is the same. 5. The trench gate IGBT chip according to claim 1 or 2, characterized in that there are multiple second trench gates II, and the distance between every two adjacent trench gates II is the same. 6. The trench gate IGBT chip according to any one of claims 1-3, characterized in that the trench width of each of the trench gates is the same, and/or the trench depth of each of the trench gates same. 7. The trench gate IGBT chip according to any one of claims 1-3, wherein the trench gate IGBT chip comprises a substrate, the trench gate is formed inside the substrate, the The trench gate includes polysilicon filled in the trench, and the polysilicon is isolated from the substrate by an insulating layer. 8. The trench gate IGBT chip according to claim 7, characterized in that the polysilicon filled in the first trench gate is drawn to the surface of the trench gate IGBT chip, and filled in the second trench and the polysilicon in the third trench is in a suspended state. 9. The trench gate IGBT chip according to claim 3, wherein the region of the first conductivity type is divided into several subregions of the first conductivity type, and each subregion of the first conductivity type is in suspended state. 10. The IGBT chip according to claim 1, wherein there are multiple second junctions, the plurality of second junctions are distributed in an array, and the shape of the array unit is a rectangle or a rhombus; The length of one side of the rectangle is twice the distance between two adjacent trench gates II, and the length of the other side is twice the distance between two adjacent trench gates III; The length of the long axis of the rhombus is 4 times the distance between two adjacent trench gates II, and the length of the short axis is 2 times the distance between two adjacent trench gates III, Or, the length of the long axis of the rhombus is 4 times the distance between the adjacent two third trench gates of the III, and the length of the short axis is 2 times the distance between the adjacent two trench gates of the II. times. 11. The trench gate IGBT chip according to any one of claims 1-3, wherein the first conductivity type region is divided into several first conductivity type subregions, and the trench gate IGBT chip It also includes: an extraction window arranged at the second intersection, and the extraction window is used to extract each sub-region of the first conductivity type around the second intersection to the surface of the chip. 12. The trench gate IGBT chip according to claim 11, wherein the lead-out window region is a doped region of the first conductivity type, and the doping concentration of the doped region of the first conductivity type is greater than 5e19/cm ³ . 13. The trench gate IGBT chip according to claim 11, characterized in that openings are provided in the lead-out window region, and the openings are used to separate the first conductivity type sub-regions around the second junction out to the chip surface.