CN113496894A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
- Publication number
- CN113496894A CN113496894A CN202010252039.8A CN202010252039A CN113496894A CN 113496894 A CN113496894 A CN 113496894A CN 202010252039 A CN202010252039 A CN 202010252039A CN 113496894 A CN113496894 A CN 113496894A
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- gate structure
- isolation
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 135
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000002955 isolation Methods 0.000 claims abstract description 126
- 230000004888 barrier function Effects 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000000903 blocking effect Effects 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 claims description 256
- 239000000463 material Substances 0.000 claims description 124
- 239000003989 dielectric material Substances 0.000 claims description 28
- 239000011241 protective layer Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- -1 silicon carbide nitride Chemical class 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate; forming a plurality of fin structures on a substrate, wherein the fin structures comprise an effective area and an isolation area to be isolated, the effective area and the isolation area are distributed in a direction parallel to the surface of the substrate, the top surface of the effective area is provided with a first barrier layer, and the top surface of the isolation area to be isolated is provided with a second barrier layer; removing the first barrier layer; after the first blocking layer is removed, forming an initial pseudo gate structure on the substrate and on the fin portion structures, wherein the initial pseudo gate structure spans the fin portion structures, and the top of the initial pseudo gate structure is exposed out of the second blocking layer on the surface of the top of the to-be-isolated area; removing the second barrier layer on the top surface of the isolation region to be isolated; after removing the second barrier layer, removing part or all of the to-be-isolated area, and forming an isolation opening in the initial pseudo gate structure, wherein the bottom plane of the isolation opening is lower than or flush with the bottom plane of the initial pseudo gate structure; a first isolation structure is formed within the isolation opening. The method improves the performance of the semiconductor structure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
Fin field effect transistors (finfets) have been widely used in recent years because of their ability to effectively control short channel effects caused by device critical dimension scaling. In the fabrication of finfet, two masks are generally used for fabricating Poly-Si Dummy Gate (Poly-Si Dummy Gate), the first mask is used to form polysilicon lines after polysilicon deposition, and the second mask is used to cut the polysilicon lines. Compared with the method for manufacturing the polycrystalline silicon pseudo gate by using a single mask, the polycrystalline silicon pseudo gate manufactured by using double masks can obtain a rectangular pseudo gate outline (namely the tail end of a cut polycrystalline silicon wire is close to a right-angled rectangle instead of an arc), so that the gate graph can be better controlled, the density of a device is improved, and the performance of the device is improved.
However, as the device size is reduced, the method for fabricating the polysilicon dummy gate has many problems, and new methods are needed to improve the performance of the formed semiconductor structure.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of fin structures on a substrate, wherein the fin structures comprise an effective area and an isolation area to be isolated, the effective area and the isolation area are distributed in a direction parallel to the surface of the substrate, the top surface of the effective area is provided with a first barrier layer, and the top surface of the isolation area to be isolated is provided with a second barrier layer; removing the first barrier layer; after the first blocking layer is removed, forming an initial pseudo gate structure on the substrate and on the fin portion structures, wherein the initial pseudo gate structure spans the fin portion structures, and the top of the initial pseudo gate structure is exposed out of the second blocking layer on the surface of the top of the to-be-isolated area; after the initial pseudo gate structure is formed, removing the second barrier layer on the top surface of the isolation region to be isolated; after removing the second barrier layer, removing part or all of the region to be isolated, and forming an isolation opening in the initial pseudo gate structure, wherein the bottom plane of the isolation opening is lower than or flush with the bottom plane of the initial pseudo gate structure; a first isolation structure is formed within the isolation opening.
Optionally, the method for forming the fin structure includes: forming a fin material layer on a substrate; forming a barrier material layer on the fin material layer; forming a patterned mask layer on the barrier material layer; and etching the blocking material layer and the fin material layer by taking the patterned mask layer as a mask to form the fin structure, forming a first blocking layer on the top surface of the effective region, and forming a second blocking layer on the top surface of the to-be-isolated region.
Optionally, after forming a plurality of fin structures on the substrate and before removing the first blocking layer, the method further includes: and forming a second isolation structure on the substrate, wherein the second isolation structure is positioned on the partial side wall surface of the fin structure, and the top surface of the second isolation structure is lower than the top surface of the fin structure.
Optionally, a bottom plane of the isolation opening is lower than or flush with a top plane of the second isolation structure.
Optionally, the material of the first barrier layer includes a dielectric material, and the dielectric material includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride.
Optionally, the material of the second barrier layer includes a dielectric material, and the dielectric material includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride.
Optionally, the material of the first isolation structure includes a dielectric material, and the dielectric material includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride.
Optionally, after the forming of the initial dummy gate structure and before the removing of the second blocking layer, the method further includes: removing part of the initial dummy gate structure to form a dummy gate structure, wherein the top surface of the dummy gate structure is lower than that of the second barrier layer; and forming a protective layer on the top surface of the pseudo gate structure, wherein the protective layer exposes the top surface of the second barrier layer.
Optionally, the forming method of the protective layer includes: etching the initial pseudo gate structure back until part of the surface of the side wall of the second barrier layer is exposed to form a pseudo gate structure; forming a protective material layer on the top surface of the pseudo gate structure and the surface of the side wall and the top surface of the second barrier layer; and flattening the protective material layer until the top surface of the second barrier layer is exposed, and forming a protective layer on the top surface of the pseudo gate structure.
Optionally, the material of the protective layer is different from the material of the second barrier layer.
Optionally, the material of the protective layer includes a dielectric material, and the dielectric material includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride.
Optionally, the method for removing the first barrier layer includes: forming a patterned mask layer on the substrate, wherein the patterned mask layer exposes the top surface of the first barrier layer; and etching the first barrier layer by taking the patterned mask layer as a mask until the top surface of the fin structure is exposed.
Optionally, the initial dummy gate structure includes a dummy gate dielectric layer and a dummy gate layer located on a surface of the dummy gate dielectric layer.
Optionally, the material of the dummy gate layer includes polysilicon.
Optionally, the method for forming the initial dummy gate structure includes: forming a pseudo gate structure material layer on the substrate, wherein the pseudo gate structure material layer covers the top surface and the side wall surface of the fin structure and the top surface of the second barrier layer; and flattening the pseudo gate structure material layer until the top surface of the second barrier layer is exposed, and forming the initial pseudo gate structure on the substrate.
Optionally, after the forming the first isolation structure, the method further includes: forming a dielectric layer on a substrate, wherein the initial pseudo gate structure is positioned in the dielectric layer; removing the initial pseudo gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening.
Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the surface of the gate dielectric layer.
Optionally, the material of the gate layer includes a metal, and the metal includes one or more of tungsten, copper, titanium nitride, tantalum nitride, and aluminum.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the first barrier layer on the top surface of the effective region is removed, the initial pseudo gate structure is formed on the substrate, the second barrier layer on the top surface of the to-be-isolated region is exposed at the top of the initial pseudo gate structure, then the second barrier layer on the top surface of the to-be-isolated region is removed, part or all of the to-be-isolated region is removed, an isolation opening is formed in the initial pseudo gate structure, and then the first isolation structure is formed in the isolation opening. According to the method, the region to be isolated of the fin part structure is formed firstly, the initial pseudo gate structure is formed, and then the region to be isolated is removed, so that the first isolation structure is formed at the position of the region to be isolated, the forming position of the first isolation structure can be self-aligned, the situation that the subsequent gate-last process is affected after the position of the first isolation structure is deviated is avoided, the process flow is simplified, the production efficiency is improved, and the performance of the formed semiconductor structure is improved.
Further, after the forming of the initial dummy gate structure and before the removing of the second blocking layer, the method further includes: and removing part of the initial pseudo gate structure to form a pseudo gate structure, wherein the top surface of the pseudo gate structure is lower than that of the second barrier layer, and then forming a protective layer on the top surface of the pseudo gate structure, wherein the protective layer can protect the top surface of the pseudo gate structure and prevent the pseudo gate structure from being damaged in the subsequent process of removing the barrier layer and the second fin portion structure.
Drawings
FIGS. 1 and 2 are schematic top view and cross-sectional structure, respectively, of a semiconductor structure in one embodiment;
fig. 3 to 11 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the conventional method for fabricating the polysilicon dummy gate needs to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 and fig. 2 are a top view and a cross-sectional view of a semiconductor structure according to an embodiment.
Referring to fig. 1 and fig. 2, fig. 1 is a top view of fig. 2, and fig. 2 is a schematic cross-sectional view of fig. 1 along a section line AA ', wherein the section line AA' extends along a dummy gate structure, and includes: the semiconductor device comprises a substrate 100, wherein the substrate 100 comprises a first region I, a second region II and an isolation region III, the isolation region III is located between the first region I and the second region II, and fin structures 101 are arranged on the first region I and the second region II; a first dielectric layer 102 located on the substrate 100, wherein the first dielectric layer 102 is located on a sidewall of the fin structure 101 and lower than a top surface of the fin structure 101; a first dummy gate structure 103 located on the first region I, the first dummy gate structure 103 crossing over the fin structure 101; a second dummy gate structure 104 located on the second region II, the second dummy gate structure 104 crossing the fin structure 101; an isolation structure 105 located within isolation region III.
In the semiconductor structure, the isolation structure 105 is used for electrically isolating the first dummy gate structure 103 and the second dummy gate structure 104. In the process of forming the first dummy gate structure 103 and the second dummy gate structure 104, an initial dummy gate structure is formed first, the initial dummy gate structure crosses the fin structure, the initial dummy gate structure extends from the first region I to the second region II, a patterned mask is formed on the surface of the initial dummy gate structure, the initial dummy gate structure on the isolation region III is removed by using the patterned mask as the mask, so that the first dummy gate structure 103 is formed on the first region I, the second dummy gate structure 104 is formed on the second region II, and the isolation structure 105 is formed on the isolation region III.
However, as the size of the semiconductor structure is smaller and smaller, when a patterned mask is formed on the surface of the initial dummy gate structure to remove the initial dummy gate structure on the isolation region III, the dimensional accuracy of the patterned mask is smaller, and the accuracy requirement and the control difficulty of the optical alignment are increased, so that the position of the formed isolation structure 105 relative to the fin structure 101 is easily shifted and cannot be accurately located on the isolation region III, as shown by the region X in fig. 2, the position of the isolation structure 105 is shifted toward the first region I. In the subsequent metal gate replacement process, when the first dummy gate structure 103 and the second dummy gate structure 104 are removed, the distance between the isolation structure 105 and the fin structure 101 in the first region I is short, so that the first dummy gate structure 103 between the isolation structure 105 and the fin structure 101 is difficult to be removed completely, and after the gate structure is formed in the first region, due to the residue of the first dummy gate structure 103, the control capability of the gate structure on the fin structure is weaker than that of the metal gate structure, so that the switching speed of the gate structure is slowed down, and the performance of the semiconductor structure is affected.
In order to solve the above problems, a technical solution of the present invention provides a method for forming a semiconductor structure, in which a region to be isolated of a fin structure is formed first, and after an initial dummy gate structure is formed, the region to be isolated is removed, so that a first isolation structure is formed at a position of the region to be isolated, and thus a formation position of the first isolation structure can achieve more accurate optical alignment through a self-alignment effect, and a situation that a subsequent gate-last process is affected after the position of the first isolation structure is offset with respect to the fin structure is avoided, thereby simplifying a process flow, improving production efficiency, and improving performance of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 11 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 3, a substrate 200 is provided.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator.
Referring to fig. 4, a plurality of fin structures are formed on a substrate 200, the fin structures include an active region 201 and an isolation region to be isolated 202 distributed along a direction parallel to a surface of the substrate, a first barrier layer 203 is formed on a top surface of the active region 201, and a second barrier layer 204 is formed on a top surface of the isolation region to be isolated 202.
The forming method of the fin structure comprises the following steps: forming a fin material layer (not shown) on the substrate 200; forming a barrier material layer (not shown) on the fin material layer; forming a patterned mask layer (not shown) on the barrier material layer; and etching the blocking material layer and the fin material layer by taking the patterned mask layer as a mask to form the fin structure, forming a first blocking layer 203 on the top surface of the effective region 201, and forming a second blocking layer 204 on the top surface of the to-be-isolated region 202.
The fin structure is made of semiconductor materials such as monocrystalline silicon, polycrystalline silicon, germanium, silicon germanium, gallium arsenide or silicon on insulator; the material of the barrier material layer comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride.
In this embodiment, the material of the fin structure includes monocrystalline silicon; the material of the barrier material layer comprises silicon nitride.
The barrier material layer provides a material layer for the first barrier layer 203 and the second barrier layer 204. The first barrier layer 203 and the second barrier layer 204 are used for protecting the top surface of the fin structure from being damaged.
The process for forming the fin material layer comprises a physical vapor deposition process or an epitaxial growth process; the process for forming the barrier material layer comprises a chemical vapor deposition process, an atomic layer deposition process or a heat treatment process and the like; and the process for etching the barrier material layer and the fin material layer comprises one or more of a dry etching process and a wet etching process.
In this embodiment, the process of forming the fin material layer includes an epitaxial growth process; the process for forming the barrier material layer comprises a chemical vapor deposition process; the process for etching the blocking material layer and the fin material layer comprises a dry etching process, wherein the dry etching process can form a fin structure with a good sidewall appearance, a first blocking layer 203 and a second blocking layer 204, so that after the second blocking layer is removed and an isolation opening is formed in an isolation region, the first isolation structure formed in the isolation opening has good size uniformity, and can play a good isolation role, so that the performance uniformity of a subsequently formed semiconductor structure is good.
With continued reference to fig. 4, after the fin structure and the first and second barrier layers 203 and 204 are formed, a second isolation structure 205 is formed on the substrate 200, wherein the second isolation structure 205 is located on a portion of a sidewall surface of the fin structure and a top surface of the second isolation structure 205 is lower than a top surface of the fin structure.
The second isolation structure 205 is used for electrical isolation between a subsequently formed gate structure and the substrate 200.
The method for forming the second isolation structure 205 includes: forming a layer of isolation material (not shown) on the substrate 200; the isolation material layer is etched back to form the second isolation structure 205.
The material of the second isolation structure 205 is different from that of the blocking material layer, and the material of the second isolation structure 205 is different from that of the fin structure 201, so that when the second isolation structure 205 is etched back, the consumption of the etching back process on the basis of the material of the second isolation structure 205, the blocking material layer (the first blocking layer 203 and the second blocking layer 204) and the fin structure material is low, and the consumption of the exposed side wall surface of the fin structure is low, so that the top surface and the side wall surface of the fin structure can be protected from the damage of the etching back process of the second isolation structure 205.
The material of the second isolation structure 205 comprises a dielectric material comprising: silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride. The process for forming the isolating material layer comprises a chemical vapor deposition process, an atomic layer deposition process or a heat treatment process and the like.
In the present embodiment, the material of the second isolation structure 205 includes silicon oxide; the process of forming the layer of barrier material comprises a chemical vapor deposition process.
Referring to fig. 5, the first barrier layer 203 is removed.
The method for removing the first barrier layer 203 comprises the following steps: forming a patterned mask layer (not shown) on the substrate 200, the patterned mask layer exposing a top surface of the first barrier layer 203; and etching the first barrier layer 203 by using the patterned mask layer as a mask until the top surface of the fin structure is exposed.
The process for removing the first barrier layer 203 includes one or more of a dry etching process and a wet etching process.
In this embodiment, the process of removing the first barrier layer 203 includes a dry etching process.
The first blocking layer 203 on the top surface of the effective region 201 is removed, and the second blocking layer 204 on the top surface of the to-be-isolated region 202 is reserved, so that when an initial pseudo gate structure crossing a plurality of fin structures is formed on the substrate subsequently, the initial pseudo gate structure can expose the second blocking layer 204, the second blocking layer and the to-be-isolated region can be removed subsequently accurately, the subsequently-formed first isolation structure can be formed on the to-be-isolated region accurately, and the condition that the position of the first isolation structure is deviated to influence a subsequent gate-last process is avoided.
Referring to fig. 6, after removing the first blocking layer 203, an initial dummy gate structure 206 is formed on the substrate 200 and on the fin structures, the initial dummy gate structure crosses over a plurality of fin structures 201, and the top of the initial dummy gate structure 206 exposes the second blocking layer 204 on the top surface of the to-be-isolated region 202.
The initial dummy gate structure 206 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on a surface of the dummy gate dielectric layer.
The dielectric constant of the material of the pseudo gate dielectric layer is less than or equal to 3.7; the material of the dummy gate layer comprises polysilicon. In this embodiment, the material of the dummy gate dielectric layer includes silicon oxide; the material of the dummy gate layer comprises polysilicon.
The method for forming the initial dummy gate structure 206 includes: forming a dummy gate structure material layer (not shown) on the substrate 200, wherein the dummy gate structure material layer includes a dummy gate dielectric material layer and a dummy gate material layer located on the dummy gate dielectric material layer, and the dummy gate structure material layer covers the top surface and the sidewall surface of the fin structure and the top surface of the second barrier layer 204; planarizing the dummy gate structure material layer until the top surface of the second barrier layer 204 is exposed, forming the initial dummy gate structure 206 on the substrate 200.
The process for forming the pseudo gate dielectric material layer comprises a chemical vapor deposition process, an atomic layer deposition process or a heat treatment process; the process for forming the pseudo gate material layer comprises a physical vapor deposition process or an atomic layer deposition process; the process for flattening the pseudo grid structure material layer comprises a chemical mechanical polishing process or an etching back process.
In this embodiment, the process of forming the dummy gate dielectric material layer includes an atomic layer deposition process; the process for forming the dummy gate material layer comprises a physical vapor deposition process; the process for planarizing the dummy gate structure material layer includes a chemical mechanical polishing process.
The material of the second blocking layer 204 is different from the material of the dummy gate structure material layer, so that the process of planarizing the dummy gate structure material layer can be stopped on the surface of the second blocking layer 204, the planarization process can damage the second blocking layer 204 less, the second blocking layer 204 on the top surface of the region to be isolated 202 can be exposed at the top of the initial dummy gate structure 206, the second blocking layer on the top surface of the region to be isolated can be removed subsequently, the region to be isolated can be further removed, a subsequent first isolation structure can be accurately located at the position of the region to be isolated, and the situation that the position of the first isolation structure is shifted to influence the performance of a subsequently formed gate structure can be avoided.
Referring to fig. 7, a portion of the initial dummy gate structure 206 is removed to form a dummy gate structure 207, wherein a top surface of the dummy gate structure 207 is lower than a top surface of the second blocking layer 204.
The method for forming the dummy gate structure 207 includes: and etching back the initial dummy gate structure 206 until part of the sidewall surface of the second barrier layer 204 is exposed, thereby forming a dummy gate structure 207.
A portion of the initial dummy gate structure 206 is removed for providing a space for subsequently forming a protection layer on the top surface of the dummy gate structure 207.
With continued reference to fig. 7, a protection layer 208 is formed on the top surface of the dummy gate structure 207, and the protection layer 208 exposes the top surface of the second barrier layer 204.
The forming method of the protective layer 208 includes: forming a protective material layer (not shown) on the top surface of the dummy gate structure 207 and on the sidewall surface and the top surface of the second barrier layer 204; planarizing the protection material layer until the top surface of the second barrier layer 204 is exposed, and forming a protection layer 208 on the top surface of the dummy gate structure 207.
The protective layer 208 is used for protecting the dummy gate structure 207, so as to prevent the dummy gate structure 207 from being damaged when the second blocking layer and the region to be isolated are subsequently removed, and prevent the height of the subsequently formed gate structure from being affected when the dummy gate structure is subsequently removed to form the gate structure.
The material of the protective layer 208 is different from the material of the second barrier layer 204. The material of the protective layer 208 is different from that of the second barrier layer 204, so that when the protective layer 208 is formed by flattening the protective material layer, the second barrier layer 204 is less damaged by the flattening process, the second barrier layer can be removed subsequently, the region to be etched is removed, and the first isolation structure can be accurately positioned on the region to be isolated.
The material of the protective layer 208 comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. In the present embodiment, the material of the protective layer 208 includes silicon carbide nitride.
In other embodiments, the protective layer can not be formed.
Referring to fig. 8, after forming the dummy gate structure 207, the second blocking layer 204 on the top surface of the region to be isolated 202 is removed, and an initial isolation opening 209 is formed, wherein the initial isolation opening 209 exposes the top surface of the region to be isolated 202.
The process for removing the second barrier layer 204 includes one or more of a dry etching process and a wet etching process.
In this embodiment, the process of removing the second barrier layer 204 includes a dry etching process.
The material of the protection layer 208 is different from that of the second barrier layer 204, so that when the second barrier layer 204 is removed, the protection layer 208 is less damaged, and thus the protection layer 208 can protect the dummy gate structure 207 from being damaged in a subsequent process of removing the region to be isolated 202.
Referring to fig. 9, after removing the second blocking layer 204, removing a part or all of the to-be-isolated region 202, and forming an isolation opening 210 in the initial dummy gate structure 207, wherein a bottom plane of the isolation opening 210 is lower than or flush with a bottom plane of the dummy gate structure 207.
The process for removing part or all of the region to be isolated 202 includes one or more of a dry etching process and a wet etching process.
In this embodiment, the process of removing part or all of the to-be-isolated area 202 includes a dry etching process, and the dry etching process has a better directionality, so that the isolation opening 210 with a better sidewall morphology and a controllable size can be formed, and the situation that the size of the formed isolation opening 210 is not controllable due to lateral etching in the process of etching the to-be-isolated area 202, and the position of the first isolation structure formed in the isolation opening 210 subsequently is not controllable is avoided.
The bottom plane of the isolation opening 210 is lower than or flush with the bottom plane of the dummy gate structure 207, and the bottom plane of the isolation opening 210 is lower than or flush with the top plane of the second isolation structure 205, so that the isolation opening 210 completely exposes the sidewall surface of the dummy gate structure 207, and a first isolation structure formed in the isolation opening subsequently can isolate a subsequently formed gate structure, so that the semiconductor structure has good performance.
Referring to fig. 10, a first isolation structure material layer 211 is formed in the isolation opening 210.
The first isolation structure material layer 211 provides a material layer for a subsequently formed first isolation structure.
The process of forming the first isolation structure material layer 211 in the isolation opening 210 includes an atomic layer deposition process or a chemical vapor deposition process.
In this embodiment, the process of forming the first isolation structure material layer 211 in the isolation opening 210 includes an atomic layer deposition process, and the atomic layer deposition process can form the first isolation structure material layer 211 with a dense structure in the isolation opening 210 with a smaller size, so as to avoid a situation that the subsequently formed first isolation structure has more defects and thus a poor isolation effect is caused.
The material of the first isolation structure material layer 211 comprises a dielectric material comprising one or a combination of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbonitride.
In this embodiment, the material of the first isolation structure material layer 211 includes silicon oxide.
In this embodiment, the region to be isolated 202 of the fin structure is formed first, and the region to be isolated 202 is removed after the initial dummy gate structure is formed, so that the first isolation structure 212 is formed at the position of the region to be isolated 202, and thus the formation position of the first isolation structure 212 can be self-aligned, thereby avoiding the situation that the subsequent gate-last process is affected after the position of the first isolation structure 212 is shifted, simplifying the process flow, improving the production efficiency, and improving the performance of the formed semiconductor structure.
Referring to fig. 11, after forming the first isolation structure material layer 211, a dielectric layer (not shown) is formed on the substrate 200, wherein the dummy gate structure 207 is located in the dielectric layer; removing the dummy gate structure 207 and forming a gate opening (not shown) in the dielectric layer; a gate structure 213 is formed within the gate opening.
The forming method of the dielectric layer comprises the following steps: forming a dielectric material layer (not shown) on the substrate, the dielectric material layer covering the top surface of the dummy gate structure 207; and planarizing the dielectric material layer, the first isolation material layer 211 and the protection layer 208 until the top surface of the dummy gate structure 207 is exposed, so as to form the dielectric layer and form the first isolation structure 212.
The material of the dielectric layer comprises a dielectric material, and the dielectric material comprises one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride and silicon carbonitride; the process for forming the dielectric material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the dielectric layer includes silicon oxide; the process for forming the dielectric material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can quickly form the dielectric material layer with thicker thickness and dense structure.
The gate structure 213 includes a gate dielectric layer (not shown) and a gate layer (not shown) on the surface of the gate dielectric layer.
In this embodiment, the gate structure 213 further includes: and the gate electrode layer is positioned on the surface of the work function layer.
In other embodiments, the work function layer can be excluded.
The gate dielectric layer is made of a high-K (dielectric constant is larger than 3.9) material, and the high-K material comprises hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal comprising a combination of one or more of tungsten, copper, titanium nitride, tantalum nitride, and aluminum.
In this embodiment, the material of the gate dielectric layer includes hafnium oxide; the material of the gate layer comprises tungsten.
The material of the work function layer comprises a P-type work function material or an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
In the semiconductor structure formed by the method, the first isolation structure 212 is formed at the position of the region to be isolated 202, so that the forming position of the first isolation structure 212 can be self-aligned, and the influence on the subsequent gate-last process after the position of the first isolation structure 212 is shifted is avoided, thereby simplifying the process flow, improving the production efficiency, and improving the performance of the formed semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of fin structures on a substrate, wherein the fin structures comprise an effective area and an isolation area to be isolated, the effective area and the isolation area are distributed in a direction parallel to the surface of the substrate, the top surface of the effective area is provided with a first barrier layer, and the top surface of the isolation area to be isolated is provided with a second barrier layer;
removing the first barrier layer;
after the first blocking layer is removed, forming an initial pseudo gate structure on the substrate and on the fin portion structures, wherein the initial pseudo gate structure spans the fin portion structures, and the top of the initial pseudo gate structure is exposed out of the second blocking layer on the surface of the top of the to-be-isolated area;
after the initial pseudo gate structure is formed, removing the second barrier layer on the top surface of the isolation region to be isolated;
after removing the second barrier layer, removing part or all of the region to be isolated, and forming an isolation opening in the initial pseudo gate structure, wherein the bottom plane of the isolation opening is lower than or flush with the bottom plane of the initial pseudo gate structure;
a first isolation structure is formed within the isolation opening.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming a fin structure comprises: forming a fin material layer on a substrate; forming a barrier material layer on the fin material layer; forming a patterned mask layer on the barrier material layer; and etching the blocking material layer and the fin material layer by taking the patterned mask layer as a mask to form the fin structure, forming a first blocking layer on the top surface of the effective region, and forming a second blocking layer on the top surface of the to-be-isolated region.
3. The method of claim 1, wherein after forming the plurality of fin structures on the substrate and before removing the first barrier layer, further comprising: and forming a second isolation structure on the substrate, wherein the second isolation structure is positioned on the partial side wall surface of the fin structure, and the top surface of the second isolation structure is lower than the top surface of the fin structure.
4. The method of claim 3, wherein a bottom plane of the isolation opening is lower than or flush with a top plane of the second isolation structure.
5. The method of forming a semiconductor structure of claim 1, wherein the material of the first barrier layer comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride.
6. The method of forming a semiconductor structure of claim 1, wherein the material of the second barrier layer comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride.
7. The method of forming a semiconductor structure of claim 1, wherein the material of the first isolation structure comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride.
8. The method of forming a semiconductor structure of claim 1, wherein after forming the initial dummy gate structure and before removing the second barrier layer, further comprising: removing part of the initial dummy gate structure to form a dummy gate structure, wherein the top surface of the dummy gate structure is lower than that of the second barrier layer; and forming a protective layer on the top surface of the pseudo gate structure, wherein the protective layer exposes the top surface of the second barrier layer.
9. The method of forming a semiconductor structure of claim 8, wherein the method of forming the protective layer comprises: etching the initial pseudo gate structure back until part of the surface of the side wall of the second barrier layer is exposed to form a pseudo gate structure; forming a protective material layer on the top surface of the pseudo gate structure and the surface of the side wall and the top surface of the second barrier layer; and flattening the protective material layer until the top surface of the second barrier layer is exposed, and forming a protective layer on the top surface of the pseudo gate structure.
10. The method of claim 8, wherein a material of the passivation layer is different from a material of the second barrier layer.
11. The method of forming a semiconductor structure of claim 10, wherein the material of the protective layer comprises a dielectric material comprising a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride.
12. The method of forming a semiconductor structure of claim 1, wherein removing the first barrier layer comprises: forming a patterned mask layer on the substrate, wherein the patterned mask layer exposes the top surface of the first barrier layer; and etching the first barrier layer by taking the patterned mask layer as a mask until the top surface of the fin structure is exposed.
13. The method of forming a semiconductor structure of claim 1, wherein the initial dummy gate structure comprises a dummy gate dielectric layer and a dummy gate layer on a surface of the dummy gate dielectric layer.
14. The method of forming a semiconductor structure of claim 13, wherein a material of the dummy gate layer comprises polysilicon.
15. The method of forming a semiconductor structure of claim 13, wherein the method of forming the initial dummy gate structure comprises: forming a pseudo gate structure material layer on the substrate, wherein the pseudo gate structure material layer covers the top surface and the side wall surface of the fin structure and the top surface of the second barrier layer; and flattening the pseudo gate structure material layer until the top surface of the second barrier layer is exposed, and forming the initial pseudo gate structure on the substrate.
16. The method of forming a semiconductor structure of claim 1, further comprising, after forming the first isolation structure: forming a dielectric layer on a substrate, wherein the initial pseudo gate structure is positioned in the dielectric layer; removing the initial pseudo gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening.
17. The method of forming a semiconductor structure of claim 16, wherein the gate structure comprises a gate dielectric layer and a gate layer on a surface of the gate dielectric layer.
18. The method of claim 17, wherein the gate layer comprises a material comprising a metal comprising a combination of one or more of tungsten, copper, titanium nitride, tantalum nitride, and aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010252039.8A CN113496894B (en) | 2020-04-01 | 2020-04-01 | Method for forming semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010252039.8A CN113496894B (en) | 2020-04-01 | 2020-04-01 | Method for forming semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113496894A true CN113496894A (en) | 2021-10-12 |
| CN113496894B CN113496894B (en) | 2024-04-19 |
Family
ID=77994258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010252039.8A Active CN113496894B (en) | 2020-04-01 | 2020-04-01 | Method for forming semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113496894B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023179411A1 (en) * | 2022-03-22 | 2023-09-28 | 华为技术有限公司 | Semiconductor device and preparation method therefor, and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9418994B1 (en) * | 2015-03-26 | 2016-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd | Fin field effect transistor (FinFET) device structure |
| CN107887272A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10074571B1 (en) * | 2017-03-07 | 2018-09-11 | Globalfoundries Inc. | Device with decreased pitch contact to active regions |
| CN109560136A (en) * | 2017-09-26 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20200075423A1 (en) * | 2018-08-31 | 2020-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Method of Forming Same |
-
2020
- 2020-04-01 CN CN202010252039.8A patent/CN113496894B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9418994B1 (en) * | 2015-03-26 | 2016-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd | Fin field effect transistor (FinFET) device structure |
| CN107887272A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10074571B1 (en) * | 2017-03-07 | 2018-09-11 | Globalfoundries Inc. | Device with decreased pitch contact to active regions |
| CN109560136A (en) * | 2017-09-26 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20200075423A1 (en) * | 2018-08-31 | 2020-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Method of Forming Same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023179411A1 (en) * | 2022-03-22 | 2023-09-28 | 华为技术有限公司 | Semiconductor device and preparation method therefor, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113496894B (en) | 2024-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220328356A1 (en) | Mechanisms for Forming FinFET Device | |
| US10541238B2 (en) | FinFET and fabrication method thereof | |
| US10062787B2 (en) | FinFET | |
| US10121852B2 (en) | Structure and process to tuck fin tips self-aligned to gates | |
| US11456216B2 (en) | Fabrication method of semiconductor structure | |
| US10784342B1 (en) | Single diffusion breaks formed with liner protection for source and drain regions | |
| CN113496894B (en) | Method for forming semiconductor structure | |
| CN113838934B (en) | Semiconductor structure and forming method thereof | |
| CN110739265B (en) | Semiconductor structure and forming method thereof | |
| US10727136B2 (en) | Integrated gate contact and cross-coupling contact formation | |
| CN110752153B (en) | Semiconductor structure and forming method thereof | |
| CN113314605A (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN109087892B (en) | Semiconductor structure, forming method thereof and forming method of fin field effect transistor | |
| CN109285889B (en) | Semiconductor structure and forming method thereof | |
| CN113851535A (en) | Semiconductor device and method of forming the same | |
| CN113745113B (en) | Semiconductor device and method of forming the same | |
| US20220208987A1 (en) | Semiconductor structure and fabrication method thereof | |
| CN113113486B (en) | Semiconductor device and method of forming the same | |
| CN112652578B (en) | Method for forming semiconductor structure and transistor | |
| US20220238517A1 (en) | Semiconductor structure and fabrication method thereof | |
| EP4358153A1 (en) | Semiconductor transistor | |
| US20230387261A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN108155148B (en) | Method for forming semiconductor structure | |
| CN112951912A (en) | Semiconductor structure and forming method thereof | |
| CN117476764A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |