CN117476764A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117476764A
CN117476764A CN202210871125.6A CN202210871125A CN117476764A CN 117476764 A CN117476764 A CN 117476764A CN 202210871125 A CN202210871125 A CN 202210871125A CN 117476764 A CN117476764 A CN 117476764A
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China
Prior art keywords
gate
forming
layer
source
etching stop
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王彦
涂武涛
邱晶
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210871125.6A priority Critical patent/CN117476764A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, wherein the method for forming comprises: providing a substrate, wherein the substrate comprises a base and a plurality of fin structures positioned on the base; forming a dummy gate crossing the fin structure on the substrate; forming source-drain epitaxial regions in the substrate at two sides of the dummy gate; forming an etching stop layer on the surface of the exposed source-drain epitaxial region; forming an interlayer dielectric layer on the surface of the pseudo gate and the surface of the etching stop layer on the substrate; removing the pseudo gate and forming a gate opening in the interlayer dielectric layer; forming a gate within the gate opening; and forming a grid cutting opening which is positioned in the grid and the interlayer dielectric layer between the adjacent fin structures, wherein the grid cutting opening penetrates through the grid along the extending direction perpendicular to the grid. The semiconductor structure and the forming method thereof improve the cutting process window of the grid electrode, reduce the damage to the device structure and improve the reliability of the device.

Description

Semiconductor structure and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.
Background
As semiconductor technology advances, the size of semiconductor devices continues to decrease. In recent years, in order to achieve smaller device sizes and higher device integration, field effect transistor devices are gradually transitioning from planar transistor structures to fin transistor structures with better electrical performance.
Important components of the fin transistor structure comprise a fin structure, a gate structure and source-drain epitaxial regions, wherein the gate structure spans the top of the fin structure and part of the side wall surface, and the source-drain epitaxial regions are positioned on the fin structure at two sides of the gate structure. In addition, in order to avoid the mutual influence between the transistor structures, a cutting channel is generally formed by cutting the gate structure, so that the gate structure is separated into a plurality of units isolated from each other, thereby realizing the mutual isolation of the transistor structures.
However, in the prior art, during the process of cutting the gate structure, the cutting process window is small, and the device structure in the transistor is easily damaged, resulting in a decrease in the device reliability.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, improving a cutting process window in the process of cutting a grid structure, reducing the damage to the device structure and improving the reliability of the device.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a plurality of fin structures and a bottom isolation structure, wherein the substrate comprises a base, the fin structures are positioned on the base, and the bottom isolation structure is positioned between the fin structures, and the height of the bottom isolation structure is lower than that of the fin structures; the grid structure spans the fin part structure and comprises a grid and side walls positioned at two sides of the grid; source and drain epitaxial regions in the substrate on both sides of the gate structure; the etching stop layer is positioned on the surface of the source-drain epitaxial region; the interlayer dielectric layer is positioned on the surface of the grid structure and the etching stop layer; the gate cutting opening is positioned in the gate structure and the interlayer dielectric layer, penetrates through the gate structure along the extending direction perpendicular to the gate structure, is positioned between adjacent fin structures, and the bottom surface of the gate cutting opening is lower than the top surface of the source-drain epitaxial region.
Optionally, the etching selectivity ratio of the material of the interlayer dielectric layer to the material of the etching stop layer is greater than 50:1.
correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a base, a plurality of fin structures positioned on the base and a bottom isolation structure positioned between the fin structures, and the height of the bottom isolation structure is lower than that of the fin structures; forming a dummy gate crossing the fin structure and side walls positioned on two sides of the dummy gate on the substrate; forming source-drain epitaxial regions in the substrate at two sides of the dummy gate; forming an etching stop layer on the surface of the exposed source drain epitaxial region; forming an interlayer dielectric layer on the surface of the pseudo gate and the surface of the etching stop layer on the substrate; removing the dummy gate and forming a gate opening in the interlayer dielectric layer; forming a gate within the gate opening; and forming a gate cutting opening in the gate and interlayer dielectric layer between the adjacent fin structures, wherein the gate cutting opening penetrates through the gate along the extending direction perpendicular to the gate, and the bottom surface of the gate cutting opening is lower than the top surface of the source-drain epitaxial region.
Optionally, the etching selectivity ratio of the interlayer dielectric layer to the etching stop layer is greater than 50:1.
optionally, the material of the etching stop layer includes aluminum nitride or aluminum oxide.
Optionally, the method for forming the etching stop layer includes: depositing an etching stop material layer on the surface of the source-drain epitaxial region, the surface of the dummy gate and the surface of the substrate; and etching the etching stop material layer by adopting directional etching treatment until the etching stop material layer on the side wall and the top surface of the dummy gate is removed, so as to form the etching stop layer.
Optionally, the method for directional etching treatment includes: forming an initial sacrificial layer on the surface of the etching stop material layer, wherein the top surface of the initial sacrificial layer is higher than the surface of the etching stop material layer; thinning the initial sacrificial layer to form a sacrificial layer, wherein the sacrificial layer exposes the etching stop material layers on the side wall surfaces and the top surfaces of the pseudo gates, and the sacrificial layer covers the substrate and the etching stop material layers on the surfaces of the source-drain epitaxial regions; and etching the side wall of the dummy gate and the etching stop material layer on the top surface.
Optionally, the deposition process of the etching stop material layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
Optionally, the extending direction of the fin structure is a first direction, the extending direction of the gate is a second direction, and the extending direction of the gate cutting opening is a third direction; the first direction is perpendicular to the second direction, and the second direction is perpendicular to the third direction.
Optionally, the thickness of the etching stop layer ranges from 30 angstroms to 50 angstroms.
Optionally, the method for forming the gate includes: depositing an initial gate within the gate opening; and flattening the initial grid until the surface of the interlayer dielectric layer is exposed, so as to form the grid.
Optionally, the method for forming the gate cutting opening includes: forming a mask layer on the surfaces of the grid electrode and the interlayer dielectric layer, wherein part of the surface of the grid electrode and the surface of the interlayer dielectric layer are exposed by the mask layer; and etching the grid electrode and the interlayer dielectric layer by taking the mask layer as a mask so as to form a grid electrode cutting opening.
Optionally, the gate cutting opening is located between adjacent fin structures, and the gate cutting opening is located between adjacent source-drain epitaxial regions.
Optionally, the gate cutting opening exposes a portion of the etch stop layer on the surface of the source drain epitaxial region.
Optionally, the width dimension of the gate cutting opening ranges from 20 nanometers to 30 nanometers.
Optionally, the distance between adjacent fin structures is in the range of 50 nm to 80 nm.
Optionally, the distance between adjacent source and drain epitaxial regions is in the range of 30-50 nanometers.
Optionally, the forming process of the source-drain epitaxial region comprises a selective epitaxial growth process.
Optionally, the material of the gate includes a metal; the interlayer dielectric layer is made of silicon oxide.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, before the grid electrode cutting opening is formed, the etching stop layer is formed on the exposed surface of the source drain epitaxial region, so that the etching stop layer is used as a protective layer on the surface of the source drain epitaxial region in the process of forming the grid electrode cutting opening in the interlayer dielectric layer and the grid electrode, when the width dimension of the grid electrode cutting opening is relatively close to the interval between adjacent source drain epitaxial regions, the etching selection between the interlayer dielectric layer and the etching stop layer is relatively large due to the existence of the etching stop layer, the forming process of the grid electrode cutting opening can be stopped on the etching stop layer, the damage to the source drain epitaxial region is avoided, the process window for forming the grid electrode cutting opening is improved, and the integrity and the reliability of a device are improved.
In the semiconductor structure provided by the technical scheme of the invention, the etching stop layer is arranged on the surface of the source-drain epitaxial region of the semiconductor structure, so that the etching stop layer is used as a protective layer on the surface of the source-drain epitaxial region, and the damage of a grid cutting opening to the source-drain epitaxial region is avoided, thereby improving the integrity and the reliability of a device.
Drawings
FIG. 1 is a schematic diagram of a process for forming a semiconductor structure;
fig. 2 to 13 are schematic structural views of a process for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the prior art, the dicing process window is smaller in the process of dicing the gate structure, and the device structure in the transistor is easily damaged, resulting in a decrease in the device reliability.
Fig. 1 is a schematic structure diagram of a semiconductor structure forming process.
Referring to fig. 1, a substrate (not shown) is provided, the substrate including a base (not shown) and a plurality of fin structures 100 on the base; forming a gate structure 101 crossing the fin structure 100, source-drain epitaxial regions 102 in the substrate at two sides of the gate structure 101 and an interlayer dielectric layer 103 surrounding the fin structure 100, the gate structure 101 and the source-drain epitaxial regions 102 on the substrate; a gate cut opening 104 is formed between adjacent fin structures 100 in the gate structure 101 and the interlayer dielectric layer 103, the gate cut opening 104 cutting off the gate structure 101.
In this embodiment, the pitch of adjacent source-drain epitaxial regions 102 is smaller than the pitch of adjacent fin structures 100.
In this embodiment, the formation process of the source drain epitaxial region 102 includes a selective epitaxial growth process.
Since the source-drain epitaxial region 102 is formed by selective epitaxial growth, the size of the source-drain epitaxial region 102 is generally larger than the size of the fin structure 101, so that the pitch of adjacent source-drain epitaxial regions 102 is smaller than the pitch of adjacent fin structures 100. During the formation of the gate cut openings 104, the gate cut openings 104 are easily contacted with the source and drain epitaxial regions 102 on both sides, thereby causing damage to the source and drain epitaxial regions 102, resulting in reduced device reliability.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, before forming a gate cutting opening, an etching stop layer and an interlayer dielectric layer positioned on the etching stop layer are formed on the exposed surface of a source-drain epitaxial region, and in the process of subsequently forming the gate cutting opening positioned in a gate and interlayer dielectric layer, the etching stop layer is used as a protective layer on the surface of the source-drain epitaxial region, so that the damage to the source-drain epitaxial region is avoided, a process window in the process of forming the gate cutting opening is improved, and the integrity and reliability of a device are improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic structural views of a process for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate (not shown) is provided, the substrate including a base (not shown), and a plurality of fin structures 250 on the base; forming a dummy gate 201 across the fin structure 250 on the substrate; source-drain epitaxial regions 203 are formed in the substrate on either side of the dummy gate 201.
Materials for the substrate include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate is silicon.
In this embodiment, the substrate further includes: a bottom isolation structure (not shown) between each fin structure 250, the bottom isolation structure having a height that is lower than the height of the fin structure 250.
In this embodiment, after the dummy gate 201 is formed, the sidewall material layer 251 is formed on the sidewall surface of the dummy gate 201 and the top surface of the dummy gate 201.
The method for forming the source-drain epitaxial region 203 comprises the following steps: after forming the sidewall material layer 251, etching fin structures 250 on two sides of the sidewall material layer 251 to form source and drain openings (not shown); source drain extension regions 203 are formed within the source drain openings.
In this embodiment, the top of the source-drain epitaxial region 203 is flush with the top of the fin structure 250.
In this embodiment, the forming process of the source-drain epitaxial region 203 includes a selective epitaxial growth process.
And then, forming an etching stop layer on the exposed surface of the source-drain epitaxial region 203. Specifically, the step of forming the etching stop layer is shown in fig. 3 and 4.
Referring to fig. 3, an etching stop material layer 210 is deposited on the surface of the source-drain epitaxial region 203, the surface of the sidewall material layer 251 on the dummy gate 201, and the surface of the substrate.
The etch stop material layer 210 provides a starting material for a subsequently formed etch stop layer.
The deposition process of the etch stop material layer 210 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 4, the etching stop material layer 210 is etched by using a directional etching process until the etching stop material layer 210 on the sidewall and top surfaces of the dummy gate 201 is removed, so as to form an etching stop layer 211 covering the surface of the source drain epitaxial region 203.
In the subsequent process of forming the gate cutting opening, the etching stop layer 211 is used as a protective layer on the surface of the source-drain epitaxial region 203, so that the forming process of the gate cutting opening can stop on the etching stop layer 211, and the damage to the source-drain epitaxial region 203 is avoided, thereby improving the process window for forming the gate cutting opening and improving the integrity and reliability of the device.
In this embodiment, the thickness of the etching stop layer 211 is in the range of 30 angstrom to 50 angstrom.
In this embodiment, the material of the etching stop layer 211 includes aluminum nitride or aluminum oxide.
In this embodiment, the etching stop layer 211 is also located on the substrate surface.
The directional etching process can remove the etching stop material layer 210 on the side wall and the top of the dummy gate 201 on the basis of retaining the etching stop material layer 210 on the surface of the substrate and the surface of the source drain epitaxial region 203, thereby forming an etching stop layer 211 covering the surface of the source drain epitaxial region 203 and the substrate.
Specifically, the method for directional etching treatment comprises the following steps: forming an initial sacrificial layer (not shown) on the surface of the etching stop material layer 210, wherein the top surface of the initial sacrificial layer is higher than the surface of the etching stop material layer 210; thinning the initial sacrificial layer to form a sacrificial layer (not shown) which exposes the etch stop material layer 210 of the sidewall surface and the top surface of the dummy gate 201, and which covers the substrate and the etch stop material layer 210 of the surface of the source drain epitaxial region 203; the etch stop material layer 210 of the sidewalls and top surface of the dummy gate 201 is etched.
In this embodiment, the material of the initial sacrificial layer comprises a carbonaceous material.
After the etching stop layer 211 is formed, the sacrificial layer is removed.
Referring to fig. 5 to 8, fig. 5 is a schematic cross-sectional view along AA ' of fig. 8, fig. 6 is a schematic cross-sectional view along BB ' of fig. 8, fig. 7 is a schematic cross-sectional view along CC ' of fig. 8, and fig. 8 is a top view along P of fig. 5, fig. 6, and fig. 7.
Forming an interlayer dielectric layer 221 on the surface of the dummy gate 201 and the surface of the etching stop layer 211 on the substrate, wherein the etching selectivity ratio of the interlayer dielectric layer 221 to the etching stop layer 211 is greater than 50:1, a step of; removing the dummy gate 201, and forming a gate opening (not shown) in the interlayer dielectric layer 221; a gate 220 is formed within the gate opening.
In this embodiment, the etching selectivity ratio of the gate 220 to the etching stop layer 211 is greater than 30:1.
because the etching selectivity of the interlayer dielectric layer 221 and the etching stop layer 211 is relatively large, and the etching selectivity of the gate 220 and the etching stop layer 211 is relatively large, in the process of subsequently etching the interlayer dielectric layer 221 and the gate 220 to form the gate cutting opening, the etching stop layer 211 is used as a protective layer on the surface of the source-drain epitaxial region 203, so that the forming process of the gate cutting opening can stop on the etching stop layer 211, the damage to the source-drain epitaxial region 203 is avoided, the process window for forming the gate cutting opening is improved, and the integrity and reliability of the device are improved.
In this embodiment, the material of the gate 220 includes a metal; the material of the interlayer dielectric layer 221 includes silicon oxide.
In this embodiment, before removing the dummy gate 201, the sidewall material layer 251 on the surface of the dummy gate 201 is removed, so that the sidewall material layer 251 on the sidewall of the dummy gate 201 becomes the sidewall 202.
In this embodiment, the method for forming the gate 220 includes: depositing an initial gate (not shown) within the gate opening after forming the gate opening; and flattening the initial gate until the interlayer dielectric layer 221 and the surface of the side wall 202 are exposed to form a gate 220.
With continued reference to fig. 8, in this embodiment, since the source-drain epitaxial region 203 is formed by a selective epitaxial growth process, the width dimension of the source-drain epitaxial region 203 is greater than the width dimension of the fin structure 250. The width dimension refers to a dimension parallel to the substrate surface and perpendicular to an extension direction of the fin structure 250.
In this embodiment, the cross-sectional pattern of the source-drain epitaxial region 203 along the CC' direction is polygonal.
In this embodiment, since the width of the source-drain epitaxial region 203 is greater, the distance between adjacent fin structures 250 is greater than the distance between adjacent source-drain epitaxial regions 203.
Specifically, the distance between adjacent fin structures 250 located on the substrate 200 ranges from 50 nanometers to 80 nanometers.
The distance between adjacent source drain epitaxial regions 203 ranges from 30 nanometers to 50 nanometers.
In this embodiment, the extending direction of the fin structure 250 is a first direction, and the extending direction of the gate 220 is a second direction. The first direction is perpendicular to the second direction.
It should be noted that, for ease of understanding, the interlayer dielectric layer 221 and the etch stop layer 211 are omitted in fig. 8, and only the relative positions of the source-drain epitaxial region 203, the gate 220, and the fin structure 250 on the substrate 200 are shown.
Next, a gate cutting opening is formed between adjacent fin structures 250 in the gate 220 and the interlayer dielectric layer 221, the gate cutting opening penetrates the gate 220 along the extending direction perpendicular to the gate 220, and the bottom surface of the gate cutting opening is lower than the top surface of the source-drain epitaxial region 203.
Specifically, the step of forming the gate cutting opening is shown in fig. 9 to 13.
Please refer to fig. 9 and 10, wherein the view direction of fig. 9 coincides with the view direction of fig. 6, and the view direction of fig. 10 coincides with the view direction of fig. 7.
An initial mask layer 230 and an upper mask structure 231 on the initial mask layer 230 are formed on the surfaces of the gate 220 and the interlayer dielectric layer 221, and a portion of the initial mask layer 230 is exposed by the upper mask structure 231.
The initial mask layer 230 provides a raw material for a subsequently formed mask layer.
In this embodiment, the material of the initial mask layer 230 includes silicon nitride or silicon oxide.
The upper mask structure 231 is used to define a specific pattern of gate cutting openings to be formed later.
In this embodiment, the material of the upper mask structure 231 includes silicon nitride or silicon oxide.
In other embodiments, the material of the upper mask structure includes photoresist.
Please refer to fig. 11 to 13 on the basis of fig. 9 and 10, wherein fig. 11 is a top view of fig. 12 and 13 along the Q direction, fig. 12 is a schematic cross-sectional view of fig. 11 along the DD 'direction and fig. 12 is consistent with the view direction of fig. 9, and fig. 13 is a schematic cross-sectional view of fig. 11 along the EE' direction and fig. 13 is consistent with the view direction of fig. 10.
Etching the initial mask layer 230 by taking the upper mask structure 231 as a mask to form a mask layer 232 positioned on the surfaces of the gate 220 and the interlayer dielectric layer 221, wherein the mask layer 232 exposes a part of the surfaces of the gate 220 and the interlayer dielectric layer 221; the gate 220 and the interlayer dielectric layer 221 are etched using the mask layer 232 as a mask to form a gate cutting opening 240.
Specifically, the gate cutting openings 240 are located between adjacent fin structures 250, the gate cutting openings 240 are located between adjacent source-drain epitaxial regions 203, and bottom surfaces of the gate cutting openings 240 are lower than top surfaces of the source-drain epitaxial regions 203.
The extending direction of the gate 220 is a second direction, and the extending direction of the gate cutting opening 240 is a third direction, and the second direction is perpendicular to the third direction.
In this embodiment, the width of the gate cutting opening 240 ranges from 20 nm to 30 nm.
With continued reference to fig. 13, in the process of etching the interlayer dielectric layer 221 and the gate 220 to form the gate cutting opening 240, since the width dimension of the gate cutting opening 240 is closer to the spacing between the adjacent source-drain epitaxial regions 203, the source-drain epitaxial regions 203 are more likely to be affected by the process of forming the gate cutting opening 240. However, the surface of the source-drain epitaxial region 203 is covered with the etching stop layer 211, and the etching selectivity of the interlayer dielectric layer 221 and the etching stop layer 211 is relatively large, and the etching selectivity of the gate 220 and the etching stop layer 211 is relatively large, so that the process window of the etching process is relatively large, and the etching effect is relatively good.
In this embodiment, the gate cutting opening 240 exposes a portion of the etching stop layer 211 on the surface of the source-drain epitaxial region 203.
In the process of etching the interlayer dielectric layer 221 between the source-drain epitaxial regions 203, even if the width dimension of the gate cutting opening 240 is greater than the distance between the adjacent source-drain epitaxial regions 203, the etching stop layer 211 is provided on the surface of the source-drain epitaxial region 203 as a protection layer, so that the forming process of the gate cutting opening 240 can stop on the etching stop layer 211, and then the gate cutting opening 240 is formed on the surface of the etching stop layer 211 in a self-aligned manner, thereby effectively avoiding the damage to the source-drain epitaxial region 203, improving the process window for forming the gate cutting opening 240, and improving the integrity and reliability of the device.
In this embodiment, the material of the etching stop layer 211 includes aluminum nitride or aluminum oxide. Aluminum nitride or aluminum oxide may enable the etching selectivity ratio of the interlayer dielectric layer 221 to the etching stop layer 211 to be greater than 50:1 aluminum nitride or aluminum oxide is far more effective as an etch stop layer 211 than silicon nitride and silicon oxide used as conventional etch stop layer 211 materials. Therefore, the etching stop layer 211 in this embodiment can well avoid the source-drain epitaxial region 203 from being affected by the process of forming the gate cutting opening 240, thereby expanding the process window.
In addition, in the subsequent process, a source-drain connection structure (not shown) located on the source-drain epitaxial region 203 is formed, and in the etching process included in the source-drain connection structure forming process, due to the existence of the etching stop layer 211, the etching process can be stopped on the surface of the etching stop layer 211, so that damage to the source-drain epitaxial region 203 caused by over-etching is avoided, and the integrity and reliability of the device are improved.
In this embodiment, since the surface of the source-drain epitaxial region 203 is covered with the etching stop layer 211 and the surface of the fin structure 250 surrounded by the gate 220 has no etching stop layer 211, the bottom of the gate cutting opening 240 between the source-drain epitaxial region 203 is located on the etching stop layer 211 and the bottom of the gate cutting opening 240 between the fin structures 250 is lower than the top surface of the substrate 200.
In this embodiment, during the process of forming the gate cutting opening 240, the thickness of the mask layer 232 is reduced to a certain extent.
Correspondingly, the embodiment of the invention also provides a semiconductor structure formed by adopting the method.
With continued reference to fig. 11-13, the semiconductor structure includes: a substrate (not labeled) comprising a base 200, a number of fin structures 250 on the base 200, and a bottom isolation structure (not shown) between each fin structure 250, the bottom isolation structure having a height lower than the fin structures 250; a gate structure (not shown) crossing the fin structure 250, the gate structure including a gate 250 and side walls (not shown) located on both sides of the gate 250; source drain epitaxial regions 203 in the substrate on either side of the gate structure; the etching stop layer 211 is positioned on the surface of the source-drain epitaxial region 203; the interlayer dielectric layer 221 is located on the surface of the gate structure and the etching stop layer 211, and the etching selectivity ratio of the interlayer dielectric layer 221 to the etching stop layer 211 is greater than 50:1, a step of; a gate cutting opening 240 located in the gate structure and the interlayer dielectric layer 221, the gate cutting opening 240 penetrating the gate structure along an extending direction perpendicular to the gate structure, the gate cutting opening 240 being located between adjacent fin structures 250, and a bottom surface of the gate cutting opening 240 being lower than a top surface of the source-drain epitaxial region 203.
In this embodiment, the material of the etching stop layer 211 includes aluminum nitride or aluminum oxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a plurality of fin structures and a bottom isolation structure, wherein the substrate comprises a base, the fin structures are arranged on the base, the bottom isolation structure is arranged between the fin structures, and the height of the bottom isolation structure is lower than that of the fin structures; the grid structure spans the fin part structure and comprises a grid and side walls positioned at two sides of the grid;
source and drain epitaxial regions in the substrate on both sides of the gate structure;
the etching stop layer is positioned on the surface of the source-drain epitaxial region;
the interlayer dielectric layer is positioned on the surface of the grid structure and the etching stop layer;
the gate cutting opening is positioned in the gate structure and the interlayer dielectric layer, penetrates through the gate structure along the extending direction perpendicular to the gate structure, is positioned between adjacent fin structures, and the bottom surface of the gate cutting opening is lower than the top surface of the source-drain epitaxial region.
2. The semiconductor structure of claim 1, wherein an etch selectivity of a material of the interlayer dielectric layer to a material of the etch stop layer is greater than 50:1.
3. a method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a base, a plurality of fin structures positioned on the base and a bottom isolation structure positioned between the fin structures, and the height of the bottom isolation structure is lower than that of the fin structures;
forming a dummy gate crossing the fin structure and side walls positioned on two sides of the dummy gate on the substrate;
forming source-drain epitaxial regions in the substrate at two sides of the dummy gate;
forming an etching stop layer on the surface of the exposed source drain epitaxial region;
forming an interlayer dielectric layer on the surface of the pseudo gate and the surface of the etching stop layer on the substrate;
removing the dummy gate and forming a gate opening in the interlayer dielectric layer;
forming a gate within the gate opening;
and forming a gate cutting opening in the gate and interlayer dielectric layer between the adjacent fin structures, wherein the gate cutting opening penetrates through the gate along the extending direction perpendicular to the gate, and the bottom surface of the gate cutting opening is lower than the top surface of the source-drain epitaxial region.
4. The method of forming a semiconductor structure as claimed in claim 3, wherein an etch selectivity of the interlayer dielectric layer to the etch stop layer is greater than 50:1.
5. the method of forming a semiconductor structure of claim 3, wherein the material of the etch stop layer comprises aluminum nitride or aluminum oxide.
6. The method of forming a semiconductor structure of claim 3, wherein the method of forming an etch stop layer comprises: depositing an etching stop material layer on the surface of the source-drain epitaxial region, the surface of the dummy gate and the surface of the substrate; and etching the etching stop material layer by adopting directional etching treatment until the etching stop material layer on the side wall and the top surface of the dummy gate is removed, so as to form the etching stop layer.
7. The method of forming a semiconductor structure of claim 6, wherein the method of directional etching process comprises: forming an initial sacrificial layer on the surface of the etching stop material layer, wherein the top surface of the initial sacrificial layer is higher than the surface of the etching stop material layer; thinning the initial sacrificial layer to form a sacrificial layer, wherein the sacrificial layer exposes the etching stop material layers on the side wall surfaces and the top surfaces of the pseudo gates, and the sacrificial layer covers the substrate and the etching stop material layers on the surfaces of the source-drain epitaxial regions; and etching the side wall of the dummy gate and the etching stop material layer on the top surface.
8. The method of claim 6, wherein the deposition process of the etch stop material layer comprises a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
9. The method of claim 3, wherein an extension direction of the fin structure is a first direction, an extension direction of the gate is a second direction, and an extension direction of the gate cutting opening is a third direction; the first direction is perpendicular to the second direction, and the second direction is perpendicular to the third direction.
10. The method of forming a semiconductor structure of claim 3, wherein the etch stop layer has a thickness in the range of 30 angstroms to 50 angstroms.
11. The method of forming a semiconductor structure of claim 3, wherein the method of forming a gate electrode comprises: depositing an initial gate within the gate opening; and flattening the initial grid until the surface of the interlayer dielectric layer is exposed, so as to form the grid.
12. The method of forming a semiconductor structure of claim 3, wherein the method of forming a gate cut opening comprises: forming a mask layer on the surfaces of the grid electrode and the interlayer dielectric layer, wherein part of the surface of the grid electrode and the surface of the interlayer dielectric layer are exposed by the mask layer; and etching the grid electrode and the interlayer dielectric layer by taking the mask layer as a mask so as to form a grid electrode cutting opening.
13. The method of claim 3, wherein the gate cut openings are located between adjacent fin structures and the gate cut openings are located between adjacent source-drain epitaxial regions.
14. The method of claim 3, wherein the gate cut opening exposes a portion of the etch stop layer on the surface of the source drain extension region.
15. The method of forming a semiconductor structure of claim 3, wherein a width dimension of said gate cut opening ranges from 20 nanometers to 30 nanometers.
16. The method of claim 3, wherein a distance between adjacent fin structures is in a range of 50 nm to 80 nm.
17. The method of forming a semiconductor structure of claim 3, wherein a distance between adjacent source drain epitaxial regions is in a range of 30 nm to 50 nm.
18. The method of forming a semiconductor structure of claim 3, wherein said source drain epitaxial region forming process comprises a selective epitaxial growth process.
19. The method of forming a semiconductor structure of claim 3, wherein a material of the gate comprises a metal; the interlayer dielectric layer is made of silicon oxide.
CN202210871125.6A 2022-07-22 2022-07-22 Semiconductor structure and forming method thereof Pending CN117476764A (en)

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